National Instruments AT-MIO E Series Operating and maintenance manual

DAQ
AT-MIO E Series Register-Level
Programmer Manual
Multifunction I/O Boards for the PC AT
AT-MIO E Series RLPM
August 1998 Edition
Part Number 340747C-01

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©Copyright 1995, 1998 National Instruments Corporation. All rights reserved.

Important Information
Warranty
The media on which you receive National Instruments software are warranted not to fail to execute programming
instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced
by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not
execute programming instructions if National Instruments receives notice of such defects during the warranty period.
National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.
A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside
of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs
of returning to the owner parts which are covered by warranty.
National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed
for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to
make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should
consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages
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Product and company names listed are trademarks or trade names of their respective companies.
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and safety in medical or clinical treatment.

© National Instruments Corporation v AT-MIO E Series RLPM
Contents
About This Manual
Organization of This Manual.........................................................................................ix
Conventions Used in This Manual.................................................................................x
Related Documentation..................................................................................................xi
Customer Communication.............................................................................................xi
Chapter 1
General Description
General Characteristics..................................................................................................1-1
Chapter 2
Theory of Operation
Functional Overview......................................................................................................2-1
ISA Bus Interface Circuitry...........................................................................................2-6
Analog Input and Timing Circuitry ...............................................................................2-8
Analog Input Circuitry ....................................................................................2-8
Data Acquisition Timing Circuitry..................................................................2-11
Single-Read Timing..........................................................................2-11
Data Acquisition Sequence Timing ..................................................2-12
Posttrigger and Pretrigger Acquisition............................................................2-18
Analog Triggering..........................................................................................................2-19
Analog Output and Timing Circuitry.............................................................................2-19
Analog Output Circuitry..................................................................................2-20
Analog Output Timing Circuitry.....................................................................2-22
Single-Point Output...........................................................................2-22
Waveform Generation.......................................................................2-22
Digital I/O Circuitry.......................................................................................................2-23
Timing I/O Circuitry......................................................................................................2-24
RTSI Bus Interface Circuitry.........................................................................................2-25
Chapter 3
Register Map and Descriptions
Register Map..................................................................................................................3-1
Register Sizes ..................................................................................................3-4
Register Descriptions.....................................................................................................3-4
Misc Register Group........................................................................................3-4
Serial Command Register .................................................................3-5

Contents
AT-MIO E Series RLPM vi
© National Instruments Corporation
Misc Command Register ..................................................................3-6
Status Register..................................................................................3-7
Analog Input Register Group..........................................................................3-8
ADC FIFO Data Register.................................................................3-8
Configuration Memory Low Register ..............................................3-10
Configuration Memory High Register..............................................3-12
Analog Output Register Group .......................................................................3-16
AO Configuration Register...............................................................3-16
DAC FIFO Data Register.................................................................3-18
DAC0 Direct Data Register..............................................................3-19
DAC1 Direct Data Register..............................................................3-20
DMA Control Register Group.........................................................................3-21
Strobes Register................................................................................3-21
Channel A Mode Register ................................................................3-22
Channel B Mode Register.................................................................3-23
Channel C Mode Register.................................................................3-24
AI AO Select Register......................................................................3-25
G0 G1 Select Register ......................................................................3-26
DIO Register Group........................................................................................3-26
DAQ-STC Register Group..............................................................................3-27
FIFO Strobe Register Group...........................................................................3-27
Configuration Memory Clear Register.............................................3-27
ADC FIFO Clear Register................................................................3-27
DAC FIFO Clear Register................................................................3-27
Chapter 4
Programming
Plug and Play Initialization ...........................................................................................4-2
Windowing Registers ....................................................................................................4-4
Programming Examples ................................................................................................4-4
Digital I/O......................................................................................................................4-5
Example 1 .......................................................................................................4-5
Example 2 .......................................................................................................4-6
Analog Input..................................................................................................................4-6
Example 1 .......................................................................................................4-7
Example 2 .......................................................................................................4-10
Example 3 .......................................................................................................4-12
Example Program .............................................................................4-13
Example 4 .......................................................................................................4-15
Example 5 .......................................................................................................4-18
Example 6 .......................................................................................................4-20
Example 7 .......................................................................................................4-22

Contents
© National Instruments Corporation vii AT-MIO E Series RLPM
Example 8........................................................................................................4-24
Example 9........................................................................................................4-26
Analog Output................................................................................................................4-29
Example 1........................................................................................................4-30
Example 2........................................................................................................4-31
Example 3........................................................................................................4-36
Example 4........................................................................................................4-38
Example 5........................................................................................................4-40
Example Program..............................................................................4-40
General-Purpose Counter/Timer....................................................................................4-42
Example 1........................................................................................................4-42
Example 2........................................................................................................4-44
Example 3........................................................................................................4-46
RTSI Trigger Lines Programming Considerations........................................................4-48
Analog Triggering..........................................................................................................4-49
Interrupt Programming ..................................................................................................4-52
DMA Programming.......................................................................................................4-53
Single Channel Versus Dual Channel DMA...................................................4-54
Chapter 5
Calibration
EEPROM.........................................................................................................5-1
Calibration DACs............................................................................................5-8
NI-DAQ Calibration Function.........................................................................5-9
Appendix A
OKI MSM82C55A Data Sheet
Appendix B
Customer Communication
Glossary
Index
Figures
Figure 2-1. AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Block Diagram2-1
Figure 2-2. AT-MIO-16E-10 and AT-MIO-16DE-10 Block Diagram....................2-2
Figure 2-3. AT-MIO-16XE-10 Block Diagram.......................................................2-3

Contents
AT-MIO E Series RLPM viii
© National Instruments Corporation
Figure 2-4. AT-AI-16XE-10 Block Diagram..........................................................2-4
Figure 2-5. AT-MIO-16XE-50 Block Diagram.......................................................2-5
Figure 2-6. ISA Bus Interface Circuitry Block Diagram.........................................2-6
Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram .............2-8
Figure 2-8. ADC Timing .........................................................................................2-11
Figure 2-9. Timing of Scan in Example 1 ...............................................................2-13
Figure 2-10. Multirate Scanning of Two Channels...................................................2-14
Figure 2-11. Multirate Scanning of Two Channels with 1:xSampling Rate.............2-15
Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate ......... 2-15
Figure 2-13. Multirate Scanning of Three Channels with 4:2:1 Sampling Rate ....... 2-15
Figure 2-14. Multirate Scanning without Ghost........................................................2-16
Figure 2-15. Occurrences of Conversion on Channel 1 in Example 3. ..................... 2-16
Figure 2-16. Successive Scans Using Ghost.............................................................. 2-17
Figure 2-17. Analog Output Circuitry Block Diagram..............................................2-20
Figure 2-18. DAQ-STC Counter Diagram ................................................................2-24
Figure 2-19. RTSI Bus Interface Circuitry Block Diagram ...................................... 2-25
Figure 4-1. Analog Trigger Structure......................................................................4-50
Figure 4-2. DMA Structure......................................................................................4-53
Figure 5-1. EEPROM Read Timing ........................................................................ 5-2
Figure 5-2. Calibration DAC Write Timing ............................................................5-9
Tables
Table 1-1. Features of the AT E Series Boards......................................................1-2
Table 2-1. Analog Input Configuration Memory ..................................................2-17
Table 3-1. AT E Series Register Map ...................................................................3-2
Table 3-2. AT E Series Windowed Register Map..................................................3-3
Table 3-3. PGIA Gain Selection.............................................................................3-11
Table 3-4. Calibration Channel Assignments.........................................................3-13
Table 3-5. Differential Channel Assignments .......................................................3-14
Table 3-6. Nonreferenced Single-Ended Channel Assignments ...........................3-14
Table 3-7. Referenced Single-Ended Channel Assignments..................................3-15
Table 3-8. Channel Assignments............................................................................3-16
Table 5-1. AT-MIO-16E-1, AT-MIO-16E-2, AT-MIO-64E-3 EEPROM Map ... 5-2
Table 5-2. AT-MIO-16E-10 and AT-MIO-16DE-10 EEPROM Map ..................5-4
Table 5-3. AT-MIO-16XE-50 EEPROM Map ......................................................5-5
Table 5-4. AT-MIO-16XE-10 and AT-AI-16XE-10 EEPROM Map....................5-7

© National Instruments Corporation ix AT-MIO E Series RLPM
About This Manual
This manual describes the registers and register map of the AT E Series
boards and contains information concerning their register-level
programming.
The DAQ-STC, a National Instruments system timing controller ASIC, is
the timing engine that drives the AT E Series boards. Consequently, the
timing and programming sections in this manual repeat certain information
from, or draw your attention to, sections in the DAQ-STC Technical
Reference Manual. You must use your register-level programmer manual
along with the DAQ-STC Technical Reference Manual for a complete
understanding of AT E Series board programming.
Unless otherwise noted, text applies to all boards in the AT E Series.
The AT E Series boards are:
• AT-MIO-16E-1
• AT-MIO-16E-2
• AT-MIO-64E-3
• AT-MIO-16E-10
• AT-MIO-16DE-10
• AT-MIO-16XE-10
• AT-AI-16XE-10
• AT-MIO-16XE-50
The AT E Series boards are high-performance multifunction analog,
digital, and timing I/O boards for the IBM PC AT series computers.
Supported functions include analog input, analog output, digital I/O, and
timing I/O.
Organization of This Manual
The AT-MIO E Series Register-Level Programmer Manual is organized as
follows:
• Chapter 1, General Description, describes the general characteristics
of the AT E Series boards.
• Chapter 2, Theory of Operation, contains a functional overview of the
AT E Series board and explains the operation of each functional unit
making up the AT E Series boards.

About This Manual
AT-MIO E Series RLPM x
© National Instruments Corporation
• Chapter 3, Register Map and Descriptions, describes in detail the
address and function of each of the AT E Series control and status
registers.
• Chapter 4, Programming, contains programming instructions for
operating the circuitry on the AT E Series board.
• Chapter 5, Calibration, explains how to calibrate the analog input and
output sections of the AT E Series boards by reading calibration
constants from the EEPROM and writing them to the calibration
DACs.
• Appendix A, OKI MSM82C55A Data Sheet, contains a manufacturer
data sheet for the MSM82C55A CMOS programmable peripheral
interface (OKI Semiconductor).
• Appendix B, Customer Communication, contains forms for you to
complete to help you communicate with National Instruments about
our products.
• The Glossary contains an alphabetical list and description of terms
used in this manual, including acronyms, abbreviations, metric
prefixes, mnemonics, and symbols.
• The Index alphabetically lists topics covered in this manual, including
the page where you can find the topic.
Conventions Used in This Manual
The following conventions are used in this manual:
<> Angle brackets containing numbers separated by an ellipsis represent a
range of values associated with a bit, port, or signal name (for example,
ACH<0..7> stands for ACH0 through ACH7).
This icon to the left of bold italicized text denotes a note, which alerts you
to important information.
bold italic Bold italic text denotes a note, caution, or warning.
italic Italic text denotes variables, emphasis, a cross reference, or an introduction
to a key concept. This font also denotes text from which you supply the
appropriate word or value, as in NI-DAQ 6.x.

About This Manual
© National Instruments Corporation xi AT-MIO E Series RLPM
monospace Text in this font denotes text or characters that you should literally enter
from the keyboard, sections of code, programming examples, and syntax
examples. This font is also used for the proper names of disk drives, paths,
directories, programs, subprograms, subroutines, device names, functions,
operations, variables, filenames and extensions, and for statements and
comments taken from programs.
PC PC refers to the IBM PC AT and compatible computers.
Related Documentation
You may find the following National Instruments documents helpful for
programming interrupts and DMA:
•Programming Interrupts for Data Acquisition on 80x86-Based
Computers, Application Note 010
•Programming DMA on PC/XT/AT Computers, Application Note 029
The following National Instruments manuals contain general information
and operating instructions for the AT E Series boards:
•AT E Series User Manual
•DAQ-STC Technical Reference Manual
Customer Communication
National Instruments wants to receive your comments on our products
and manuals. We are interested in the applications you develop with our
products, and we want to help if you have problems with them. To make it
easy for you to contact us, this manual contains comment and configuration
forms for you to complete. These forms are in Appendix B, Customer
Communication, at the end of this manual.

© National Instruments Corporation 1-1 AT-MIO E Series RLPM
1
General Description
This chapter describes the general characteristics of the AT E Series
boards.
General Characteristics
The AT E Series boards are completely Plug and Play-compatible
multifunction analog, digital, and timing I/O boards for the PC AT and
compatible computers. This family of boards features 12-bit and
16-bit ADCs with 16 and 64 analog inputs, 12-bit and 16-bit DACs with
voltage outputs, eight and 32 lines of TTL-compatible digital I/O, and two
24-bit counter/timers for timing I/O. Because the AT E Series boards have
no DIP switches, jumpers, or potentiometers, they are easily configured
and calibrated using software.
The AT E Series boards are the first completely switchless and jumperless
DAQ boards. This feature is made possible by the National Instruments
DAQ-PnP bus interface chip to connect the board to the AT I/O bus.
The DAQ-PnP implements the Plug and Play ISA Specification so that
the DMA, interrupts, and base I/O addresses are all software configurable.
This allows you to easily change the AT E Series board configuration
without having to remove the board from your computer.
The AT E Series boards use the National Instruments DAQ-STC system
timing controller for time-related functions. The DAQ-STC consists
of three timing groups that control analog input, analog output, and
general-purpose counter/timer functions. These groups include a total of
seven 24-bit and three 16-bit counters and a maximum timing resolution
of 50 ns.
Acommon problem withDAQboards is that youcannot easily synchronize
several measurement functions to a common trigger or timing event. The
AT E Series boards have the Real-Time System Integration (RTSI) bus to
solve this problem. The RTSI bus consists of our RTSI bus interface and a
ribbon cable to route timing and trigger signals between several functions
on up to five DAQ boards in your PC.

Chapter 1 General Description
AT-MIO E Series RLPM 1-2
© National Instruments Corporation
The AT E Series boards can interface to an SCXI system so that you can
acquire over 3,000 analog signals from thermocouples, RTDs, strain
gauges, voltage sources, and current sources. You can also acquire or
generate digital signals for communication and control. SCXI is the
instrumentation front end for plug-in DAQ boards.
Refer to Table 1-1 for a listing of the various boards in the AT E Series and
their distinguishing features.
Your AT E Series board is completely software configurable. Refer to your
AT E Series User Manual if you have not already installed and configured
your board.
Table 1-1. Features of the AT E Series Boards
Board Features
AT-MIO-16E-1 16 single-ended or eight differential 12-bit analog
inputs, 1,250 kS/s, two 12-bit analog outputs,
eight digital I/O, analog and digital triggering
AT-MIO-16E-2 16 single-ended or eight differential 12-bit analog
inputs, 500 kS/s, two 12-bit analog outputs, eight
digital I/O, analog and digital triggering
AT-MIO-64E-3 64 single-ended or 32 differential 12-bit analog
inputs, 500 kS/s, two 12-bit analog outputs, eight
digital I/O, analog and digital triggering
AT-MIO-16E-10 16 single-ended or eight differential 12-bit analog
inputs, 100 kS/s, two 12-bit analog outputs, eight
digital I/O, digital triggering
AT-MIO-16DE-10 16 single-ended or eight differential 12-bit analog
inputs, 100 kS/s, two 12-bit analog outputs, 32
digital I/O, digital triggering
AT-MIO-16XE-10 16 single-ended or eight differential 16-bit analog
inputs, 100 kS/s, two 16-bit analog outputs, eight
digital I/O, analog and digitial triggering
AT-MIO-16XE-50 16 single-ended or eight differential 16-bit analog
inputs, 20 kS/s, two 12-bit analog outputs, eight
digital I/O, digital triggering
AT-AI-16XE-10 16 single-ended or eight differential 16-bit analog
inputs, 100 kS/s, eight digital I/O, analog and
digital triggering

© National Instruments Corporation 2-1 AT-MIO E Series RLPM
2
Theory of Operation
This chapter contains a functional overview of the AT E Series boards and
explains the operation of each functional unit making up the AT E Series
boards.
Functional Overview
The block diagram in Figures 2-1 through 2-5 give a functional overview
of each AT E Series board.
Figure 2-1. AT-MIO-16E-1, AT-MIO-16E-2, and AT-MIO-64E-3 Block Diagram
Timing
PFI / Trigger
I/O Connector
3
RTSI Bus
AT – I/O Channel
Digital I/O (8)
12-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
+
NI-PGIA
Gain
Amplifier
–
Calibration
Mux
Mux Mode
Selection
Switches
Analog
Muxes
Voltage
REF Calibration
DACs
Dither
Circuitry
Trigger
Analog
Trigger
Circuitry
2
Trigger Level
DACs
6Calibration
DACs
DAC0
DAC1
3
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Bus
Interface
(8)*
(8)*
DAC
FIFO
8
Data (16)
AI Control
Data (16)
Analog
Input
Control EEPROM
Control DMA Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
8255
DIO
Control Bus
Interface
IRQ
DMA
Data
Transceivers
AO Control
ADC
FIFO
*32 on the AT-MIO-64E-3

Chapter 2 Theory of Operation
AT-MIO E Series RLPM 2-2
© National Instruments Corporation
Figure 2-2. AT-MIO-16E-10 and AT-MIO-16DE-10 Block Diagram
Timing
PFI / Trigger
I/O Connector
4
RTSI Bus
AT – I/O Channel
Digital I/O (8)
12-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
+
NI-PGIA
Gain
Amplifier
–
Calibration
Mux
Mux Mode
Selection
Switches
Analog
Muxes
Voltage
REF Calibration
DACs
Dither
Circuitry
6Calibration
DACs
DAC0
DAC1
3
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Bus
Interface
(8)
(8)
8255
DIO
Port
8
Data (16)
AI Control
Data (16)
Analog
Input
Control EEPROM
Control DMA Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
8255
DIO
Control Bus
Interface
IRQ
DMA
Data
Transceivers
AO Control
Data (8)
PC (8)
PB (8)
PA (8) AT-MIO-16DE-10 ONLY
ADC
FIFO

Chapter 2 Theory of Operation
© National Instruments Corporation 2-3 AT-MIO E Series RLPM
Figure 2-3. AT-MIO-16XE-10 Block Diagram
Timing
PFI / Trigger
I/O Connector
3
2
2
RTSI Bus
AT – I/O Channel
Digital I/O (8)
16-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
REF
Buffer
+
Programmable
Gain
Amplifier
–
Calibration
Mux
Mux Mode
Selection
Switches
Analog
Muxes
Voltage
REF Calibration
DACs
4Calibration
DACs
DAC0
DAC1
7
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Bus
Interface
(8)
(8)
8
AI Control
Analog
Input
Control EEPROM
Control DMA Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
8255
DIO
Control Bus
Interface
IRQ
DMA
AO Control
DAC
FIFO
Data (16)
Trigger Level
DACs Analog
Trigger
Circuitry
Data (16)
Data
Transceivers
ADC
FIFO
Trigger

Chapter 2 Theory of Operation
AT-MIO E Series RLPM 2-4
© National Instruments Corporation
Figure 2-4. AT-AI-16XE-10 Block Diagram
Timing
PFI / Trigger
I/O Connector
3
2
2
RTSI Bus
AT – I/O Channel
Digital I/O (8)
16-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
REF
Buffer
+
Programmable
Gain
Amplifier
–
Calibration
Mux
Mux Mode
Selection
Switches
Analog
Muxes
Voltage
REF Calibration
DACs
7
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Bus
Interface
(8)
(8)
8
AI Control
Analog
Input
Control EEPROM
Control DMA Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
8255
DIO
Control Bus
Interface
IRQ
DMA
Data (16)
Trigger Level
DACs Analog
Trigger
Circuitry
Data
Transceivers
ADC
FIFO
Trigger
Data (16)

Chapter 2 Theory of Operation
© National Instruments Corporation 2-5 AT-MIO E Series RLPM
Figure 2-5. AT-MIO-16XE-50 Block Diagram
The following major components make up the AT E Series boards:
• ISA bus interface circuitry with Plug and Play capability (DAQ-PnP)
• Analog input circuitry
• Analog trigger circuitry
• Analog output circuitry
• Digital I/O circuitry
• Timing I/O circuitry (DAQ-STC)
• RTSI bus interface circuitry
The internal data and control buses interconnect the components. Notice
that the DAQ-STC is the timing engine that provides precise timing signals
for the analog input and output operations. The timing I/O circuitry
information in this manual is skeletal in nature and is sufficient in most
Timing
PFI / Trigger
I/O Connector
3
2
RTSI Bus
AT – I/O Channel
Digital I/O (8)
16-Bit
Sampling
A/D
Converter
EEPROM
Configuration
Memory
+
Programmable
Gain
Amplifier
–
Calibration
Mux
Mux Mode
Selection
Switches
Analog
Muxes
Voltage
REF Calibration
DACs
4Calibration
DACs
DAC0
DAC1
3
DAQ - STC
Analog Input
Timing/Control
Analog Output
Timing/Control
Digital I/O
Trigger
Counter/
Timing I/O
RTSI Bus
Interface
DMA/
Interrupt
Request
Bus
Interface
(8)
(8)
8
Data (16)
AI Control
Data (16)
Analog
Input
Control EEPROM
Control DMA Interface
DAQ-PnP
DAQ-STC
Bus
Interface
Plug
and
Play
Analog
Output
Control
8255
DIO
Control Bus
Interface
IRQ
DMA
Data
Transceivers
AO Control
ADC
FIFO

Chapter 2 Theory of Operation
AT-MIO E Series RLPM 2-6
© National Instruments Corporation
cases. For register-level programming information, refer to the DAQ-STC
Technical Reference Manual.
ISA Bus Interface Circuitry
The AT E Series boards are all full-size, 16-bit ISA I/O interface cards. The
ISA bus features a 16-bit address bus, a 16-bit data bus, a DMA arbitration
bus, interrupt lines, and several control and support signals. Figure 2-6
shows the functional blocks making up the AT E Series ISA bus interface
circuitry.
Figure 2-6. ISA Bus Interface Circuitry Block Diagram
IRQ 8
Data Bus16 Internal Data Bus
Request
Sources
16
DMA Request 7
DMA Acknowledge 7
DMA TC
Address16
ISA Control
Data
Buffers
Plug and Play
Interface
IRQ Board
Select
DMA
Access
DMA
DAQ-PnP
Analog Input FIFO Flags
Register SelectsRegister
Interface
DMA
Interface
Analog Output FIFO Flags
DAQ-STC
Base Address

Chapter 2 Theory of Operation
© National Instruments Corporation 2-7 AT-MIO E Series RLPM
The DAQ-PnP provides the main interface to the ISA bus, including
support for the Plug and Play ISA Specification. Plug and Play provides a
mechanism for assigning bus resources to the card using software only.
This eliminates the need for setting jumpers or DIP switches on the board
to select the base I/O address, interrupt lines, and DMA channels. In a
Plug and Play aware system, the Plug and Play circuitry in the DAQ-PnP
can request a base I/O address, up to three DMA channels, and up to
two interrupt lines from the configuration manager. In other systems,
application software can simply assign particular resources to the card.
The DAQ-PnP stores the resource assignments in the Plug and Play
configuration registers. It also performs the base I/O address decoding
after the board is activated through software. The DAQ-PnP performs full
16-bit address decoding, where address lines SA<15..5> are used for the
comparison. This decoding allows the board to be located on any 32-byte
boundary within the 16-bit address space. The remaining address lines
SA<4..0> are used to select the onboard registers.
The register interfaceblock within the DAQ-PnP is used to select the target
register of a particular read or write cycle. These accesses are controlled by
the base address decoding, SA<4..0> and the ISA control lines when the
CPU is trying to access the board. In the case of DMA transfers, the access
is controlled by the DMA block within the DAQ-PnP and the ISA control
lines. The register interface block provides all access to the registers in the
DAQ-PnP, DAQ-STC, and other onboard resources such as the FIFOs.
The DMA interface block within the DAQ-PnP provides for high-speed
data transfer between the board and the system memory. Up to three DMA
channels can be used simultaneously for data transfers with analog input,
analog output, and the general-purpose counters. The DMA circuitry can
only perform 16-bit transfers—DMA channels 5, 6, and 7 are available in
ISA computers, whereas channels 0, 1, 2, 3, 5, 6, and 7 are available in
EISA computers. The DMA transfers are initiated by theDAQ-STC, which
indicates to the DAQ-PnP when the data transfers should occur. The
DAQ-PnP then asserts the appropriate DMA request line and performs the
transfer when the DMA acknowledge occurs.
The DAQ-STC can generate interrupts from over 20 sources and can route
these interrupts to one or two of eight interrupt lines on the ISA bus
interface. The use of two interrupt lines can improve performance in some
environments but is usually more difficult to program. The AT E Series
boards connect the eight DAQ-STC interrupt lines (0..7) to the IRQ3, 4, 5,
7, 10, 11, 12, and 15 lines, respectively.

Chapter 2 Theory of Operation
AT-MIO E Series RLPM 2-8
© National Instruments Corporation
The data buffers are used to control the direction of the data transfers on the
bi-directional data lines based on whether the transfer is a read or write
operation. The enabling and direction of the buffers is controlled by the
DAQ-PnP.
Analog Input and Timing Circuitry
The AT E Series boards have 16 to 64 analog input channels and a timing
core within the DAQ-STC that is dedicated to analog input operation.
Figure 2-7 shows a general block diagram for the analog input circuitry.
Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram
Analog Input Circuitry
The general model for analog input on the AT E Series boards includes
input multiplexer, multiplexer mode selection switches, a
software-programmable gain instrumentation amplifier, calibration
Calibration
DACs
Mode
Selection
Dither
Convert
ADC FIFO
ACH0
AISense
Input Multiplexer*
Cal Mux
AIGND
Gain
PGIA
Polarity
Channel
Type
Channel
Number
Calibration
Sources
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
ACH8
ACH9
ACH10
ACH11
ACH12
ACH13
ACH14
ACH15
*There are four banks of 16 channels on the AT-MIO-64E-3