National Instruments NI PXIe-1062Q User manual

INSTALLATION GUIDE
8-Slot NI PXIe-1062Q Backplane
This guide describes installation requirements for the 8-slot
NI PXIe-1062Q backplane.
Contents
NI PXIe-1062Q Chassis Backplane Overview ....................................... 2
Interoperability with CompactPCI................................................... 2
System Controller Slot..................................................................... 3
Hybrid Peripheral Slots.................................................................... 3
PXI Peripheral Slots......................................................................... 3
System Timing Slot ......................................................................... 4
PXI Local Bus.................................................................................. 5
PXI Trigger Bus............................................................................... 6
System Reference Clock.................................................................. 6
PXIe_SYNC_CTRL ........................................................................ 9
Mechanical Requirements....................................................................... 9
Mounting.......................................................................................... 9
Cooling............................................................................................. 10
Handling.................................................................................................. 10
Dimensions ...................................................................................... 11
Electrical Requirements .......................................................................... 12
PXI Connectors................................................................................ 12
Power ............................................................................................... 12
Connector J29 ........................................................................... 12
Connector J27 ........................................................................... 15
Connector J26 ........................................................................... 15
Connector W1........................................................................... 16
Backplane Specifications................................................................. 16
10 MHz System Reference Clock (PXI_CLK10) .................... 16
Pinouts..................................................................................................... 17
System Controller Slot Pinouts........................................................ 18
System Timing Slot Pinouts ............................................................ 19
Peripheral Slot Pinouts..................................................................... 21
Hybrid Slot Pinouts.......................................................................... 23

8-Slot NI PXIe-1062Q Backplane Installation Guide 2 ni.com
NI PXIe-1062Q Chassis Backplane Overview
This section provides an overview of the backplane features for the
NI PXIe-1062Q chassis. Figure 1 shows the backplane.
Figure 1. 8-Slot NI PXIe-1062Q Backplane
Interoperability with CompactPCI
With the NI PXIe-1062Q, you can use the following devices in a single PXI
Express chassis:
• PXI Express-compatible products
• CompactPCI Express-compatible 4-Link system controller products
• CompactPCI Express-compatible Type-2 peripheral products
• PXI peripheral products
• Standard CompactPCI peripheral products

©National Instruments Corporation 3 8-Slot NI PXIe-1062Q Backplane Installation Guide
System Controller Slot
The system controller slot is slot 1 of the chassis and is a 4-Link
configuration system slot as defined by the CompactPCI Express and
PXI Express specifications. It has three system controller expansion slots
for system controller modules that are wider than one slot. These slots
allow the system controller to expand to the left to prevent the system
controller from using peripheral slots.
The backplane routes a x4 PCI Express link from the system controller slot
to slots 3, 4, and 5, and a x1 PCI Express link to a PCI Express to PCI
Translation Bridge on the backplane. The PCI Express to PCI Translation
Bridge on the backplane provides a 32-bit/33 MHz PCI bus to slots 2, 3, 5,
6, 7, and 8.
The system controller slot also has connectivity to some PXI features, such
as PXI_CLK10, PXI Star, PXI Trigger Bus, and PXI Local Bus 6.
The system controller can control the power supply with the PS_ON#
signals. A logic low on this line turns on the power supply.
Hybrid Peripheral Slots
The chassis includes two hybrid peripheral slots as defined by the PXI-5
PXI Express Hardware Specification: slot 3 and slot 5. A hybrid peripheral
slot can accept the following peripheral modules:
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot.
• A hybrid-compatible PXI peripheral module modified by replacing the
J2 connector with an XJ4 connector installed in the upper eight rows
of J2. Refer to the PXI Express Specification for details. The PXI
peripheral communicates through the backplane 32-bit PCI bus.
• A CompactPCI 32-bit peripheral on the backplane 32-bit PCI bus.
The hybrid peripheral slots provide full PXI Express functionality and
32-bit PXI functionality except for PXI Local Bus. The hybrid peripheral
slot connects only to PXI Local Bus 6 left and right.
PXI Peripheral Slots
Four PXI peripheral slots accept PXI or CompactPCI peripherals: slot 2,
slot 6, slot 7, and slot 8. These slots are on the backplane 32-bit PCI bus.
These slots offer full PXI functionality, but have no PXI Express features.
The 64-bit PCI signals on the P2 connectors are not connected.

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System Timing Slot
The system timing slot is slot 4. The system timing slot accepts the
following peripheral modules:
• A PXI Express system timing module with a x4 or x1 PCI Express link
to the system slot.
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot.
The system timing slot has three dedicated differential pairs
(PXIe_DSTAR) connected from the TP2 connector to the XP3 connector
for each hybrid peripheral slot, as well as routed back to the XP3 connector
of the system timing slot, as shown in Figure 2. You can use the
PXIe_DSTAR pairs for high-speed triggering, synchronization, and
clocking. Refer to the PXI Express Specification for details.
The system timing slot also has a single-ended (PXI Star) trigger connected
to every slot. Refer to Figure 2 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system
timing module can source a 10 MHz clock to which the backplane
phase-locks. Refer to the System Reference Clock section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a
system timing module can control the PXIe_SYNC100 timing. Refer to the
PXI Express Specification and the PXIe_SYNC_CTRL section for details.

©National Instruments Corporation 5 8-Slot NI PXIe-1062Q Backplane Installation Guide
Figure 2. PXIe_DSTAR and PXI Star Connectivity Diagram
PXI Local Bus
The PXI backplane local bus is a daisy-chained bus that connects each
peripheral slot with adjacent peripheral slots to the left and right, as shown
in Figure 3.
The backplane routes the full 13-line PXI Local Bus between adjacent PXI
slots (slots 6, 7, and 8) and PXI Local Bus 6 between all other slots. Refer
to Figure 3 for details. The left local bus 6 from slot 1 is not routed
anywhere, and the right local bus signals from slot 8 are not routed
anywhere.
Local bus signals may range from high-speed TTL signals to analog signals
as high as 42 V.
Initialization software uses the configuration information specific to each
adjacent peripheral module to evaluate local bus compatibility.
PXI Star 0
PXI Star 2
PXI Star 3
PXI Star 5
PXI Star 6
PXI Star 1
PXI Star 4
P1 P2 P1 P2 P1 P2 P1 XP3 XP4 P1 P2
XP3XP2XP1 XP4
P1 XP3 XP4
XP3TP2 XP4
Slot 1: System Controller Slot
Slot 2: PXI Peripheral Slot
Slot 3: Hybrid Peripheral Slot
Slot 4: System Timing Slot
Slot 5: Hybrid Peripheral Slot
Slot 6: PXI Peripheral Slot Slot 7: PXI Peripheral Slot Slot 8: PXI Peripheral Slot
PXIe_DSTAR0
PXIe_DSTAR9
PXIe_DSTAR8

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Figure 3. PXI Trigger Bus and Local Bus Connectivity Diagram
PXI Trigger Bus
All slots share eight trigger lines.You can use these trigger lines in a variety
of ways. For example, you can use triggers to synchronize the operation of
several different PXI peripheral modules. In other applications, one module
can control carefully timed sequences of operations performed on other
modules in the system. Modules can pass triggers to one another, allowing
precisely timed responses to asynchronous external events the system is
monitoring or controlling.
System Reference Clock
The NI PXIe-1062Q chassis supplies the PXI 10 MHz system clock
signal (PXI_CLK10) independently driven to each peripheral slot, and
PXIe_CLK100 and PXIe_SYNC100 to the hybrid slots and system
timing slot.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 250 ps between slots) drives PXI_CLK10
to each peripheral slot. Refer to Figure 4 for the PXI_CLK10 routing
configuration. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to the hybrid peripheral slots
and system timing slot. Refer to Figure 4 for the routing configuration of
PXIe_CLK100. These clocks are matched in skew to less than 100 ps. The
differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_CLK100, so that when there is no
peripheral or a peripheral that does not connect to PXIe_CLK100, no clock
is driven on the pair to that slot.
P1 P2 P1 P2 P1 P2 P1 XP3 XP4 P1 P2
XP3XP2XP1 XP4
P1 XP3 XP4
XP3TP2 XP4
Trigger
Bus
Trigger
Bus
Trigger
Bus
Trigger
Bus
Trigger
Bus
PXI_LB
(12:0)
PXI_LB
(12:0)
Trigger
Bus
Trigger
Bus
PXI_LB6 PXI_LB6 PXI_LB6 PXI_LB6 PXI_LB6
87654321

©National Instruments Corporation 7 8-Slot NI PXIe-1062Q Backplane Installation Guide
An independent buffer drives PXIe_SYNC100 to the hybrid peripheral slot
and system timing slot. Refer to Figure 4 for the routing configuration of
PXIe_SYNC100. These clocks are matched in skew to less than 100 ps.
The differential pair must be terminated on the peripheral with LVPECL
termination for the buffer to drive PXIe_SYNC100, so that when there is
no peripheral or a peripheral that does not connect to PXIe_SYNC100, no
SYNC100 signal is driven on the pair to that slot.
Figure 4. Distribution of PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100
PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing
relationship described in Figure 5.
Figure 5. System Reference Clock Default Behavior
PXI_CLK10
PXI_CLK10_IN
PXIe_CLK100 PXIe_SYNC100
System Controller Slot (1)
PXI Peripheral Slot (2)
Hybrid Peripheral Slot (3)
System Timing Slot (4)
Hybrid Peripheral Slot (5)
PXI Peripheral Slot (6) PXI Peripheral Slot (7) PXI Peripheral Slot (8)
10 MHz
REF IN
10 MHz
REF OUT
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
012345678901234567890123456789

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To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the system
timing slot. Refer to Table 10, XP4 Connector Pinout for the System Timing
Slot, for the pinout. When a 10 MHz clock is detected on this pin, the
backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100.) Refer to Backplane Specifications
for the specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
You also can drive a 10 MHz clock on the 10 MHz REF IN pin of connector
J27. When a 10 MHz clock is detected on this connector, the backplane
automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100.) Refer to Backplane Specifications
for the specification information for an external clock provided on the
10 MHz REF IN pin of connector J27.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
system timing slot and the 10 MHz REF IN pin of connector J27, the signal
on the system timing slot is selected. Refer to Table 1, which explains how
the backplane selects the 10 MHz clocks.
A copy of the backplane PXI_CLK10 is exported to the 10 MHz REF OUT
pin of connector J27. An independent buffer drives this clock. Refer to
Backplane Specifications for the specification information for the 10 MHz
REF OUT signal on connector J27.
Table 1. Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN
Connector J27
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100
No clock present No clock present Backplane generates its own clocks
No clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
connector J27—10 MHz REF IN
10 MHz clock present No clock present PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
system timing slot—PXI_CLK10_IN
10 MHz clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
system timing slot—PXI_CLK10_IN

©National Instruments Corporation 9 8-Slot NI PXIe-1062Q Backplane Installation Guide
PXIe_SYNC_CTRL
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/nMHz, where nis a positive
integer. The default for nis 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows nto be programmed to other integers. For
example, setting n= 3 creates a PXIe_SYNC100 with a 300 ns period while
still maintaining its phase relationship to PXI_CLK10. The nvalue can be
any positive integer from 1 to 255.
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL, for use when n > 1. Refer to Table 9, XP3 Connector
Pinout for the System Timing Slot, for the system timing slot pinout. Refer
to Backplane Specifications for the PXIe_SYNC_CTRL input
specifications.
By default, a high level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge, the
PXIe_SYNC100 signal restarts. This allows several chassis to have their
PXIe_SYNC100 in phase with each other. Refer to Figure 6 for timing
details with this method.
Figure 6. PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
Mechanical Requirements
Mounting
Figure 7 shows the backplane dimensions. There are 24 holes available for
mounting with M2.5 hardware.
Use all mounting holes for proper backplane support.
Two mounting holes on top of the backplane have plated annular pads on
the front and back of the backplane. Use these mounting holes to connect
the backplane ground to the chassis in which the backplane is mounted. If
you do not want to connect the backplane ground to the chassis, use
insulated washers at these mounting holes. Refer to Figure 9 for the
mounting hole positions.
PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
SYNC100 Divider
Restarted Here

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Cooling
Note National Instruments is not responsible for damage to the backplane if inadequate
cooling is used.
You should mount a fan below the backplane. Airflow should be from the
bottom to the top of the PXI modules. You must determine the airflow
requirements for your system based on the PXI Hardware Specification.
Handling
Cautions Be careful to avoid bending or otherwise damaging the pins on the backplane
connectors. Bent pins may cause functional failures or damage when the backplane is
powered.
To protect both yourself and the backplane from electrical hazards, leave the chassis
powered off until you finish installing the PXI controller and modules.
Caution Electrostatic discharge can damage your equipment. To avoid such damage,
discharge the static built up on your body by touching a grounded metal object before
handling the PXI equipment. Then touch the antistatic plastic package containing the
backplane to a metal part of your PXI chassis before removing the backplane from the
packaging.