National Instruments PXI Express NI PXIe-1065 User manual

INSTALLATION GUIDE
18-Slot NI PXIe-1065 Backplane
This guide describes installation requirements for the 18-slot
NI PXIe-1065 backplane.
Contents
NI PXIe-1065 Backplane Overview ....................................................... 2
Interoperability with CompactPCI................................................... 3
System Controller Slot..................................................................... 3
Hybrid Peripheral Slots.................................................................... 4
PXI Peripheral Slots......................................................................... 4
PXI Express Peripheral Slots........................................................... 4
System Timing Slot ......................................................................... 5
PXI Local Bus.................................................................................. 6
PXI Trigger Bus............................................................................... 7
System Reference Clock.................................................................. 8
PXIe_SYNC_CTRL ........................................................................ 10
Mechanical Requirements....................................................................... 11
Mounting.......................................................................................... 11
Cooling............................................................................................. 11
Handling.................................................................................................. 12
Dimensions ...................................................................................... 12
Electrical Requirements .......................................................................... 13
PXI Connectors................................................................................ 13
Power ............................................................................................... 14
Connector J205 ......................................................................... 14
Connector J206 ......................................................................... 16
Connector J200 ......................................................................... 17
Connectors J213, J214, J215, and J216 .................................... 17
Backplane Specifications................................................................. 17
System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications................................................... 18
10 MHz System Reference Clock: PXI_CLK10...................... 18
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe_SYNC100 .................................................................... 18
External Clock Source .............................................................. 19

18-Slot NI PXIe-1065 Backplane Installation Guide 2 ni.com
PXIe_SYNC_CTRL..................................................................19
PXI Differential Star Triggers (PXIe-DSTARA,
PXIe-DSTARB, PXIe-DSTARC) ..........................................20
Pinouts .....................................................................................................20
System Controller Slot Pinouts ........................................................21
System Timing Slot Pinouts .............................................................22
Peripheral Slot Pinouts .....................................................................24
Hybrid Slot Pinouts ..........................................................................26
NI PXIe-1065 Backplane Overview
This section provides an overview of the backplane features for the
NI PXIe-1065 chassis. Figure 1 shows the backplane.
Figure 1. 18-Slot NI PXIe-1065 Backplane

©National Instruments Corporation 3 18-Slot NI PXIe-1065 Backplane Installation Guide
Interoperability with CompactPCI
With the NI PXIe-1065, you can use the following devices in a single PXI
Express system:
• PXI Express-compatible products
• CompactPCI Express-compatible 4-Link system controller products
• CompactPCI Express-compatible Type-2 peripheral products
• PXI peripheral products
• Standard CompactPCI peripheral products
System Controller Slot
The system controller slot is slot 1 of the backplane and is a 4-Link
configuration system slot as defined by the CompactPCI Express and
PXI Express specifications. It has three system controller expansion slots
for system controller modules that are wider than one slot. These slots
allow the system controller to expand to the left to prevent the system
controller from using peripheral slots.
The backplane routes a x4 PCI Express link from the system controller
slot to slots 7 and 8, and a x1 PCI Express link to a PCI Express to PCI
Translation Bridge on the backplane. The PCI Express to PCI Translation
Bridge on the backplane provides a 32-bit/33 MHz PCI bus to slots 2 to 7.
The second PCI Translation Bridge provides PCI bus to slots 11, 12, 13, 15,
16, 17, and 18 (not to slot 14).
A x4 link goes to the PXI Express switch and the PCI Express connectivity
of slots 9 to 14 is connected through the switch.
The system controller slot also has connectivity to some PXI features, such
as PXI_CLK10, PXI Star, PXI Trigger Bus, and PXI Local Bus 6.
The system controller can control the power supply with the PS_ON#
signals. A logic low on this line turns on the power supply.
Note The Inhibit Mode switch on the chassis rear panel must be in the Default position
for the system controller to control the power supply. Refer to the Inhibit Mode Switch
section of Chapter 2, Installation and Configuration, in the NI PXIe-1065 User Manual for
details about the Inhibit Mode switch.

18-Slot NI PXIe-1065 Backplane Installation Guide 4 ni.com
Hybrid Peripheral Slots
The backplane includes four hybrid peripheral slots as defined by the PXI-5
PXI Express Hardware Specification: slot 7 and slots 11–13. A hybrid
peripheral slot can accept the following peripheral modules:
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot or through a switch to the system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot or through a switch to the system slot.
• A hybrid-compatible PXI peripheral module modified by replacing the
J2 connector with an XJ4 connector installed in the upper eight rows
of J2. Refer to the PXI Express Specification for details. The PXI
peripheral communicates through the backplane 32-bit PCI bus.
• A CompactPCI 32-bit peripheral on the backplane 32-bit PCI bus.
The hybrid peripheral slots provide full PXI Express functionality and
32-bit PXI functionality except for PXI Local Bus. The hybrid peripheral
slot connects only to PXI Local Bus 6 left and right.
PXI Peripheral Slots
Nine PXI peripheral slots accept PXI or CompactPCI peripherals: slots 2–6
and slots 15–18. These slots are on the backplane 32-bit PCI buses. These
slots offer full PXI functionality, but have no PXI Express features. The
64-bit PCI signals on the P2 connectors are not connected.
PXI Express Peripheral Slots
There are three PXI Express peripheral slots: slots 8–10. Slot 8 is directly
connected to the system slot with a x4 PCI Express link. Slots 9 and 10 are
connected to the system slot through a PCI Express switch. PXI Express
peripheral slots can accept the following modules:
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot or through a switch to the system slot.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot or through a switch to the system slot.

©National Instruments Corporation 5 18-Slot NI PXIe-1065 Backplane Installation Guide
System Timing Slot
The system timing slot is slot 14. The system timing slot accepts the
following peripheral modules:
• A PXI Express system timing module with a x4 or x1 PCI Express link
to the system slot through a PCIe switch.
• A PXI Express peripheral with a x4 or x1 PCI Express link to the
system slot through a PCIe switch.
• A CompactPCI Express Type-2 peripheral with a x4 or x1 PCI Express
link to the system slot through a PCIe switch.
The system timing slot has three dedicated differential pairs
(PXIe_DSTAR) connected from the TP1 and TP2 connectors to the XP3
connector for each PXI Express peripheral or hybrid peripheral slot, as well
as routed back to the XP3 connector of the system timing slot, as shown in
Figure 2. You can use the PXIe_DSTAR pairs for high-speed triggering,
synchronization, and clocking. Refer to the PXI Express Specification for
details.
The system timing slot also has a single-ended (PXI Star) trigger connected
to every slot. Refer to Figure 2 for details.
The system timing slot has a pin (PXI_CLK10_IN) through which a system
timing module can source a 10 MHz clock to which the backplane
phase-locks. Refer to the System Reference Clock section for details.
The system timing slot has a pin (PXIe_SYNC_CTRL) through which a
system timing module can control the PXIe_SYNC100 timing. Refer to the
PXI Express Specification and the PXIe_SYNC_CTRL section for details.

18-Slot NI PXIe-1065 Backplane Installation Guide 6 ni.com
Figure 2. PXIe_DSTAR and PXI Star Connectivity Diagram
PXI Local Bus
The PXI backplane local bus is a daisy-chained bus that connects each
peripheral slot with adjacent peripheral slots to the left and right, as shown
in Figure 3.
The backplane routes the full 13-line PXI Local Bus between adjacent PXI
slots (slots 2–6 and 15–18) and PXI Local Bus 6 between all other slots.
Refer to Figure 3 for details. The left local bus 6 from slot 1 is not routed
anywhere, and the right local bus signals from slot 18 are not routed
anywhere.
Local bus signals may range from high-speed TTL signals to analog signals
as high as 42 V.
P2
P1
XP4
XP3
TP2
TP1
P2
P1
P2
P1
P2
P1
P1
P1
P1
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P1
XP4
XP3
XP2
XP1
PXIe_DSTAR 11
PXIe_DSTAR 8
PXIe_DSTAR 6
PXIe_DSTAR 5
PXIe_DSTAR 3
PXIe_DSTAR 2
PXIe_DSTAR 1
PXIe_DSTAR 1
PXIe_DSTAR 4
PXI STAR 3
PXI STAR 1
PXI STAR 2 PXI STAR 9
PXI STAR 7
PXI STAR 6
PXI STAR 5
PXI STAR 4
PXI STAR 8
PX STAR 11
PX DSTAR 10
PXI STAR 13
PXI STAR 12
PXI STAR 15
PXI STAR 14
PXI STAR 16
PXI STAR 0
1
8
9
10
7H11 HH
12 H
13 14 15
65
4
3
216 17 18

©National Instruments Corporation 7 18-Slot NI PXIe-1065 Backplane Installation Guide
Initialization software uses the configuration information specific to each
adjacent peripheral module to evaluate local bus compatibility.
Figure 3. PXI Trigger Bus and Local Bus Connectivity Diagram
PXI Trigger Bus
All slots on the same PXI bus segment share eight PXI trigger lines. You
can use these trigger lines in a variety of ways. For example, you can use
triggers to synchronize the operation of several different PXI peripheral
modules. In other applications, one module in the system timing slot can
control carefully timed sequences of operations performed on other
modules in the system. Modules can pass triggers to one another, allowing
precisely timed responses to asynchronous external events the system is
monitoring or controlling.
The PXI trigger lines from adjacent PXI trigger bus segments can be routed
in either direction across the PXI trigger bridges through buffers. This
allows you to send trigger signals to, and receive trigger signals from, every
slot in the chassis. You can configure static trigger routing (user-specified
line and directional assignments) through Measurement & Automation
Explorer (MAX). Dynamic routing of triggers (automatic line assignments)
is supported through certain National Instruments drivers such as
NI-DAQmx.
P2
P1
XP4
XP3
TP2
TP1
P2
P1
P2
P1
P2
P1
P1
P1
P1
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P1
XP4
XP3
XP2
XP1
PXI_LB6
PXI_LB6
PXI_LB6
PXI_LB6 PXI_LB6 PXI_LB6 PXI_LB6 PXI_LB6 PXI_LB6 PXI_LB6
PXI_LB (12:0) PXI_LB (12:0) PXI_LB (12:0) PXI_LB (12:0)
PXI_LB (12:0) PXI_LB (12:0) PXI_LB (12:0)
PXI
Trigger Bus
Buffer Bridge
PXI
Trigger Bus
Buffer Bridge
PXI Trigger Bus Segment 1 PXI Trigger Bus Segment 2 PXI Trigger Bus Segment 3
1
8
9
10
7H11 HH
12 H
13 14 15
65
4
3
216 17 18

18-Slot NI PXIe-1065 Backplane Installation Guide 8 ni.com
Note Although you can route any trigger line in either direction, you cannot route it in
more than one direction at a time.
System Reference Clock
The NI PXIe-1065 backplane supplies the PXI 10 MHz system clock signal
(PXI_CLK10) independently driven to each peripheral slot, and
PXIe_CLK100 and PXIe_SYNC100 to the PXI Express slots, hybrid slots,
and system timing slot.
An independent buffer (having a source impedance matched to the
backplane and a skew of less than 1 ns between slots) drives PXI_CLK10
to each peripheral slot. Refer to Figure 4 for the PXI_CLK10 routing
configuration. You can use this common reference clock signal to
synchronize multiple modules in a measurement or control system.
An independent buffer drives PXIe_CLK100 to the PXI Express peripheral
slots, hybrid peripheral slots, and system timing slot. Refer to Figure 4 for
the routing configuration of PXIe_CLK100. These clocks are matched in
skew to less than 100 ps. The differential pair must be terminated on the
peripheral with LVPECL termination for the buffer to drive PXIe_CLK100,
so that when there is no peripheral or a peripheral that does not connect to
PXIe_CLK100, no clock is driven on the pair to that slot.
An independent buffer drives PXIe_SYNC100 to the PXI Express
peripheral slots, hybrid peripheral slots, and system timing slot. Refer to
Figure 4 for the routing configuration of PXIe_SYNC100. The differential
pair must be terminated on the peripheral with LVPECL termination for the
buffer to drive PXIe_SYNC100, so that when there is no peripheral or a
peripheral that does not connect to PXIe_SYNC100, no SYNC100 signal
is driven on the pair to that slot.

©National Instruments Corporation 9 18-Slot NI PXIe-1065 Backplane Installation Guide
Figure 4. Distribution of PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100
PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 have the default timing
relationship described in Figure 5.
Figure 5. System Reference Clock Default Behavior
To synchronize the system to an external clock, you can drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the system
timing slot. Refer to Table 11, XP4 Connector Pinout for the System Timing
Slot, for the pinout. When a 10 MHz clock is detected on this pin, the
backplane automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100.) Refer to Backplane Specifications
for the specification information for an external clock provided on the
PXI_CLK10_IN pin of the system timing slot.
P2
P1
XP4
XP3
TP2
TP1
P2
P1
P2
P1
P2
P1
P1
P1
P1
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
XP4
XP3
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
XP4
XP3
XP2
XP1
P1
10 MHz
REF IN
10 MHz
REF OUT
PXI_CLK10_IN
1
8
9
10
PXIe_CLK100
PXIe_SYNC100
PXI_CLK10
7H11 HH
12 H
13 14 15
65
4
3
216 17 18
PXIe_CLK100
PXI_CLK10
PXIe_SYNC100
012345678901234567890123456789

18-Slot NI PXIe-1065 Backplane Installation Guide 10 ni.com
You also can drive a 10 MHz clock on the 10 MHz REF IN pin of connector
J206. When a 10 MHz clock is detected on this connector, the backplane
automatically phase-locks the PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 signals to this external clock and distributes these signals
to the slots. (Refer to Figure 4 for the distribution of PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100.) Refer to Backplane Specifications
for the specification information for an external clock provided on the
10 MHz REF IN pin of connector J206.
If the 10 MHz clock is present on both the PXI_CLK10_IN pin of the
system timing slot and the 10 MHz REF IN pin of connector J206, the
signal on the system timing slot is selected. Refer to Table 1, which
explains how the backplane selects the 10 MHz clocks.
A copy of the backplane PXI_CLK10 is exported to the 10 MHz REF OUT
pin of connector J206. An independent buffer drives this clock. Refer to
Backplane Specifications for the specification information for the 10 MHz
REF OUT signal on connector J206.
PXIe_SYNC_CTRL
PXIe_SYNC100 is by default a 10 ns pulse synchronous to PXI_CLK10.
The frequency of PXIe_SYNC100 is 10/nMHz, where nis a positive
integer. The default for nis 1, giving PXIe_SYNC100 a 100 ns period.
However, the backplane allows nto be programmed to other integers. For
example, setting n= 3 creates a PXIe_SYNC100 with a 300 ns period while
still maintaining its phase relationship to PXI_CLK10. The nvalue can be
any positive integer from 1 to 255.
Table 1. Backplane External Clock Input Truth Table
System Timing Slot
PXI_CLK10_IN
Connector J206
10 MHz REF IN
Backplane PXI_CLK10,
PXIe_CLK100, and PXIe_SYNC100
No clock present No clock present Backplane generates its own clocks
No clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
connector J206—10 MHz REF IN
10 MHz clock present No clock present PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
system timing slot—PXI_CLK10_IN
10 MHz clock present 10 MHz clock present PXI_CLK10, PXIe_CLK100, and
PXIe_SYNC100 all phase-locked to
system timing slot—PXI_CLK10_IN

©National Instruments Corporation 11 18-Slot NI PXIe-1065 Backplane Installation Guide
The system timing slot has a control pin for PXIe_SYNC100 called
PXIe_SYNC_CTRL, for use when n > 1. Refer to Table 10, XP3 Connector
Pinout for the System Timing Slot, for the system timing slot pinout. Refer
to Backplane Specifications for the PXIe_SYNC_CTRL input
specifications.
By default, a high level detected by the backplane on the
PXIe_SYNC_CTRL pin causes a synchronous restart for the
PXIe_SYNC100 signal. On the next PXI_CLK10 edge, the
PXIe_SYNC100 signal restarts. This allows several chassis to have their
PXIe_SYNC100 in phase with each other. Refer to Figure 6 for timing
details with this method.
Figure 6. PXIe_SYNC100 at 3.33 MHz Using PXIe_SYNC_CTRL as Restart
Mechanical Requirements
Mounting
Figure 7 shows the backplane dimensions. There are 42 holes available for
mounting with M2.5 hardware.
Use all mounting holes for proper backplane support.
Five mounting holes on top of the backplane have plated annular pads on
the front and back of the backplane. Use these mounting holes to connect
the backplane ground to the chassis in which the backplane is mounted. If
you do not want to connect the backplane ground to the chassis, use
insulated washers at these mounting holes. Refer to Figure 9 for the
mounting hole positions.
Cooling
Note National Instruments is not responsible for damage to the backplane if inadequate
cooling is used.
You should mount a fan below the backplane. Airflow should be from the
bottom to the top of the PXI modules. You must determine the airflow
requirements for your system based on the PXI Hardware Specification.
PXI_CLK10
PXIe_SYNC_CTRL
PXIe_SYNC100
SYNC100 Divider
Restarted Here

18-Slot NI PXIe-1065 Backplane Installation Guide 12 ni.com
Handling
Cautions Be careful to avoid bending or otherwise damaging the pins on the backplane
connectors. Bent pins may cause functional failures or damage when the backplane is
powered.
To protect both yourself and the backplane from electrical hazards, leave the chassis
powered off until you finish installing the PXI controller and modules.
Caution Electrostatic discharge can damage your equipment. To avoid such damage,
discharge the static built up on your body by touching a grounded metal object before
handling the PXI equipment. Then touch the antistatic plastic package containing the
backplane to a metal part of your PXI chassis before removing the backplane from the
packaging.
Dimensions
Figure 7. Dimensions
1.110 in.
(28.19 mm)
0.110 in.
(2.79 mm)
5.916 in.
(150.27 mm)
0.122 in.
(3.09 mm)
0.972 in.
(24.68 mm)
0.162 in.
(4.11 mm)
0.800 in.
(20.32 mm)
16.56 in.
(420.65 mm)

©National Instruments Corporation 13 18-Slot NI PXIe-1065 Backplane Installation Guide
Electrical Requirements
PXI Connectors
The PXI and PXI Express connectors have pin descriptions defined in the
PXI Hardware Specification and PXI Express Hardware Specification.
Figure 8 shows the connectors.
Figure 8. PXI Connectors
Figure 9. Backplane Power, J200, and CLK10 Connectors
1Card-Cage Thermistor
Connectors(x4)
2Slot 1 (Controller Slot)
3PXI Peripheral Slots(2–6, 15–18)
4 Hybrid Peripheral Slots(7, 11–13)
5 PXI Express Peripheral Slots(8–10)
6System Timing Slot (14)
1Plated Mounting Holes(5x)
2 Connector J200
3Connector J205
4 Connector J206
233
44
56
1111
1
4
3
2

18-Slot NI PXIe-1065 Backplane Installation Guide 14 ni.com
Power
Refer to the PXI Express Hardware Specification for power requirements
and to the specifications of the chosen power supply to determine the
minimum load required.
Connector J205
Connector J205 is the NI PXIe-1065 backplane power supply connector.
Figure 9 shows the J205 location. Refer to Table 2 for the pin descriptions.
Connector J205 consists of four large #8 pins (34–37) and nine #12 pins
(1–9) for power. There are also 24 #20 pins (10–33) for mixed power and
signaling. Table 2 also indicates which pins must be connected for basic
backplane operation.
Refer to the CompactPCI Express specification for details regarding
PS_ON# and PS_OK.
Caution Do not use the voltage sense pins (10, 18, and 25) to power the board. These pins
are connected by thin trace to the backplane center and are for voltage sensing only.
Providing current through these pins may damage the backplane. If your power supply has
voltage sensing, use these pins; otherwise, leave them unconnected. Pins with “power
plane” in the description are connected to the backplane’s internal power planes and are
suitable for carrying current.
Note Tyco Electronics manufactures the J205 mating connector, which you can order with
part number 6648167–1.
Note The connector SMBus pins are connected to the backplane SMBus, which the
CompactPCI Express specification defines. (The specification also defines uses and
addressing.) Improper use of the SMBus could result in system controller malfunctions.
There are three SMBus slave devices on the NI PXIe-1065 backplane. The
Backplane Descriptor EEPROM is at slave address A4Has defined by the
CompactPCI Express specification, and the backplane clocking CPLD is at
slave address 5AH. There is a temperature monitoring device at slave
address 5CH. If you must connect an SMBus slave device to the J205
SMBus pins, use slave address 58H.

©National Instruments Corporation 15 18-Slot NI PXIe-1065 Backplane Installation Guide
Table 2. Connector J205 Pin Descriptions
Connector Pin Signal Description
Required
for Basic
Power Up
1+5V +5 V power plane Yes
2GND Ground plane Yes
3GND Ground plane Yes
4+3.3V +3.3 V power plane Yes
5+12V +12 V power plane Yes
6GND Ground plane Yes
7GND Ground plane Yes
8+12V +12 V power plane Yes
9GND Ground plane Yes
10 +12V_SENSE +12 V sense only, no power No
11 GND Ground plane Yes
12 –12V –12 V power plane Yes
13 GND Ground plane No
14 OVERTEMP# Alert of over-temperature
condition in card cage
No
15 GND Ground plane No
16 LED1 J200—pin 3 No
17 LED2 J200—pin 4 No
18 +5V_SENSE +5 V sense only, no power No
19 GND Ground plane No
20 GND Ground plane No
21 GND Ground plane No
22 SMBCLK Backplane SMBus clock No
23 SMBDAT Backplane SMBus data No
24 SMBALERT# Backplane SMBus alert# No
25 +3.3V_SENSE +3.3 V sense cnly,
no power
No
26 GND Ground plane Yes
27 –12V –12 V power plane Yes
28 5VAUX 5VAUX power plane Yes
123
456
789
10 15
16 21
22 27
28 33
34 35
36 37

18-Slot NI PXIe-1065 Backplane Installation Guide 16 ni.com
Connector J206
Connector J206 is for interfacing with the backplane PXI_CLK10 circuitry.
Figure 10 shows the J206 connector location. Positronic manufactures the
J206 mating connector, which you can order with part number
CBD7W2M2000Z-759.1.
Figure 10. J206 Connector
29 GND Ground plane Yes
30 PS_ON# From system
slot J20—pin D2
No
31 12V_FAN To test point E8 No
32 GND Ground plane Yes
33 PS_OK To system slot from
power supply
Yes
34 GND Ground plane Yes
35 GND Ground plane Yes
36 +3.3V +3.3 V power plane Yes
37 +5V +5 V power plane Yes
Table 2. Connector J205 Pin Descriptions (Continued)
Connector Pin Signal Description
Required
for Basic
Power Up
Ground
10 MHz
OUT
10 MHz
IN

©National Instruments Corporation 17 18-Slot NI PXIe-1065 Backplane Installation Guide
Connector J200
Use connector J200 in conjunction with J205 for interfacing with an inhibit
switch and LED. You do not need to connect anything to J200 for basic
backplane power up. Refer to Table 3 for the pin descriptions. The power
button (PWRBTN#) signal is a momentary pushbutton signal that tells the
system controller to enable or inhibit the power supply. You can use signals
LED1 and LED2 to drive a bicolor LED in the power switch, but you also
can use these signals to carry another digital signal.
Connectors J213, J214, J215, and J216
Use these connectors for four thermistors to monitor the card-cage
temperature. You can use signal OVERTEMP# on J205 as an alarm
indicating when the card-cage temperature exceeds 90 °C when used in
conjunction with the four thermistors.
Note Use a Sensor Scientific KWM502C-6 or similar thermistor with these connectors.
Note The mating connector for J213, J214, J215, and J216 is Molex part number
50-57-9402.
Backplane Specifications
Size......................................................... 3U-sized; one system slot
(with three system expansion
slots) and 17 peripheral slots.
Compliant with IEEE 1101.10
mechanical packaging.
PXI Express specification
compliant.
Accepts both PXI Express and
CompactPCI (PICMG 2.0 R 3.0)
3U modules.
Table 3. Connector J200 Pin Descriptions
Connector Pin Signal Description
1PWRBTN# Input to system
slot J20—pin F2
2GND Ground plane
3LED1 J205—pin 16
4LED2 J205—pin 17
1
2
3
4
J200

18-Slot NI PXIe-1065 Backplane Installation Guide 18 ni.com
Backplane bare-board material ...............UL 94 V-0 Recognized
Backplane connectors .............................Conforms to IEC 917 and
IEC 1076-4-101, and are
UL 94 V-0 rated
System Synchronization Clock (PXI_CLK10, PXIe_CLK100,
PXIe_SYNC100) Specifications
10 MHz System Reference Clock: PXI_CLK10
Maximum slot-to-slot skew ....................1 ns
Accuracy.................................................±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter .......................................5 ps RMS phase-jitter
(10Hz–1MHzrange)
Duty-factor..............................................45%–55%
Unloaded signal swing............................3.3 V ±0.3 V
Note For other specifications, refer to the PXI-1 Hardware Specification.
100 MHz System Reference Clock: PXIe_CLK100 and
PXIe_SYNC100
Maximum slot-to-slot skew ....................100 ps
Accuracy.................................................±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter .......................................3 ps RMS phase-jitter
(10 Hz–12 kHz range)
2 ps RMS phase-jitter
(12kHz–20MHzrange)
Duty-factor for PXIe_CLK100...............45%–55%
Absolute single-ended voltage swing
(When each line in the differential pair
has 50 Ωtermination to 1.30 V
or Thévenin equivalent)..........................400–1000 mV
Note For other specifications, refer to the PXI-5 PXI Express Hardware Specification.

©National Instruments Corporation 19 18-Slot NI PXIe-1065 Backplane Installation Guide
External 10 MHz Reference Out (on J206)
Accuracy ................................................ ±25 ppm max. (guaranteed over
the operating temperature range)
Maximum jitter ...................................... 5 ps RMS phase-jitter
(10Hz–1MHzrange)
Output amplitude.................................... 1 VPP ±20% square-wave
into 50 Ω
2 VPP unloaded
Output impedance .................................. 50 Ω±5 Ω
External Clock Source
Frequency............................................... 10 MHz ±100 PPM
Input amplitude
J206................................................. 200 mVPP to 5 VPP square-wave
or sine-wave
System timing slot
PXI_CLK10_IN.............................. 5 V or 3.3 V TTL signal
J206 input impedance............................. 50 Ω±5 Ω
Maximum jitter introduced
by backplane .......................................... 1 ps RMS phase-jitter
(10Hz–1MHzrange)
PXIe_SYNC_CTRL
VIH .......................................................... 2.0–5.5 V
VIL .......................................................... 0–0.8 V
PXI Star Trigger
Maximum slot-to-slot skew ................... 250 ps
Backplane characteristic impedance ...... 65 Ω±10%
Notes For PXI slot to PXI Star mapping, refer to the System Timing Slot section of
Chapter 1, Getting Started, in the NI PXIe-1065 User Manual.
For other specifications, refer to the PXI-1 Hardware Specification.

18-Slot NI PXIe-1065 Backplane Installation Guide 20 ni.com
PXI Differential Star Triggers (PXIe-DSTARA,
PXIe-DSTARB, PXIe-DSTARC)
Maximum slot-to-slot skew ....................150 ps
Maximum differential skew....................25 ps
Backplane differential impedance ..........100 Ω±10%
Notes For PXIe slot to PXI_DSTAR mapping, refer to the System Timing Slot section of
Chapter 1, Getting Started, in the NI PXIe-1065 User Manual.
For other specifications, the NI PXIe-1065 complies with the PXI-5 PXI Express
Hardware Specification.
Pinouts
This section describes the connector pinouts for the NI PXIe-1065 chassis
backplane.
Table 4 shows the XP1 connector pinout for the System Controller slot.
Table 5 shows the XP2 Connector Pinout for the System Controller slot.
Table 6 shows the XP3 Connector Pinout for the System Controller slot.
Table 7 shows the XP4 Connector Pinout for the System Controller slot.
Table 8 shows the TP1 Connector Pinout for the System Controller slot.
Table 9 shows the TP2 Connector Pinout for the System Timing slot.
Table 10 shows the XP3 Connector Pinout for the System Timing slot.
Table 11 shows the XP4 Connector Pinout for the System Timing slot.
Table 12 shows the P1 connector pinout for the peripheral slots.
Table 13 shows the P2 connector pinout for the peripheral slots.
Table 14 shows the P1 connector pinout for the Hybrid peripheral slots.
Table 15 shows the XP3 Connector Pinout for the Hybrid peripheral slots.
Table 16 shows the XP4 Connector Pinout for the Hybrid peripheral slots.
For more detailed information, refer to the PXI-5 PXI Express Hardware
Specification, Revision 2.0. Contact the PXI Systems Alliance for a copy
of the specification.