National Instruments 779640-01 User manual

USER GUIDE AND SPECIFICATIONS
NI USB-6525
This user guide describes how to use the National Instruments USB-6525
data acquisition (DAQ) device.
Introduction
The NI USB-6525 is a full-speed USB 2.0 device that provides
eight ±60 VDC channel-to-channel isolated digital inputs (DI),
eight 60 VDC/30 Vrms channel-to-channel isolated solid-state relay (SSR)
outputs, and a 32-bit counter.
Figure 1. USB-6525 Top View
1 USB Cable Strain Relief
1

USB-6525 User Guide and Specifications 2 ni.com
Figure 2. USB-6525 Back View
Installing Software
Software support for the USB-6525 for Windows 2000/XP is provided by
NI-DAQmx.
The NI-DAQmx CD contains example programs that you can use to get
started programming with the USB-6525. Refer to the NI-DAQmx for USB
Devices Getting Started Guide, that shipped with your device and is also
accessible from Start»All Programs»National Instruments»NI-DAQ
for more information.
Note For information about non-Windows operating system support, refer to ni.com/
info and enter rddqld.
Hardware
The block diagram in Figure 3 shows key functional components of the
USB-6525.
Figure 3. USB-6525 Block Diagram
P0.<0..7>A/B
P1.<0..7>+/–
Digital I/O Terminal Block
Vbus
Full-Speed USB Interface
USB
SSRs
P0
P1
USB Microcontroller
Current-
Limiting
Isolated
Inputs

©National Instruments Corporation 3 USB-6525 User Guide and Specifications
Refer to the Safety Guidelines section of this document for important safety
information.
Setting Up Hardware
Complete the following steps to set up the hardware:
1. Install combicon screw terminal blocks by inserting them into the
combicon jacks.
Note The USB-6525 kit ships with signal labels. You can apply the signal labels on the
screw terminal blocks for easy signal identification.
2. Refer to Table 1 and Figure 4 for label orientation and affix provided
signal labels to the screw terminal blocks. Insert the screw terminal
blocks into their respective matching combicon jacks. Refer to
Figure 4 for more information about signal label orientation.
Figure 4. Signal Label Application Diagram
3. Connect the wiring to the appropriate screw terminals.
1 Overlay Label with Pin Orientation Guides
2 Combicon Jack
3 Screw Terminal Blocks
4 Signal Labels
4
3
3
2
1
4

USB-6525 User Guide and Specifications 4 ni.com
I/O Connector
The USB-6525 device ships with two detachable terminal blocks for digital
signals. Each individual terminal accepts a wire gauge between
16 AWG–28 AWG.
Table 1. Digital Terminal Assignments
Module Terminal Signal Module Terminal Signal
1P0.0A 17 P1.0+
2P0.0B 18 P1.0–
3P0.1A 19 P1.1+
4P0.1B 20 P1.1–
5P0.2A 21 P1.2+
6P0.2B 22 P1.2–
7P0.3A 23 P1.3+
8P0.3B 24 P1.3–
9P0.4A 25 P1.4+
10 P0.4B 26 P1.4–
11 P0.5A 27 P1.5+
12 P0.5B 28 P1.5–
13 P0.6A 29 P1.6+
14 P0.6B 30 P1.6–
15 P0.7A 31 P1.7+/PFI 0+
16 P0.7B 32 P1.7–/PFI 0–

©National Instruments Corporation 5 USB-6525 User Guide and Specifications
Signal Descriptions
Table 2 describes the signals available on the I/O connectors.
Features
The NI 6525 features digital filtering, change detection, programmable
power-up output states, and a watchdog timer.
Digital Filtering
Use the digital filter option available on the NI 6525 input lines to eliminate
glitches on input data. When used with change detection, filtering can also
reduce the number of changes to examine and process.
You can configure the digital input channels to pass through a digital filter,
and you can program the filter interval the filter uses. The filter blocks
pulses that are shorter than half of the specified filter interval and passes
pulses that are longer than the specified interval. Intermediate-length
pulses—pulses longer than half of the interval but less than the
interval—may or may not pass the filter.
The filter operates on the inputs from the optocouplers. The optocouplers
turn on faster than they turn off, passing rising edges faster than falling
Table 2. Signal Descriptions
Signal Name Direction Description
P0.<0..7>A/B Output Solid-state relay 60 VDC/30 Vrms (42.4 Vpk) output
P1.<0..6>+/– Input ±60 VDC digital input.
P1.<0..6>+ corresponds to the positive input terminal.
P1.<0..6>– corresponds to the negative input terminal.
P1.7+/– or PFI 0+/– Input This channel is configurable as either a digital input or
an event counter.
Digital Input Signal—±60 VDC digital input.
P1.7+ corresponds to the positive input terminal.
P1.7– corresponds to the negative input terminal.
CTR—As a counter, this signal can be used as an event
counter input source.
PFI 0+ corresponds to the positive counter terminal.
PFI 0– corresponds to the negative counter terminal.

USB-6525 User Guide and Specifications 6 ni.com
edges. The optocouplers can therefore subtract up to 150 μs from a low
pulse.
Table 3 lists the pulse widths guaranteed to be passed and blocked.
You can enable filtering on as many input lines as is necessary for your
application. All filtered lines share the same timing interval, which ranges
from 120 μs to 2600 ms.
Internally, the filter uses two clocks: the sample clock and the filter clock.
The sample clock has a 40 μs period1. The filter clock is generated by a
counter and has a period equal to one half of the specified timing interval.
The input signal is sampled on each rising edge of the sample clock, which
is every 40 μs1. A change in the input signal is recognized only if it
maintains its new state for at least two consecutive rising edges of the filter
clock.
The filter clock is programmable and allows you to control how long a
pulse must last to be recognized. The sample clock provides a fast sample
rate to ensure that input pulses remain constant between filter clocks.
Table 3. NI 6525 Digital Filtering
Filter Interval
Pulse Width Passed Pulse Width Blocked
Low Pulse High Pulse Low Pulse High Pulse
tinterval tinterval + 150 μs tinterval tinterval/2 (tinterval/2) – 150 μs
1 The accuracy of the sample clock is ±1.5%.

©National Instruments Corporation 7 USB-6525 User Guide and Specifications
Digital Filtering Example
Figure 5 shows a filter configuration with a tinterval filter interval
(tinterval/2 filter clock).
Figure 5. Digital Filtering Example
In periods A and B, the filter blocks the glitches because the external signal
does not remain steadily high from one rising edge of the filter clock to the
next. In period C, the filter passes the transition because the external signal
remains steadily high. Depending on when the transition occurs, the filter
may require up to two filter clocks—one full filter interval—to pass a
transition. The figure shows a rising (0 to 1) transition. The same filtering
applies to falling (1 to 0) transitions.
Change Detection
You can program the NI 6525 to send an interrupt when a change occurs on
any input line.
The NI 6525 can monitor changes on selected input lines or on all input
lines. It can monitor for rising edges (0 to 1), falling edges (1 to 0), or both.
When an input change occurs, the NI 6525 generates an interrupt, and the
NI-DAQ driver then notifies the software.
Note Excessive change detections can affect system performance. Use digital filtering to
minimize the effects of noisy input lines.
The NI 6525 sends a change detection when any one of the changes occurs,
but it does not report which line changed or if the line was rising or falling.
After a change, you can read the input lines to determine the current line
states. The maximum rate of change detection is determined by the
software response time, which varies from system to system.
HHHHH
HLLHH
HLLHH
A
B
C
Sample Clock
External
Signal
Sampled
Filtered
Signal
External
Signal
Filter
Clock

USB-6525 User Guide and Specifications 8 ni.com
An overflow bit indicates that an additional rising or falling edge has been
detected before the software could process the previous change.
Refer to the software documentation for information about how to set up
and implement the change detection.
Change Detection Example
Table 4 shows a change detection example for six bits of one port.
This example assumes the following line connections:
• Bits 7, 6, 5, and 4 are connected to data lines from a four-bit TTL
output device. The NI 6525 detects any change in the input data so you
can read the new data value.
• Bit 1 is connected to a limit sensor. The NI 6525 detects rising edges
on the sensor, which correspond to over-limit conditions.
• Bit 0 is connected to a switch. The software can react to any switch
closure, which is represented by a falling edge. If the switch closure is
noisy, enable digital filtering for this line.
In this example, the NI 6525 reports rising edges only on bit 1, falling edges
only on bit 0, and rising and falling edges on bits 7, 6, 5, and 4. The NI 6525
reports no changes for bits 3 and 2. After receiving notification of a change,
you can read the port to determine the current values of all eight lines. You
cannot read the state of any lines that are configured for change detection
until the change detection interrupt occurs.
Table 4. Change Detection Example
Bit
76543210
Changes to detect — —
Enable rising-edge
detection
yes yes yes yes no no yes no
Enable falling-edge
detection
yes yes yes yes no no no yes

©National Instruments Corporation 9 USB-6525 User Guide and Specifications
Programmable Power-Up Output States
The default power-up state of the digital output lines is logic low, which
opens the solid-state relays. The lines on output ports are user-configurable
for logic high (closed relay) or logic low (open relay). User-configurable
power-up states are useful for ensuring that the NI 6525 powers up in a
known state.
To use MAX (recommended) to program the power-up states, select
the device and click the Properties button. Refer to the software
documentation for information about how to program the power-up states
using NI-DAQ with LabVIEW or other National Instruments application
development environments (ADEs).
Watchdog Timer
The watchdog timer is a software configurable feature used to set critical
outputs to safe states in the event of a software failure, a system crash, or
any other loss of communication between the application and the NI 6525.
When the watchdog timer is enabled, if the NI 6525 does not receive a
watchdog reset software command within the time specified for the
watchdog timer, the outputs go to a user-defined safe state and remain in
that state until the watchdog timer is disarmed by the application and new
values are written, the NI 6525 is reset, or the computer is restarted. The
expiration signal that indicates an expired watchdog will continue to assert
until the watchdog is disarmed. After the watchdog timer expires, the
NI 6525 ignores any writes until the watchdog timer is disarmed.
You can set the watchdog timer timeout period to specify the amount of
time that must elapse before the watchdog timer expires. The counter on the
watchdog timer is configurable up to (232 – 1) × 40 μs1before it expires.
Digital I/O
USB-6525 has eight channel-to-channel optically isolated inputs,
P1.<0..7>, and eight channel-to-channel optically isolated solid-state relay
outputs, P0.<0..7>. P1.7/PFI 0 can also function as a 32-bit counter. Refer
to the Event Counter section for more information about the counter.
Optically Isolated Inputs
The USB-6525 provides eight channels of isolated digital inputs. These
inputs consist of an optocoupler, a depletion-mode MOSFET-based
current-limiting circuit, and Schottky diode.
1 The accuracy of the sample clock is ±1.5%.

USB-6525 User Guide and Specifications 10 ni.com
Each channel has its own positive and negative terminals. The input range
on the channels is –60 VDC to +60 VDC.
Sensing DC Voltages
The USB-6525 detects a wide range of DC signals, from TTL-like logic
levels to DC power supply levels up to 60 V.
Applying a DC voltage of at least 3.2 V across two input terminals registers
logic high. Applying no voltage or a voltage difference of 1 V or less
registers logic low. DC voltages between 1 V and 3.2 V may not register a
consistent or usable value.
Signal Connection Example
Figure 6 shows signal connections for a power supply and load connected
to an isolated input.
Figure 6. Connecting a Power Supply and Load to the Isolated Input
Caution Use twisted-pair field wiring to reduce EMC noise.
In Figure 6, the USB-6525 is sensing a powered load that is connected to
the power supply through a switch.
Note Power supplies must be within the USB-6525 device range. Refer to the
Specifications section for information about these ranges.
When the switch is open, no current flows through the load and no voltage
is applied to the load or to the USB-6525 input. The digital logic of the
USB-6525 then registers a logic low for the channel. When the switch is
Isolation
Digital
Logic
Computer
Ground
USB-6525
P1.x+
P1.x–
MOSFET-Based
Current-Limiting
Circuitry
Schottky
Load
+
_
Twisted-Pair
Wiring
Vcc
Vsupply