NEC mPD98409 User manual

Document No. S14769EJ1V0IFJ1 (1st edition)
Date Published December 2000 N CP(K)
Printed in Japan
Information
µ
µµ
µ
PD98409 Q&A
(NEASCOT-S40CTM)
ATM LIGHT SAR CONTROLLER
©2000

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[MEMO]

Information S14769EJ1V0IF00 3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmust notbetouchedwithbarehands. Similarprecautionsneed
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins, it is possible that an internalinputlevelmaybegenerateddue to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOS devices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

Information S14769EJ1V0IF00
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NEASCOT-S40C and EEPROM are trademarks of NEC Corporation.
M8E 00.4
The information in this document is current as of May, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
•
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INTRODUCTION
Target Readers This manual is intended for engineers who wish to understand the functions of the
µ
PD98409 and use it when designing application systems.
Purpose This manual aims to answer questions asked by users of this product and has been
prepared as a reference in cases where there are points that users feel require
clarification.
How to Read This Manual Refer to the table of contents for the item that is unclear.
Readers of this manual are required to have general knowledge in the fields of
electricity, logic circuits, and microcontrollers.
When designing, be sure to use the latest user’s manual and/or data sheet.
Related Documents •Data sheet : S12775E
•User’s manual : S12776E
Conventions Data significance : Higher digits on the left, lower digits on the right
Active low : XXX_B (_B following pin or signal name)
Memory map address : Lower addresses on the top, higher addresses on the bottom
Numeric notation : Binary ...............XXXX or XXXXB
Decimal.............XXXX
Hexadecimal.....XXXXh

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CONTENTS
CHAPTER 1 PINS....................................................................................................................................11
Q.1.1 How does the RSTOUT_B pin operate? ...........................................................................................11
CHAPTER 2 PCI INTERFACE................................................................................................................12
Q.2.1 How should the Cache line size of the PCI configuration register be set?.............................................12
Q.2.2 Which PCI commands are issued by the
µ
PD98409 when it is the master?..........................................12
Q.2.3 How should the Latency timer of the PCI configuration register be set? ...............................................12
Q.2.4 What is the function of the Retry timer in the PCI configuration register?..............................................13
Q.2.5 When the
µ
PD98409 is the target, what happens if an invalid command is received? ...........................13
Q.2.6 Are the registers of the
µ
PD98409 mapped to the I/O space or the memory space? .............................13
Q.2.7 Does the
µ
PD98409 support the master operation of AD line driving, known as arbitration parking,
if it is selected by the arbiter when there is no master to request transfer on the PCI bus?.....................13
Q.2.8 Can big endian format be used in PCI bus mode?.............................................................................14
Q.2.9 What is the value of the Revision ID in the PCI configuration register?
Does this value change according to the version? .............................................................................14
Q.2.10 Why is it impossible to write 0 to Status bits 31 to 27 and 24 in the PCI configuration register?..............14
Q.2.11 What are the settings related to burst size when the
µ
PD98409 performs a transfer as the master?.......14
Q.2.12 How long does it take for the EEPROM™ connection check and automatic loading? ............................15
CHAPTER 3 UTOPIA INTERFACE........................................................................................................16
Q.3.1 When should the TCLAV signal be deasserted?................................................................................16
Q.3.2 What is the phase difference (delay) between TCLK and RCLK?........................................................16
Q.3.3 The clocks of UTOPIA (TCLK and RCLK) output the BUSCLK as is. Can any other clocks be used?.....16
Q.3.4 Can the RCLAV signal be deasserted in the middle of a cell transfer during cell-level handshaking?......17
Q.3.5 Does the RENBL_B signal perform the same operation in No drop mode (DR in GMR register = 1)
as in octet or cell-level handshake mode?.........................................................................................17
Q.3.6 What is the status of the Tx7 to Tx0 pins while the TENBL_B signal is inactive (high level)?..................17
Q.3.7 An external PHY device is connected to the UTOPIA interface, but controlled by an external interface.
At this time, is it necessary to use the PHY control interface of the
µ
PD98409?....................................17
CHAPTER 4 CONTROL MEMORY ........................................................................................................18
Q.4.1 The
µ
PD98409 has an on-chip control memory, but is it possible to connect additional memories
such as SRAM externally? ..............................................................................................................18
Q.4.2 How long does it take for the control memory to be automatically initialized after reset?........................18
Q.4.3 Are the contents of the control memory cleared to 0 when the control memory is automatically
initialized after reset?......................................................................................................................18
CHAPTER 5 MAILBOX............................................................................................................................19
Q.5.1 Can a mailbox be set straddling over the boundary of a 64 KB area? ..................................................19
Q.5.2 When does the mailbox become full and how is transmission/reception stopped?.................................19

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CHAPTER 6 TRANSMISSION SCHEDULER ........................................................................................20
Q.6.1 What is the relationship between the scheduler register settings (I, M, and P parameters) and
the actual transmission rate?...........................................................................................................20
Q.6.2 Is the same cell scheduling operation performed with scheduler register settings of I/M = 1/10 and
I/M = 10/100?.................................................................................................................................20
Q.6.3 Is it possible to make the priorities of two or more shapers the same? .................................................20
Q.6.4 Is it possible to control the band between VCs (for example, widen the cell transmission interval
between VC1 and VC2)?.................................................................................................................21
Q.6.5 What is the time set for transmitting one cell in cell transmission scheduling?.......................................21
Q.6.6 What is the relationship between cell transmission scheduling and DMA operations?............................22
Q.6.7 Does the host CPU have to set the A bit of the scheduler register?......................................................22
CHAPTER 7 TRANSMISSION.................................................................................................................23
Q.7.1 Is it possible for the transmit FIFO to overflow and for cells to be discarded?........................................23
Q.7.2 Is there a limit to the size of the transmit queue of each VC configured with a transmit packet
descriptor?.....................................................................................................................................23
Q.7.3 How is transmission performed if SIZE = 0 is set for an AAL-5 transmit packet descriptor?....................23
Q.7.4 If a transmit queue consists of a valid packet descriptor →link pointer →blank packet descriptor
sequence, to what does the Tx queue read pointer of the transmit VC table point on completion of
transmission?.................................................................................................................................24
Q.7.5 Can a packet be added during transmission when the transmit VC is active? .......................................24
Q.7.6 When are the contents of packet descriptor Word0 stored in transmit VC table Word0?.........................25
Q.7.7 Is there a limit to the number of VCs linked to a shaper? ....................................................................25
Q.7.8 Is there any problem if the value of the vacant field (Word1, Word2 bits 31 to 16)
of the transmit packet descriptor is not 0? Are the values on the system memory rewritten? ..................25
Q.7.9 Is there any problem if the value of the vacant field (Word1, Word2 bits 31 to 16)
of the transmit buffer descriptor is not 0? Are the values on the system memory rewritten?...................26
Q.7.10 What does the Packet queue pointer field for transmission indication indicate?.....................................26
Q.7.11 How can the OAM F5 cell be transmitted?.........................................................................................27
CHAPTER 8 RECEPTION........................................................................................................................28
Q.8.1 What will happen if a VPI/VCI value cell not enabled by the receive lookup table has been received,
and is it reported?...........................................................................................................................28
Q.8.2 How is a CRC-10 error reported when a Raw cell is received? Is it possible
to disable error checking?................................................................................................................28
Q.8.3 Is there a limit to the number of batches in the receive pool? ..............................................................29
Q.8.4 Is it possible to temporarily stop reception for each VC?.....................................................................29
Q.8.5 Are there cases in which a receive batch is consumed even if a receive indication that
includes error information has been reported?...................................................................................29
Q.8.6 Is only the user data of AAL-5 CPCS-PDU stored in the receive buffer when an AAL-5 packet is
received?.......................................................................................................................................29
Q.8.7 How should the T1 time register (T1R) be set to detect a T1 error? .....................................................30
Q.8.8 Can the receive pool for Raw cells be shared with the receive pool for AAL-5?.....................................30

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Q.8.9 Pools 0 to 7 are allocated as the receive pools for Raw cells. Can all the pools from 0 to 7
be used for receiving Raw cells, or can only one of the pools from 0 to 7 be used?...............................30
Q.8.10 What is the Alert level of a receive pool descriptor? Are the settings and interrupts of the Alert level
valid for a Raw cell pool? ................................................................................................................30
Q.8.11 What kind of support is there for receive VPI/VCI? When reducing from VPI/VCI 24 bits to
VPI/VCI 15 bits via a setting in the VRR register, how is the area that is invalidated by SHIFT and
MASK processed?..........................................................................................................................31
Q.8.12 How should the UINFO field of the receive VC table and receive indication be used?............................31
Q.8.13 What is the Packet size field in the receive indication?.......................................................................32
CHAPTER 9 TRANSMISSION/RECEPTION...........................................................................................33
Q.9.1 Can the contents of the transmit/receive VC table be changed during transmission or reception? ..........33
Q.9.2 How many bits can be supported for VPI/VCI?..................................................................................33
Q.9.3 To what part is the CRC-32 operation applied? .................................................................................34
Q.9.4 Is the receive indication issued even when a Raw cell is received? .....................................................34
CHAPTER 10 COMMANDS.....................................................................................................................35
Q.10.1 What will happen if the Tx_Ready command is issued to a VC that is transmitting a packet
(active VC)?...................................................................................................................................35
Q.10.2 What will happen if the Close_Channel command is issued with an incorrect setting
for the transmit or receive VC specified by the R/T bit of the command?..............................................35
Q.10.3 When accessing the control memory by using the Indirect_Access command, can two or more
addresses be accessed by issuing the command only once?..............................................................35
Q.10.4 How is the NOP command used? ....................................................................................................36
CHAPTER 11 LOOPBACK......................................................................................................................37
Q.11.1 Is valid data output to the PHY side (UTOPIA interface) in loopback mode?.........................................37
Q.11.2 Does the pin status of the UTOPIA interface affect the transmit/receive operations
of the
µ
PD98409 in loopback mode?................................................................................................37
CHAPTER 12 REGISTERS......................................................................................................................38
Q.12.1 What is the function of the ADDR register?.......................................................................................38
Q.12.2 How are the ECCR and ERDR registers initialized?...........................................................................38
Q.12.3 Can transmission/reception be temporarily halted by clearing the SE and
RE bits of the GMR register during transmission/reception? ...............................................................38
Q.12.4 What is the value of the VER register? .............................................................................................38
CHAPTER 13 JTAG.................................................................................................................................39
Q.13.1 How can the JTAG function be reset when JTAG is not used?............................................................39

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CHAPTER 14 AC/DC CHARACTERISTICS...........................................................................................40
Q.14.1 When +5 V is supplied to the VDD5 pin, how much is the current consumption of the power supply?........40
Q.14.2 Can a 5 V device be directly connected to the UTOPIA interface?
At that time, does the handling of the VDD5 pin influence this connection?.............................................40
CHAPTER 15 OTHER ITEMS.................................................................................................................41
Q.15.1 Access is prohibited for 20 clocks (BUSCLK input) after reset.
Does this mean that access is prohibited only after a hardware reset?.................................................41
Q.15.2 Are there any differences in the initialization of the device between a hardware reset
(input of a low level to the RST_B pin) and a software reset (writing the SWR register)?........................41

Information S14769EJ1V0IF00 11
CHAPTER 1 PINS
Q.1.1
How does the RSTOUT_B pin operate?
A.1.1
The RSTOUT_B pin goes low at the same time as the RST_B pin and holds the low level for 11 to 22 clocks
(BUSCLK input) after the RST_B pin has gone high.
Reference:
µ
PD98409 User’s Manual 2.2.1 (2) PHY device control interface

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CHAPTER 2 PCI INTERFACE
Q.2.1
How should the Cache line size of the PCI configuration register be set?
A.2.1
The Cache line size setting is not related to the burst size when the
µ
PD98409 performs transfer as the master.
The burst size is determined by the settings of the AD, TBE, and SZ fields in the GMR register.
The Cache line size setting, however, is related to PCI commands issued by the
µ
PD98409 (see Q.2.2).
Reference:
µ
PD98409 User’s Manual 4.1.2 Configuration register
Q.2.2
Which PCI commands are issued by the
µ
PD98409 when it is the master?
A.2.2
Refer to 4.1.3 (2) Master transaction in the
µ
PD98409 User’s Manual. Regarding read commands, however, the
command issued differs depending on the Cache line size setting.
When the Cache line size is set to 4, 8, or 16, the commands shown in 4.1.3 (2) (a) Read transaction in the
µ
PD98409 User’s Manual are issued.
When the Cache line size is set to other than 4, 8, or 16, the
µ
PD98409 always issues a memory read command.
Caution is therefore required when using the
µ
PD98409 in a system that performs processing via read command
type identification.
Reference:
µ
PD98409 User’s Manual 4.1.3 (2) Master transaction
Q.2.3
How should the Latency timer of the PCI configuration register be set?
A.2.3
The Latency timer setting is valid when the lower 3 bits of the set value are masked.
In other words, the Latency timer setting should be 0, 8, 16, …, 248.
Reference:
µ
PD98409 User’s Manual 4.1.2 Configuration register

CHAPTER 2 PCI INTERFACE
Information S14769EJ1V0IF00 13
Q.2.4
What is the function of the Retry timer in the PCI configuration register?
A.2.4
The
µ
PD98409 counts Retry, Disconnect, and Latency timeouts as the Retry timer count. If the number of all of
these transfer interruptions exceeds the Retry timer count value, the FERR bit of the GSR register is set and
operation is stopped.
Reference:
µ
PD98409 User’s Manual 4.1.2 Configuration register
Q.2.5
When the
µ
PD98409 is the target, what happens if an invalid command is received?
A.2.5
The
µ
PD98409 does not respond to the transfer (DEVSEL_B does not become active).
Reference:
µ
PD98409 User’s Manual 4.1.3 (1) Slave transaction
Q.2.6
Are the registers of the
µ
PD98409 mapped to the I/O space or the memory space?
A.2.6
Both I/O and memory space can be used. I/O and memory space can also be used simultaneously.
Reference:
µ
PD98409 User’s Manual 4.1.2 Configuration register
Q.2.7
Does the
µ
PD98409 support the master operation of AD line driving, known as arbitration parking, if it is
selected by the arbiter when there is no master to request transfer on the PCI bus?
A.2.7
Yes.
Reference:
µ
PD98409 User’s Manual 4.1.1 Features of PCI bus interface

CHAPTER 2 PCI INTERFACE
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Q.2.8
Can big endian format be used in PCI bus mode?
A.2.8
No. Only little endian format is supported by the
µ
PD98409.
Reference:
µ
PD98409 User’s Manual 4.1.1 Features of PCI bus interface
Q.2.9
What is the value of the Revision ID in the PCI configuration register?
Does this value change according to the version?
A.2.9
The Revision ID is 02h, and is common to all versions. The values of the VER register, a
µ
PD98409 internal
register, differ depending on the version. The VER register can be used to identify the version of the device.
Reference:
µ
PD98409 User’s Manual 4.1.2 Configuration register
Q.2.10
Why is it impossible to write 0 to Status bits 31 to 27 and 24 in the PCI configuration register?
A.2.10
Write operations to the Status register conform to the PCI standard. When 0 is written to a bit, the bit holds the
value, and when 1 is written to that bit, it is cleared to 0.
Reference:
µ
PD98409 User’s Manual 4.1.2 Configuration register
Q.2.11
What are the settings related to burst size when the
µ
PD98409 performs a transfer as the master?
A.2.11
The burst size is determined by the settings of the AD, TBE, and SZ fields in the GMR register. The Cache line
size setting in the PCI configuration register is not related to the burst size. For details about the burst size, refer
to 4.1.3 PCI bus transaction in the
µ
PD98409 User’s Manual.
Reference:
µ
PD98409 User’s Manual 4.1.3 (6) Burst transfer

CHAPTER 2 PCI INTERFACE
Information S14769EJ1V0IF00 15
Q.2.12
How long does it take for the EEPROM™ connection check and automatic loading?
A.2.12
The connection check takes about 600 clocks (BUSCLK input) and automatic loading about 2400 clocks (BUSCLK
input).
Reference:
µ
PD98409 User’s Manual 4.2 Serial EEPROM Interface

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CHAPTER 3 UTOPIA INTERFACE
Q.3.1
When should the TCLAV signal be deasserted?
A.3.1
Deassert it between H2 (2nd byte of the cell header) and P44 (44th byte of the payload). Do not deassert it at H1.
TSOC
Tx 7 t o T x 0
TxCLAV
T ENBL _ B
TCLK
5 85 75 65 55 45 35 25 15 054321
H2 P4 5P4 4 XX H1X X
P4 8
P4 7P4 6
Reference:
µ
PD98409 User’s Manual 4.3.1 (1) Transmit interface
Q.3.2
What is the phase difference (delay) between TCLK and RCLK?
A.3.2
The phase difference between TCLK and RCLK has not been formally established.
Reference:
µ
PD98409 User’s Manual 4.3.1 UTOPIA interface
Q.3.3
The clocks of UTOPIA (TCLK and RCLK) output the BUSCLK as is. Can any other clocks be used?
A.3.3
No.
Reference:
µ
PD98409 User’s Manual 4.3.1 UTOPIA interface

CHAPTER 3 UTOPIA INTERFACE
Information S14769EJ1V0IF00 17
Q.3.4
Can the RCLAV signal be deasserted in the middle of a cell transfer during cell-level handshaking?
A.3.4
Yes. The
µ
PD98409 does not fetch the data of Rx7 to Rx0 while the RCLAV signal is deasserted. When the
RCLAV signal is asserted again, it starts fetching Rx7 to Rx0 as valid data.
Reference:
µ
PD98409 User’s Manual 4.3.1 (2) Receive interface
Q.3.5
Does the RENBL_B signal perform the same operation in No drop mode (DR in GMR register = 1) as in octet or
cell-level handshake mode?
A.3.5
Yes. For details of the operation, refer to 4.3.1 UTOPIA interface in the
µ
PD98409 User’s Manual.
Reference:
µ
PD98409 User’s Manual 4.3.1 (2) Receive interface
Q.3.6
What is the status of the Tx7 to Tx0 pins while the TENBL_B signal is inactive (high level)?
A.3.6
The Tx7 to Tx0 pins output 0.
Reference:
µ
PD98409 User’s Manual 4.3.1 UTOPIA interface
Q.3.7
An external PHY device is connected to the UTOPIA interface, but controlled by an external interface. At this
time, is it necessary to use the PHY control interface of the
µ
PD98409?
A.3.7
It is all right not to use the PHY control interface of the
µ
PD98409. In this case, the PHINT_B and CD0 to CD7
pins must be externally pulled up. All other pins may be left open.
Reference:
µ
PD98409 User’s Manual 4.3.2 PHY device control interface

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18
CHAPTER 4 CONTROL MEMORY
Q.4.1
The
µ
PD98409 has an on-chip control memory, but is it possible to connect additional memories such as SRAM
externally?
A.4.1
SRAM cannot be additionally connected. The
µ
PD98409 supports 64 VCs (as the on-chip control memory) for
transmission/reception.
Reference:
µ
PD98409 User’s Manual 5.2 Setting of Control Memory
Q.4.2
How long does it take for the control memory to be automatically initialized after reset?
A.4.2
It takes about 1024 clocks (BUSCLK input).
Reference:
µ
PD98409 User’s Manual 5.1 (2) Initializing control memory
Q.4.3
Are the contents of the control memory cleared to 0 when the control memory is automatically initialized after
reset?
A.4.3
When the control memory of the
µ
PD98409 is automatically initialized, the entire control memory is cleared to 0,
after which block numbers are written.
Reference:
µ
PD98409 User’s Manual 5.1 (2) Initializing control memory

Information S14769EJ1V0IF00 19
CHAPTER 5 MAILBOX
Q.5.1
Can a mailbox be set straddling over the boundary of a 64 KB area?
A.5.1
No, it cannot. A mailbox must fit into the area of 64 KB set by the MSH register (the higher 16 bits of the mailbox
start address). If the mailbox is used at the maximum size (about 64 KB), the MSL register must be cleared to 0.
Mailbox
Mailbox
XXX10000h
OK NG
XXX20000h XXX20000h
64 KB boundary
64 KB boundary
System memory System memory
XXX10000h
64 KB boundary
64 KB boundary
Reference:
µ
PD98409 User’s Manual 5.3.1 Setting of mailbox
Q.5.2
When does the mailbox become full and how is transmission/reception stopped?
A.5.2
The mailbox full notice is issued when the corresponding indication has been correctly written to the mailbox
making it full. Transmission/reception is stopped when an attempt is made to write the next indication to the full
mailbox.
Reference:
µ
PD98409 User’s Manual 5.3.2 Operation of mailbox

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20
CHAPTER 6 TRANSMISSION SCHEDULER
Q.6.1
What is the relationship between the scheduler register settings (I, M, and P parameters) and the actual
transmission rate?
A.6.1
The scheduler register (I, M, and P parameters) is set in cell units. The average rate is set by I/M, which is the
valid cell transmission of I cells per M cell. For the peak rate, the valid cell interval is set as the P cell interval.
The actual transmission rate set by the scheduler register is dependent on the speed (line speed) of the PHY
device connected at the line side. The relationship between the line speed and transmission rate can be
expressed as follows:
Average rate = I/M ×Line speed
Peak rate = Line speed/(P + 1)
Here is an example of a setting where the line speed is 155.52 Mbps.
Example Line speed = 155.52 Mbps, Average rate = 38.88 Mbps, Peak rate = 51.84 Mbps
I/M = 38.88/155.52 = 1/4
P = (155.52/51.84) −1 = 2
Reference:
µ
PD98409 User’s Manual 5.4.4 (4) Scheduler register
Q.6.2
Is the same cell scheduling operation performed with scheduler register settings of I/M = 1/10 and I/M = 10/100?
A.6.2
Yes.
Reference:
µ
PD98409 User’s Manual 5.4.4 (4) Scheduler register
Q.6.3
Is it possible to make the priorities of two or more shapers the same?
A.6.3
Yes. The priorities of the shapers can be made the same by setting the same value to the PRIORITY field of the
scheduler register of each shaper. If a cell transmission timing conflict between shapers of the same priority
occurs, cells are sequentially transmitted to the shapers by using a round-robin algorithm.
Reference:
µ
PD98409 User’s Manual 5.4.4 (4) Scheduler register