Nuvoton NuMicro NUC029 Series Product manual

NuMicro® NUC029LEE/NUC029SEE
32-bit Arm®Cortex®-M0 Microcontroller
Aug, 2018 Page 1of 497 Rev 1.00
NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
NuMicro® NUC029 Series
NUC029LEE/NUC029SEE
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro®microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

NuMicro® NUC029LEE/NUC029SEE
32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
TABLE OF CONTENTS
LIST OF FIGURES .....................................................................................................7
LIST OF TABLES.....................................................................................................11
1GENERAL DESCRIPTION...................................................................................12
2FEATURES ..........................................................................................................13
3ABBREVIATIONS................................................................................................16
4PARTS INFORMATION LIST AND PIN CONFIGURATION................................18
4.1 NuMicro®NUC029 Series Selection Code...................................................18
4.2 NuMicro®NUC029 Series Selection Guide ..................................................19
4.3 Pin Configuration.................................................................................20
4.3.1 NuMicro®NUC029LEE/NUC029SEE Pin Diagram .............................................. 20
4.4 Pin Description....................................................................................22
4.4.1 NuMicro®NUC029LEE/NUC029SEE Pin Description........................................... 22
5BLOCK DIAGRAM...............................................................................................27
5.1 NuMicro®NUC029LEE/NUC029SEE Block Diagram ......................................27
6FUNCTIONAL DESCRIPTION.............................................................................28
6.1 ARM®Cortex®-M0 Core.........................................................................28
6.2 System Manager .................................................................................30
6.2.1 Overview ................................................................................................ 30
6.2.2 System Reset .......................................................................................... 30
6.2.3 System Power Distribution ........................................................................... 31
6.2.4 System Memory Map ................................................................................. 32
6.2.5 Register Lock........................................................................................... 33
6.2.6 Auto Trim................................................................................................ 34
6.2.7 Register Map ........................................................................................... 36
6.2.8 Register Description................................................................................... 37
6.2.9 System Timer (SysTick) .............................................................................. 74
6.2.10Nested Vectored Interrupt Controller (NVIC)...................................................... 79
6.2.11System Control....................................................................................... 105
6.3 Clock Controller................................................................................. 113
6.3.1 Overview .............................................................................................. 113
6.3.2 System Clock and SysTick Clock ................................................................. 116
6.3.3 Power-down Mode Clock........................................................................... 117
6.3.4 Frequency Divider Output.......................................................................... 117

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32-bit Arm®Cortex®-M0 Microcontroller
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6.3.5 Register Map ......................................................................................... 119
6.3.6 Register Description................................................................................. 120
6.4 Flash Memory Controller (FMC) .............................................................142
6.4.1 Overview .............................................................................................. 142
6.4.2 Features............................................................................................... 142
6.4.3 Block Diagram........................................................................................ 143
6.4.4 Functional Description .............................................................................. 144
6.4.5 Register Map ......................................................................................... 154
6.4.6 Register Description................................................................................. 155
6.5 External Bus Interface (EBI).................................................................. 164
6.5.1 Overview .............................................................................................. 164
6.5.2 Features............................................................................................... 164
6.5.3 Block Diagram........................................................................................ 165
6.5.4 Functional Description .............................................................................. 165
6.5.5 Register Map ......................................................................................... 171
6.5.6 Register Description................................................................................. 172
6.6 General Purpose I/O (GPIO) .................................................................176
6.6.1 Overview .............................................................................................. 176
6.6.2 Features............................................................................................... 176
6.6.3 Basic Configuration.................................................................................. 177
6.6.4 Functional Description .............................................................................. 177
6.6.5 Register Map ......................................................................................... 180
6.6.6 Register Description................................................................................. 183
6.7 PDMA Controller (PDMA)..................................................................... 195
6.7.1 Overview .............................................................................................. 195
6.7.2 Features............................................................................................... 195
6.7.3 Block Diagram........................................................................................ 196
6.7.4 Basic Configuration.................................................................................. 197
6.7.5 Functional Description .............................................................................. 197
6.7.6 Register Map ......................................................................................... 200
6.7.7 Register Description................................................................................. 202
6.8 Timer Controller (TIMER) .....................................................................233
6.8.1 Overview .............................................................................................. 233
6.8.2 Features............................................................................................... 233
6.8.3 Block Diagram........................................................................................ 234

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32-bit Arm®Cortex®-M0 Microcontroller
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6.8.4 Basic Configuration.................................................................................. 236
6.8.5 Functional Description .............................................................................. 236
6.8.6 Register Map ......................................................................................... 239
6.8.7 Register Description................................................................................. 241
6.9 PWM Generator and Capture Timer (PWM)............................................... 250
6.9.1 Overview .............................................................................................. 250
6.9.2 Features............................................................................................... 251
6.9.3 Block Diagram........................................................................................ 252
6.9.4 Basic Configuration.................................................................................. 255
6.9.5 Functional Description .............................................................................. 255
6.9.6 Register Map ......................................................................................... 265
6.9.7 Register Description................................................................................. 267
6.10Watchdog Timer (WDT).......................................................................295
6.10.1Overview .............................................................................................. 295
6.10.2Features............................................................................................... 295
6.10.3Block Diagram........................................................................................ 296
6.10.4Basic Configuration.................................................................................. 297
6.10.5Functional Description .............................................................................. 297
6.10.6Register Map ......................................................................................... 299
6.10.7Register Description................................................................................. 300
6.11Window Watchdog Timer (WWDT).......................................................... 303
6.11.1Overview .............................................................................................. 303
6.11.2Features............................................................................................... 303
6.11.3Block Diagram........................................................................................ 303
6.11.4Basic Configuration.................................................................................. 304
6.11.5Functional Description .............................................................................. 304
6.11.6Register Map ......................................................................................... 307
6.11.7Register Description................................................................................. 308
6.12Real Time Clock (RTC)........................................................................313
6.12.1Overview .............................................................................................. 313
6.12.2Features............................................................................................... 313
6.12.3Block Diagram........................................................................................ 314
6.12.4Basic Configuration.................................................................................. 314
6.12.5Functional Description .............................................................................. 314
6.12.6Register Map ......................................................................................... 318

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32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
6.12.7Register Description................................................................................. 320
6.13UART Interface Controller (UART) ..........................................................336
6.13.1Overview .............................................................................................. 336
6.13.2Features............................................................................................... 336
6.13.3Block Diagram........................................................................................ 337
6.13.4Basic Configuration.................................................................................. 338
6.13.5Functional Description .............................................................................. 339
6.13.6Register Map ......................................................................................... 360
6.13.7Register Description................................................................................. 362
6.14I2C Serial Interface Controller (I2C).......................................................... 389
6.14.1Overview .............................................................................................. 389
6.14.2Features............................................................................................... 389
6.14.3Basic Configuration.................................................................................. 390
6.14.4Block Diagram........................................................................................ 390
6.14.5Functional Description .............................................................................. 390
6.14.6Example for Random Read on EEPROM ....................................................... 403
6.14.7Register Map ......................................................................................... 405
6.14.8Register Description................................................................................. 406
6.15Serial Peripheral Interface (SPI) .............................................................416
6.15.1Overview .............................................................................................. 416
6.15.2Features............................................................................................... 416
6.15.3Block Diagram........................................................................................ 417
6.15.4Basic Configuration.................................................................................. 417
6.15.5Functional Description .............................................................................. 417
6.15.6Timing Diagram ...................................................................................... 425
6.15.7Programming Examples............................................................................ 428
6.15.8Register Map ......................................................................................... 430
6.15.9Register Description................................................................................. 431
6.16USB Device Controller (USBD) ..............................................................447
6.16.1Overview .............................................................................................. 447
6.16.2Features............................................................................................... 447
6.16.3Block Diagram........................................................................................ 448
6.16.4Basic Configuration.................................................................................. 448
6.16.5Functional Description .............................................................................. 448
6.16.6Register Map ......................................................................................... 453

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32-bit Arm®Cortex®-M0 Microcontroller
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6.16.7Register Description................................................................................. 455
6.17Analog-to-Digital Converter (ADC) .......................................................... 472
6.17.1Overview .............................................................................................. 472
6.17.2Features............................................................................................... 472
6.17.3Block Diagram........................................................................................ 473
6.17.4Basic Configuration.................................................................................. 473
6.17.5Functional Description .............................................................................. 474
6.17.6Register Map ......................................................................................... 481
6.17.7Register Description................................................................................. 482
7ELECTRICAL CHARACTERISTICS..................................................................494
8PACKAGE DIMENSIONS..................................................................................495
8.1 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm)..............................................495
8.2 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)..............................................496
9REVISION HISTORY..........................................................................................497

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32-bit Arm®Cortex®-M0 Microcontroller
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LIST OF FIGURES
Figure 4.1-1 NuMicro®NUC029 Series Selection Code................................................................ 18
Figure 4.3-1 NuMicro®NUC029SEE LQFP 64-pin Diagram ......................................................... 20
Figure 4.3-2 NuMicro®NUC029LEE LQFP 48-pin Diagram.......................................................... 21
Figure 5.1-1 NuMicro®NUC029LEE/NUC029SEE Block Diagram ............................................... 27
Figure 6.1-1 Functional Controller Diagram................................................................................... 28
Figure 6.2-1 NuMicro®NUC029LEE/NUC029SEE Power Distribution Diagram........................... 31
Figure 6.3-1 Clock Generator Block Diagram.............................................................................. 114
Figure 6.3-2 Clock Generator Global View Diagram.................................................................... 115
Figure 6.3-3 System Clock Block Diagram .................................................................................. 116
Figure 6.3-4 SysTick Clock Control Block Diagram..................................................................... 116
Figure 6.3-5 Clock Source of Frequency Divider......................................................................... 117
Figure 6.3-6 Frequency Divider Block Diagram........................................................................... 118
Figure 6.4-1 Flash Memory Control Block Diagram..................................................................... 143
Figure 6.4-2 Flash Memory Organization .................................................................................... 145
Figure 6.4-3 Program Executing Range for Booting from APROM and LDROM ........................ 149
Figure 6.4-4 Executable Range of Code with IAP Function Enabled.......................................... 150
Figure 6.4-5 Example Flow of Boot Selection by BS Bit.............................................................. 151
Figure 6.4-6 ISP Flow Example ................................................................................................... 152
Figure 6.5-1 EBI Block Diagram.................................................................................................. 165
Figure 6.5-2 Connection of 16-bit EBI Data Width with 16-bit Device........................................ 166
Figure 6.5-3 Connection of 8-bit EBI Data Width with 8-bit Device............................................. 166
Figure 6.5-4 Timing Control Waveform for 16-bit Data Width...................................................... 168
Figure 6.5-5 Timing Control Waveform for 8-bit Data Width....................................................... 169
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle........................................................ 170
Figure 6.6-1 Push-Pull Output...................................................................................................... 177
Figure 6.6-2 Open-Drain Output .................................................................................................. 178
Figure 6.6-3 Quasi-bidirectional I/O Mode................................................................................... 178
Figure 6.7-1 DMA Controller Block Diagram................................................................................ 196
Figure 6.7-2 CRC Generator Block Diagram ............................................................................... 197
Figure 6.8-1 Timer Controller Block Diagram .............................................................................. 234
Figure 6.8-2 Clock Source of Timer Controller ............................................................................ 235
Figure 6.8-3 Continuous Counting Mode..................................................................................... 237
Figure 6.9-1 PWM Generator 0 Clock Source Control................................................................. 252
Figure 6.9-2 PWM Generator 0 Architecture Diagram................................................................. 252
Figure 6.9-3 PWM Generator 2 Clock Source Control................................................................. 253
Figure 6.9-4 PWM Generator 2 Architecture Diagram................................................................. 253

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Figure 6.9-5 PWM Generator 4 Clock Source Control................................................................. 254
Figure 6.9-6 PWM Generator 4 Architecture Diagram................................................................. 254
Figure 6.9-7 Legend of Internal Comparator Output of PWM-Timer ........................................... 255
Figure 6.9-8 PWM-Timer Operation Timing................................................................................. 256
Figure 6.9-9 PWM Edge-aligned Interrupt Generate Timing Waveform...................................... 256
Figure 6.9-10 Center-aligned Type Output Waveform................................................................. 257
Figure 6.9-11 PWM Center-aligned Interrupt Generate Timing Waveform ................................. 258
Figure 6.9-12 PWM Double Buffering Illustration......................................................................... 259
Figure 6.9-13 PWM Controller Output Duty Ratio........................................................................ 259
Figure 6.9-14 Paired-PWM Output with Dead-zone Generation Operation ................................ 260
Figure 6.9-15 PWM trigger ADC to conversion in Center-aligned type Timing Waveform.......... 260
Figure 6.9-16 Capture Operation Timing ..................................................................................... 261
Figure 6.9-17 PWM Group A PWM-Timer Interrupt Architecture Diagram.................................. 262
Figure 6.9-18 PWM Group B PWM-Timer Interrupt Architecture Diagram.................................. 262
Figure 6.10-1 Watchdog Timer Clock Control.............................................................................. 296
Figure 6.10-2 Watchdog Timer Block Diagram............................................................................ 296
Figure 6.10-3 Watchdog Timer Time-out Interval and Reset Period Timing ............................... 298
Figure 6.11-1 Window Watchdog Timer Clock Control................................................................ 303
Figure 6.11-2 Window Watchdog Timer Block Diagram.............................................................. 304
Figure 6.11-3 Window Watchdog Timer Reset and Reload Behavior......................................... 305
Figure 6.12-1 RTC Block Diagram............................................................................................... 314
Figure 6.13-1 UART Clock Control Diagram................................................................................ 337
Figure 6.13-2 UART Block Diagram ............................................................................................ 338
Figure 6.13-3 Transmit Delay Time Operation............................................................................. 341
Figure 6.13-4 Auto Flow Control Block Diagram.......................................................................... 345
Figure 6.13-5 UART CTS Auto Flow Control Enabled................................................................. 345
Figure 6.13-6 UART RTS Auto Flow Control Enabled................................................................. 346
Figure 6.13-7 UART RTS Flow with Software Control................................................................ 346
Figure 6.13-8 IrDA Control Block Diagram .................................................................................. 347
Figure 6.13-9 IrDA TX/RX Timing Diagram ................................................................................. 348
Figure 6.13-10 Structure of LIN Frame........................................................................................ 348
Figure 6.13-11 Structure of LIN Byte ........................................................................................... 349
Figure 6.13-12 Break Detection in LIN Mode............................................................................... 351
Figure 6.13-13 LIN Frame ID and Parity Format ......................................................................... 352
Figure 6.13-14 LIN Sync Field Measurement.............................................................................. 354
Figure 6.13-15 UA_BAUD Update Sequence in Automatic Resynchronization Mode when
LINS_DUM_EN (UA_LIN_CTL[3]) = 1.................................................................................. 355

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32-bit Arm®Cortex®-M0 Microcontroller
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Figure 6.13-16 UA_BAUD Update Sequence in Automatic Resynchronization Mode when
LINS_DUM_EN (UA_LIN_CTL[3])= 0................................................................................... 355
Figure 6.13-17 RS-485 RTS Driving Level in Auto Direction Mode............................................. 358
Figure 6.13-18 RS-485 RTS Driving Level with Software Control.............................................. 358
Figure 6.13-19 Structure of RS-485 Frame ................................................................................. 359
Figure 6.14-1 I2C Controller Block Diagram................................................................................. 390
Figure 6.14-2 I2C Bus Timing....................................................................................................... 391
Figure 6.14-3 I2C Protocol........................................................................................................... 391
Figure 6.14-4 START and STOP Conditions............................................................................... 392
Figure 6.14-5 Bit Transfer on the I2C Bus.................................................................................... 393
Figure 6.14-6 Acknowledge on the I2C Bus................................................................................. 393
Figure 6.14-7 Master Transmits Data to Slave............................................................................ 393
Figure 6.14-8 Master Reads Data from Slave ............................................................................. 394
Figure 6.14-9 Control I2C Bus according to Current I2C Status................................................... 394
Figure 6.14-10 Master Transmitter Mode Control Flow............................................................... 395
Figure 6.14-11 Master Receiver Mode Control Flow................................................................... 396
Figure 6.14-12 Save Mode Control Flow..................................................................................... 397
Figure 6.14-13 GC Mode ............................................................................................................. 398
Figure 6.14-14 Arbitration Lost..................................................................................................... 399
Figure 6.14-15 I2C Data Shifting Direction................................................................................... 400
Figure 6.14-16 I2C Time-out Count Block Diagram ..................................................................... 402
Figure 6.14-17 EEPROM Random Read..................................................................................... 403
Figure 6.14-18 Protocol of EEPROM Random Read .................................................................. 404
Figure 6.15-1 SPI Block Diagram................................................................................................. 417
Figure 6.15-2 SPI Master Mode Application Block Diagram........................................................ 418
Figure 6.15-3 SPI Slave Mode Application Block Diagram.......................................................... 418
Figure 6.15-4 32-Bit in One Transaction...................................................................................... 419
Figure 6.15-5 Variable Bus Clock Frequency.............................................................................. 421
Figure 6.15-6 Byte Reorder Function........................................................................................... 421
Figure 6.15-7 Timing Waveform for Byte Suspend...................................................................... 422
Figure 6.15-8 Bit Sequence of Dual Output Mode....................................................................... 423
Figure 6.15-9 Bit Sequence of Dual Input Mode.......................................................................... 423
Figure 6.15-10 FIFO Mode Block Diagram.................................................................................. 424
Figure 6.15-11 SPI Timing in Master Mode ................................................................................. 426
Figure 6.15-12 SPI Timing in Master Mode (Alternate Phase of SPI Bus Clock)........................ 426
Figure 6.15-13 SPI Timing in Slave Mode ................................................................................... 427
Figure 6.15-14 SPI Timing in Slave Mode (Alternate Phase of SPI Bus Clock).......................... 427

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32-bit Arm®Cortex®-M0 Microcontroller
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Figure 6.16-1 USB Device Block Diagram................................................................................... 448
Figure 6.16-2 Wake-up Interrupt Operation Flow ....................................................................... 450
Figure 6.16-3 Endpoint SRAM Structure ..................................................................................... 451
Figure 6.16-4 Setup Transaction Followed by Data IN Transaction............................................ 452
Figure 6.16-5 Data Out Transfer.................................................................................................. 452
Figure 6.17-1 ADC Controller Block Diagram.............................................................................. 473
Figure 6.17-2 ADC Clock Control................................................................................................. 474
Figure 6.17-3 Single Mode Conversion Timing Diagram............................................................. 475
Figure 6.17-4 Single-Cycle Scan on Enabled Channels Timing Diagram................................... 476
Figure 6.17-5 Continuous Scan on Enabled Channels Timing Diagram..................................... 477
Figure 6.17-6 VBG for Measuring AVDD Application Block Diagram ............................................. 478
Figure 6.17-7 A/D Conversion Result Monitor Logics Diagram................................................... 479
Figure 6.17-8 A/D Controller Interrupt.......................................................................................... 480
Figure 6.17-9 ADC Single-end Input Conversion Voltage and Conversion Result Mapping....... 483
Figure 6.17-10 ADC Differential Input Conversion Voltage and Conversion Result Mapping..... 484