Nuvoton NuMicro NUC029 Series Product manual

NuMicro® NUC029LEE/NUC029SEE
32-bit Arm®Cortex®-M0 Microcontroller
Aug, 2018 Page 1of 497 Rev 1.00
NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
NuMicro® NUC029 Series
NUC029LEE/NUC029SEE
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro®microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
LIST OF FIGURES .....................................................................................................7
LIST OF TABLES.....................................................................................................11
1GENERAL DESCRIPTION...................................................................................12
2FEATURES ..........................................................................................................13
3ABBREVIATIONS................................................................................................16
4PARTS INFORMATION LIST AND PIN CONFIGURATION................................18
4.1 NuMicro®NUC029 Series Selection Code...................................................18
4.2 NuMicro®NUC029 Series Selection Guide ..................................................19
4.3 Pin Configuration.................................................................................20
4.3.1 NuMicro®NUC029LEE/NUC029SEE Pin Diagram .............................................. 20
4.4 Pin Description....................................................................................22
4.4.1 NuMicro®NUC029LEE/NUC029SEE Pin Description........................................... 22
5BLOCK DIAGRAM...............................................................................................27
5.1 NuMicro®NUC029LEE/NUC029SEE Block Diagram ......................................27
6FUNCTIONAL DESCRIPTION.............................................................................28
6.1 ARM®Cortex®-M0 Core.........................................................................28
6.2 System Manager .................................................................................30
6.2.1 Overview ................................................................................................ 30
6.2.2 System Reset .......................................................................................... 30
6.2.3 System Power Distribution ........................................................................... 31
6.2.4 System Memory Map ................................................................................. 32
6.2.5 Register Lock........................................................................................... 33
6.2.6 Auto Trim................................................................................................ 34
6.2.7 Register Map ........................................................................................... 36
6.2.8 Register Description................................................................................... 37
6.2.9 System Timer (SysTick) .............................................................................. 74
6.2.10Nested Vectored Interrupt Controller (NVIC)...................................................... 79
6.2.11System Control....................................................................................... 105
6.3 Clock Controller................................................................................. 113
6.3.1 Overview .............................................................................................. 113
6.3.2 System Clock and SysTick Clock ................................................................. 116
6.3.3 Power-down Mode Clock........................................................................... 117
6.3.4 Frequency Divider Output.......................................................................... 117

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6.3.5 Register Map ......................................................................................... 119
6.3.6 Register Description................................................................................. 120
6.4 Flash Memory Controller (FMC) .............................................................142
6.4.1 Overview .............................................................................................. 142
6.4.2 Features............................................................................................... 142
6.4.3 Block Diagram........................................................................................ 143
6.4.4 Functional Description .............................................................................. 144
6.4.5 Register Map ......................................................................................... 154
6.4.6 Register Description................................................................................. 155
6.5 External Bus Interface (EBI).................................................................. 164
6.5.1 Overview .............................................................................................. 164
6.5.2 Features............................................................................................... 164
6.5.3 Block Diagram........................................................................................ 165
6.5.4 Functional Description .............................................................................. 165
6.5.5 Register Map ......................................................................................... 171
6.5.6 Register Description................................................................................. 172
6.6 General Purpose I/O (GPIO) .................................................................176
6.6.1 Overview .............................................................................................. 176
6.6.2 Features............................................................................................... 176
6.6.3 Basic Configuration.................................................................................. 177
6.6.4 Functional Description .............................................................................. 177
6.6.5 Register Map ......................................................................................... 180
6.6.6 Register Description................................................................................. 183
6.7 PDMA Controller (PDMA)..................................................................... 195
6.7.1 Overview .............................................................................................. 195
6.7.2 Features............................................................................................... 195
6.7.3 Block Diagram........................................................................................ 196
6.7.4 Basic Configuration.................................................................................. 197
6.7.5 Functional Description .............................................................................. 197
6.7.6 Register Map ......................................................................................... 200
6.7.7 Register Description................................................................................. 202
6.8 Timer Controller (TIMER) .....................................................................233
6.8.1 Overview .............................................................................................. 233
6.8.2 Features............................................................................................... 233
6.8.3 Block Diagram........................................................................................ 234

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6.8.4 Basic Configuration.................................................................................. 236
6.8.5 Functional Description .............................................................................. 236
6.8.6 Register Map ......................................................................................... 239
6.8.7 Register Description................................................................................. 241
6.9 PWM Generator and Capture Timer (PWM)............................................... 250
6.9.1 Overview .............................................................................................. 250
6.9.2 Features............................................................................................... 251
6.9.3 Block Diagram........................................................................................ 252
6.9.4 Basic Configuration.................................................................................. 255
6.9.5 Functional Description .............................................................................. 255
6.9.6 Register Map ......................................................................................... 265
6.9.7 Register Description................................................................................. 267
6.10Watchdog Timer (WDT).......................................................................295
6.10.1Overview .............................................................................................. 295
6.10.2Features............................................................................................... 295
6.10.3Block Diagram........................................................................................ 296
6.10.4Basic Configuration.................................................................................. 297
6.10.5Functional Description .............................................................................. 297
6.10.6Register Map ......................................................................................... 299
6.10.7Register Description................................................................................. 300
6.11Window Watchdog Timer (WWDT).......................................................... 303
6.11.1Overview .............................................................................................. 303
6.11.2Features............................................................................................... 303
6.11.3Block Diagram........................................................................................ 303
6.11.4Basic Configuration.................................................................................. 304
6.11.5Functional Description .............................................................................. 304
6.11.6Register Map ......................................................................................... 307
6.11.7Register Description................................................................................. 308
6.12Real Time Clock (RTC)........................................................................313
6.12.1Overview .............................................................................................. 313
6.12.2Features............................................................................................... 313
6.12.3Block Diagram........................................................................................ 314
6.12.4Basic Configuration.................................................................................. 314
6.12.5Functional Description .............................................................................. 314
6.12.6Register Map ......................................................................................... 318

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6.12.7Register Description................................................................................. 320
6.13UART Interface Controller (UART) ..........................................................336
6.13.1Overview .............................................................................................. 336
6.13.2Features............................................................................................... 336
6.13.3Block Diagram........................................................................................ 337
6.13.4Basic Configuration.................................................................................. 338
6.13.5Functional Description .............................................................................. 339
6.13.6Register Map ......................................................................................... 360
6.13.7Register Description................................................................................. 362
6.14I2C Serial Interface Controller (I2C).......................................................... 389
6.14.1Overview .............................................................................................. 389
6.14.2Features............................................................................................... 389
6.14.3Basic Configuration.................................................................................. 390
6.14.4Block Diagram........................................................................................ 390
6.14.5Functional Description .............................................................................. 390
6.14.6Example for Random Read on EEPROM ....................................................... 403
6.14.7Register Map ......................................................................................... 405
6.14.8Register Description................................................................................. 406
6.15Serial Peripheral Interface (SPI) .............................................................416
6.15.1Overview .............................................................................................. 416
6.15.2Features............................................................................................... 416
6.15.3Block Diagram........................................................................................ 417
6.15.4Basic Configuration.................................................................................. 417
6.15.5Functional Description .............................................................................. 417
6.15.6Timing Diagram ...................................................................................... 425
6.15.7Programming Examples............................................................................ 428
6.15.8Register Map ......................................................................................... 430
6.15.9Register Description................................................................................. 431
6.16USB Device Controller (USBD) ..............................................................447
6.16.1Overview .............................................................................................. 447
6.16.2Features............................................................................................... 447
6.16.3Block Diagram........................................................................................ 448
6.16.4Basic Configuration.................................................................................. 448
6.16.5Functional Description .............................................................................. 448
6.16.6Register Map ......................................................................................... 453

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6.16.7Register Description................................................................................. 455
6.17Analog-to-Digital Converter (ADC) .......................................................... 472
6.17.1Overview .............................................................................................. 472
6.17.2Features............................................................................................... 472
6.17.3Block Diagram........................................................................................ 473
6.17.4Basic Configuration.................................................................................. 473
6.17.5Functional Description .............................................................................. 474
6.17.6Register Map ......................................................................................... 481
6.17.7Register Description................................................................................. 482
7ELECTRICAL CHARACTERISTICS..................................................................494
8PACKAGE DIMENSIONS..................................................................................495
8.1 64-pin LQFP (7x7x1.4 mm footprint 2.0 mm)..............................................495
8.2 48-pin LQFP (7x7x1.4 mm footprint 2.0 mm)..............................................496
9REVISION HISTORY..........................................................................................497

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LIST OF FIGURES
Figure 4.1-1 NuMicro®NUC029 Series Selection Code................................................................ 18
Figure 4.3-1 NuMicro®NUC029SEE LQFP 64-pin Diagram ......................................................... 20
Figure 4.3-2 NuMicro®NUC029LEE LQFP 48-pin Diagram.......................................................... 21
Figure 5.1-1 NuMicro®NUC029LEE/NUC029SEE Block Diagram ............................................... 27
Figure 6.1-1 Functional Controller Diagram................................................................................... 28
Figure 6.2-1 NuMicro®NUC029LEE/NUC029SEE Power Distribution Diagram........................... 31
Figure 6.3-1 Clock Generator Block Diagram.............................................................................. 114
Figure 6.3-2 Clock Generator Global View Diagram.................................................................... 115
Figure 6.3-3 System Clock Block Diagram .................................................................................. 116
Figure 6.3-4 SysTick Clock Control Block Diagram..................................................................... 116
Figure 6.3-5 Clock Source of Frequency Divider......................................................................... 117
Figure 6.3-6 Frequency Divider Block Diagram........................................................................... 118
Figure 6.4-1 Flash Memory Control Block Diagram..................................................................... 143
Figure 6.4-2 Flash Memory Organization .................................................................................... 145
Figure 6.4-3 Program Executing Range for Booting from APROM and LDROM ........................ 149
Figure 6.4-4 Executable Range of Code with IAP Function Enabled.......................................... 150
Figure 6.4-5 Example Flow of Boot Selection by BS Bit.............................................................. 151
Figure 6.4-6 ISP Flow Example ................................................................................................... 152
Figure 6.5-1 EBI Block Diagram.................................................................................................. 165
Figure 6.5-2 Connection of 16-bit EBI Data Width with 16-bit Device........................................ 166
Figure 6.5-3 Connection of 8-bit EBI Data Width with 8-bit Device............................................. 166
Figure 6.5-4 Timing Control Waveform for 16-bit Data Width...................................................... 168
Figure 6.5-5 Timing Control Waveform for 8-bit Data Width....................................................... 169
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle........................................................ 170
Figure 6.6-1 Push-Pull Output...................................................................................................... 177
Figure 6.6-2 Open-Drain Output .................................................................................................. 178
Figure 6.6-3 Quasi-bidirectional I/O Mode................................................................................... 178
Figure 6.7-1 DMA Controller Block Diagram................................................................................ 196
Figure 6.7-2 CRC Generator Block Diagram ............................................................................... 197
Figure 6.8-1 Timer Controller Block Diagram .............................................................................. 234
Figure 6.8-2 Clock Source of Timer Controller ............................................................................ 235
Figure 6.8-3 Continuous Counting Mode..................................................................................... 237
Figure 6.9-1 PWM Generator 0 Clock Source Control................................................................. 252
Figure 6.9-2 PWM Generator 0 Architecture Diagram................................................................. 252
Figure 6.9-3 PWM Generator 2 Clock Source Control................................................................. 253
Figure 6.9-4 PWM Generator 2 Architecture Diagram................................................................. 253

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Figure 6.9-5 PWM Generator 4 Clock Source Control................................................................. 254
Figure 6.9-6 PWM Generator 4 Architecture Diagram................................................................. 254
Figure 6.9-7 Legend of Internal Comparator Output of PWM-Timer ........................................... 255
Figure 6.9-8 PWM-Timer Operation Timing................................................................................. 256
Figure 6.9-9 PWM Edge-aligned Interrupt Generate Timing Waveform...................................... 256
Figure 6.9-10 Center-aligned Type Output Waveform................................................................. 257
Figure 6.9-11 PWM Center-aligned Interrupt Generate Timing Waveform ................................. 258
Figure 6.9-12 PWM Double Buffering Illustration......................................................................... 259
Figure 6.9-13 PWM Controller Output Duty Ratio........................................................................ 259
Figure 6.9-14 Paired-PWM Output with Dead-zone Generation Operation ................................ 260
Figure 6.9-15 PWM trigger ADC to conversion in Center-aligned type Timing Waveform.......... 260
Figure 6.9-16 Capture Operation Timing ..................................................................................... 261
Figure 6.9-17 PWM Group A PWM-Timer Interrupt Architecture Diagram.................................. 262
Figure 6.9-18 PWM Group B PWM-Timer Interrupt Architecture Diagram.................................. 262
Figure 6.10-1 Watchdog Timer Clock Control.............................................................................. 296
Figure 6.10-2 Watchdog Timer Block Diagram............................................................................ 296
Figure 6.10-3 Watchdog Timer Time-out Interval and Reset Period Timing ............................... 298
Figure 6.11-1 Window Watchdog Timer Clock Control................................................................ 303
Figure 6.11-2 Window Watchdog Timer Block Diagram.............................................................. 304
Figure 6.11-3 Window Watchdog Timer Reset and Reload Behavior......................................... 305
Figure 6.12-1 RTC Block Diagram............................................................................................... 314
Figure 6.13-1 UART Clock Control Diagram................................................................................ 337
Figure 6.13-2 UART Block Diagram ............................................................................................ 338
Figure 6.13-3 Transmit Delay Time Operation............................................................................. 341
Figure 6.13-4 Auto Flow Control Block Diagram.......................................................................... 345
Figure 6.13-5 UART CTS Auto Flow Control Enabled................................................................. 345
Figure 6.13-6 UART RTS Auto Flow Control Enabled................................................................. 346
Figure 6.13-7 UART RTS Flow with Software Control................................................................ 346
Figure 6.13-8 IrDA Control Block Diagram .................................................................................. 347
Figure 6.13-9 IrDA TX/RX Timing Diagram ................................................................................. 348
Figure 6.13-10 Structure of LIN Frame........................................................................................ 348
Figure 6.13-11 Structure of LIN Byte ........................................................................................... 349
Figure 6.13-12 Break Detection in LIN Mode............................................................................... 351
Figure 6.13-13 LIN Frame ID and Parity Format ......................................................................... 352
Figure 6.13-14 LIN Sync Field Measurement.............................................................................. 354
Figure 6.13-15 UA_BAUD Update Sequence in Automatic Resynchronization Mode when
LINS_DUM_EN (UA_LIN_CTL[3]) = 1.................................................................................. 355

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Figure 6.13-16 UA_BAUD Update Sequence in Automatic Resynchronization Mode when
LINS_DUM_EN (UA_LIN_CTL[3])= 0................................................................................... 355
Figure 6.13-17 RS-485 RTS Driving Level in Auto Direction Mode............................................. 358
Figure 6.13-18 RS-485 RTS Driving Level with Software Control.............................................. 358
Figure 6.13-19 Structure of RS-485 Frame ................................................................................. 359
Figure 6.14-1 I2C Controller Block Diagram................................................................................. 390
Figure 6.14-2 I2C Bus Timing....................................................................................................... 391
Figure 6.14-3 I2C Protocol........................................................................................................... 391
Figure 6.14-4 START and STOP Conditions............................................................................... 392
Figure 6.14-5 Bit Transfer on the I2C Bus.................................................................................... 393
Figure 6.14-6 Acknowledge on the I2C Bus................................................................................. 393
Figure 6.14-7 Master Transmits Data to Slave............................................................................ 393
Figure 6.14-8 Master Reads Data from Slave ............................................................................. 394
Figure 6.14-9 Control I2C Bus according to Current I2C Status................................................... 394
Figure 6.14-10 Master Transmitter Mode Control Flow............................................................... 395
Figure 6.14-11 Master Receiver Mode Control Flow................................................................... 396
Figure 6.14-12 Save Mode Control Flow..................................................................................... 397
Figure 6.14-13 GC Mode ............................................................................................................. 398
Figure 6.14-14 Arbitration Lost..................................................................................................... 399
Figure 6.14-15 I2C Data Shifting Direction................................................................................... 400
Figure 6.14-16 I2C Time-out Count Block Diagram ..................................................................... 402
Figure 6.14-17 EEPROM Random Read..................................................................................... 403
Figure 6.14-18 Protocol of EEPROM Random Read .................................................................. 404
Figure 6.15-1 SPI Block Diagram................................................................................................. 417
Figure 6.15-2 SPI Master Mode Application Block Diagram........................................................ 418
Figure 6.15-3 SPI Slave Mode Application Block Diagram.......................................................... 418
Figure 6.15-4 32-Bit in One Transaction...................................................................................... 419
Figure 6.15-5 Variable Bus Clock Frequency.............................................................................. 421
Figure 6.15-6 Byte Reorder Function........................................................................................... 421
Figure 6.15-7 Timing Waveform for Byte Suspend...................................................................... 422
Figure 6.15-8 Bit Sequence of Dual Output Mode....................................................................... 423
Figure 6.15-9 Bit Sequence of Dual Input Mode.......................................................................... 423
Figure 6.15-10 FIFO Mode Block Diagram.................................................................................. 424
Figure 6.15-11 SPI Timing in Master Mode ................................................................................. 426
Figure 6.15-12 SPI Timing in Master Mode (Alternate Phase of SPI Bus Clock)........................ 426
Figure 6.15-13 SPI Timing in Slave Mode ................................................................................... 427
Figure 6.15-14 SPI Timing in Slave Mode (Alternate Phase of SPI Bus Clock).......................... 427

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Figure 6.16-1 USB Device Block Diagram................................................................................... 448
Figure 6.16-2 Wake-up Interrupt Operation Flow ....................................................................... 450
Figure 6.16-3 Endpoint SRAM Structure ..................................................................................... 451
Figure 6.16-4 Setup Transaction Followed by Data IN Transaction............................................ 452
Figure 6.16-5 Data Out Transfer.................................................................................................. 452
Figure 6.17-1 ADC Controller Block Diagram.............................................................................. 473
Figure 6.17-2 ADC Clock Control................................................................................................. 474
Figure 6.17-3 Single Mode Conversion Timing Diagram............................................................. 475
Figure 6.17-4 Single-Cycle Scan on Enabled Channels Timing Diagram................................... 476
Figure 6.17-5 Continuous Scan on Enabled Channels Timing Diagram..................................... 477
Figure 6.17-6 VBG for Measuring AVDD Application Block Diagram ............................................. 478
Figure 6.17-7 A/D Conversion Result Monitor Logics Diagram................................................... 479
Figure 6.17-8 A/D Controller Interrupt.......................................................................................... 480
Figure 6.17-9 ADC Single-end Input Conversion Voltage and Conversion Result Mapping....... 483
Figure 6.17-10 ADC Differential Input Conversion Voltage and Conversion Result Mapping..... 484

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LIST OF TABLES
Table 4.1-1 List of Abbreviations.................................................................................................... 17
Table 6.2-1 Address Space Assignments for On-Chip Controllers................................................ 33
Table 6.2-2 Exception Model ......................................................................................................... 80
Table 6.2-3 System Interrupt Map ................................................................................................. 81
Table 6.2-4 Vector Table Format................................................................................................... 81
Table 6.3-1 Chip Idle/Power-down Mode Control Table.............................................................. 123
Table 6.4-1 Memory Address Map............................................................................................... 144
Table 6.4-2 ISP Command List.................................................................................................... 153
Table 6.10-1 Watchdog Timer Time-out Interval Period Selection.............................................. 298
Table 6.11-1 Window Watchdog Timer Prescale Value Selection .............................................. 304
Table 6.11-2 WINCMP Setting Limitation .................................................................................... 306
Table 6.13-1 UART Interface Controller Pin................................................................................ 339
Table 6.13-2 UART Baud Rate Equation..................................................................................... 339
Table 6.13-3 UART Controller Baud Rate Parameter Setting Table........................................... 340
Table 6.13-4 UART Controller Baud Rate Register (UA_BAUD) Setting Table.......................... 341
Table 6.13-5 UART Controller Interrupt Source and Flag List..................................................... 343
Table 6.13-6 Controller Interrupt Source and Flag in DMA Mode List......................................... 343
Table 6.13-7 UART Line Control of Word and Stop Length Setting............................................ 344
Table 6.13-8 UART Line Control of Parity Bit Setting.................................................................. 344
Table 6.13-9 LIN Header Selection in Master Mode.................................................................... 349
Table 6.14-1 I2C Status Code Description................................................................................... 402

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1 GENERAL DESCRIPTION
The NuMicro®NUC029LEE/NUC029SEE of NUC029 series is embedded with the ARM®Cortex®-
M0 core running up to 72 MHz and features 128 Kbytes flash, 16K bytes SRAM, and 8 Kbytes
loader ROM for the ISP. It is also equipped with plenty of peripheral devices, such as Timers,
Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI,
I2C, PWM Timer, GPIO, LIN, CAN, USB 2.0 FS Device, 12-bit ADC, Low Voltage Reset Controller
and Brown-out Detector.

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2 FEATURES
ARM®Cortex®-M0 core
–Runs up to 72 MHz
–One 24-bit system timer
–Supports low power sleep mode
–Single-cycle 32-bit hardware multiplier
–NVIC for the 32 interrupt inputs, each with 4-levels of priority
–Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V
Flash Memory
–128K bytes Flash for program code
–8 KB flash for ISP loader
–Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
–512 byte page erase for flash
–Configurable Data Flash address and size for 128 KB system
–Supports 2-wired ICP update through SWD/ICE interface
SRAM Memory
–16K bytes embedded SRAM
–Supports PDMA mode
PDMA (Peripheral DMA)
–Supports 9 channels PDMA for automatic data transfer between SRAM and peripherals
–Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC-16 and
CRC-32
Clock Control
–Flexible selection for different applications
–Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to ±1 % at +25 ℃and VDD = 5 V
Trimmed to ±3 % at -40 ℃~ +105 ℃and VDD = 2.5 V ~ 5.5 V
–Built-in 48 MHz internal high speed RC oscillator (HIRC) for USB device operation
(Frequency variation < 2% at -40oC ~ +105oC)
Dynamically calibrating the HIRC OSC to 48 MHz ±0.25% from -40℃to 105℃by
external 32.768K crystal oscillator (LXT) or internal USB synchronous mode
–Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
–Supports one PLL, up to 72 MHz, for high performance system operation
–External 4~24 MHz high speed crystal input for USB and precise timing operation
–External 32.768 kHz low speed crystal input for RTC function and low power system
operation
GPIO
–Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
–TTL/Schmitt trigger input selectable
–I/O pin configured as interrupt source with edge/level setting
Timer
–Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
–Independent clock source for each timer
–Provides one-shot, periodic, toggle and continuous counting operation modes
–Supports event counting function
–Supports input capture function
Watchdog Timer
–Multiple clock sources

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–8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
–Wake-up from Power-down or Idle mode
–Interrupt or reset selectable on watchdog time-out
–Supports 4 selectable Watchdog Timer reset delay period(1026, 130, 18 or 3 WDT_CLK)
Window Watchdog Timer
–6-bit down counter with 11-bit prescale for wide range window selected
RTC
–Supports software compensation by setting frequency compensate register (FCR)
–Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
–Supports Alarm registers (second, minute, hour, day, month, year)
–Selectable 12-hour or 24-hour mode
–Automatic leap year recognition
–Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4,
1/2 and 1 second
–Supports battery power pin (VBAT)
–Supports wake-up function
PWM/Capture
–Up to three built-in 16-bit PWM generators providing six PWM outputs or three
complementary paired PWM outputs
–Each PWM generator equipped with one clock source selector, one clock divider, one 8-bit
prescaler and one Dead-Zone generator for complementary paired PWM
–Supports One-shot or Auto-reload mode
–Up to six 16-bit digital capture timers (shared with PWM timers) providing six rising/falling
capture inputs
–Supports Capture interrupt
UART
–Up to three UART controllers
–UART ports with flow control (TXD, RXD, nCTS and nRTS)
–UART0 with 64-byte FIFO is for high speed
–UART1/2(optional) with 16-byte FIFO for standard device
–Supports IrDA (SIR) and LIN function
–Supports RS-485 9-bit mode and direction control
–Programmable baud-rate generator up to 1/16 system clock
–Supports CTS wake-up function (UART0 and UART1 support)
–Supports PDMA mode
SPI
–Up to two sets of SPI controllers
–The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
–The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
–Supports SPI Master/Slave mode
–Full duplex synchronous serial data transfer
–Variable length of transfer data from 8 to 32 bits
–MSB or LSB first data transfer
–Rx and Tx on both rising or falling edge of serial clock independently
–Two slave/device select lines in Master mode, and one slave/device select line in Slave
mode
–Supports Byte Suspend mode in 32-bit transmission
–Supports PDMA mode
–Supports three wire, no slave select signal, bi-direction interface
I2C
–Up to two sets of I2C devices
–Master/Slave mode
–Bidirectional data transfer between masters and slaves
–Multi-master bus (no central master)
–Arbitration between simultaneously transmitting masters without corruption of serial data on

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32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
the bus
–Serial clock synchronization allowing devices with different bit rates to communicate via one
serial bus
–Serial clock synchronization used as a handshake mechanism to suspend and resume serial
transfer
–Programmable clocks allowing for versatile rate control
–Supports multiple address recognition (four slave address with mask option)
–Supports wake-up function
USB 2.0 Full-Speed Device
–One set of USB 2.0 FS Device 12 Mbps
–On-chip USB Transceiver
–Provides 1 interrupt source with 4 interrupt events
–Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
–Auto suspend function when no bus signaling for 3 ms
–Provides 8 programmable endpoints
–Includes 512 Bytes internal SRAM as USB buffer
–Provides remote wake-up capability
–Supports Crystal-less function
ADC
–12-bit SAR ADC with 1 MSPS(chip working at 5V)
–Up to 12-ch single-end input or 5-ch differential input
–Single scan/single cycle scan/continuous scan
–Each channel with individual result register
–Scan on enabled channels
–Threshold voltage detection
–Conversion started by software programming, external input or PWM Center-aligned trigger
–Supports PDMA mode
EBI (External bus interface)
–Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
–Supports 8-/16-bit data width
–Supports byte write in 16-bit data width mode
96-bit unique ID (UID)
128-bit unique customer ID(UCID)
One built-in temperature sensor with 1℃resolution
Brown-out Detector
–With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
–Supports Brown-out Interrupt and Reset option
Low Voltage Reset
–Threshold voltage level: 2.0 V
Operating Temperature: -40℃~ 105℃
Packages:
–All Green package (RoHS)
–LQFP 64-pin / 48-pin

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32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
3 ABBREVIATIONS
Acronym
Description
ACMP
Analog Comparator Controller
ADC
Analog-to-Digital Converter
AES
Advanced Encryption Standard
APB
Advanced Peripheral Bus
AHB
Advanced High-Performance Bus
BOD
Brown-out Detection
CAN
Controller Area Network
DAP
Debug Access Port
DES
Data Encryption Standard
EBI
External Bus Interface
EPWM
Enhanced Pulse Width Modulation
FIFO
First In, First Out
FMC
Flash Memory Controller
FPU
Floating-point Unit
GPIO
General-Purpose Input/Output
HCLK
The Clock of Advanced High-Performance Bus
HIRC
22.1184 MHz Internal High Speed RC Oscillator
HXT
4~24 MHz External High Speed Crystal Oscillator
IAP
In Application Programming
ICP
In Circuit Programming
ISP
In System Programming
LDO
Low Dropout Regulator
LIN
Local Interconnect Network
LIRC
10 kHz internal low speed RC oscillator (LIRC)
MPU
Memory Protection Unit
NVIC
Nested Vectored Interrupt Controller
PCLK
The Clock of Advanced Peripheral Bus
PDMA
Peripheral Direct Memory Access
PLL
Phase-Locked Loop
PWM
Pulse Width Modulation
QEI
Quadrature Encoder Interface
SDIO
Secure Digital Input/Output

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32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
SPI
Serial Peripheral Interface
SPS
Samples per Second
TDES
Triple Data Encryption Standard
TMR
Timer Controller
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
USB
Universal Serial Bus
WDT
Watchdog Timer
WWDT
Window Watchdog Timer
Table 4.1-1 List of Abbreviations

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32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
4 PARTS INFORMATION LIST AND PIN CONFIGURATION
4.1 NuMicro®NUC029 Series Selection Code
CPU core
ARM Cortex M0
Package Type
F: TSSOP 20
T: QFN33 (5x5)
Z: QFN33 (4x4)
N: QFN48 (7x7)
L: LQFP 48 (7x7)
S: LQFP 64 (7x7)
Temperature
Flash Size
A: Less than 68K
D: 68K
E: 128K
G: 256K
NUC029 -XXX
E: - 40 ℃~ +105℃
N: - 40 ℃~ +85℃
Figure 4.1-1 NuMicro®NUC029 Series Selection Code

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32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
4.2 NuMicro®NUC029 Series Selection Guide
Part Number
APROM (KB)
RAM (KB)
Data Flash (KB)
SPROM(KB)
ISP ROM (KB)
I/O
Timer (32-Bit)
Connectivity
I2S
PWM (16-Bit)
ADC
ACMP
PDMA
RTC
EBI
PLL
ISP/ICP/IAP
Package
Operating
Temperature
Range (℃)
UART
SPI
I2C
USCI[4]
USB
LIN
NUC029FAE
16
2
Conf
-
2
17
2
1
1
1
-
-
-
-
3
4[1]
2[3]
-
-
-
-
√
TSSOP20
-40 to +105
NUC029TAN
32
4
4
-
4
24
4
2
1
2
-
-
-
-
5
5
3[2]
-
-
-
√
√
QFN33(4*4)
-40 to +85
NUC029ZAN
64
4
4
-
4
24
4
2
1
2
-
-
-
-
5
5
3[2]
-
-
-
√
√
QFN33(5*5)
-40 to +85
NUC029LAN
64
4
4
-
4
40
4
2
2
2
-
-
-
-
8
8
4
-
-
√
√
√
LQFP48
-40 to +85
NUC029LDE
68
8
Conf
-
4
42
4
4
1
2
-
-
3
-
12
8
-
-
-
-
√
√
LQFP48
-40 to +105
NUC029SDE
68
8
Conf
-
4
56
4
4
1
2
-
-
3
-
12
8
-
-
-
-
√
√
LQFP64
-40 to +105
NUC029LEE
128
16
Conf
-
8
31
4
2
1
2
-
1
2
-
6
10
-
9
√
-
√
√
LQFP48
-40 to +105
NUC029SEE
128
16
Conf
-
8
45
4
3
2
2
-
1
3
-
6
12
-
9
√
√
√
√
LQFP64
-40 to +105
NUC029LGE
256
20
Conf
2
4
35
4
3
2
2
3
1
-
2
10
9
2
5
√
√
√
√
LQFP48
-40 to +105
NUC029SGE
256
20
Conf
2
4
49
4
3
2
2
3
1
-
2
12
15
2
5
√
√
√
√
LQFP64
-40 to +105
[1] NUC029FAE is 10-bit ADC. All the others are 12-bit ADC.
[2] For NUC029TAN/NUC029ZAN, ACMP3 only has positive and negative input.
[3] For NUC029FAE , ACMP0 only has positive and negative input. And ACMP1 only has positive input.
[4] USCI 能够被配置为 UART, SPI 或I2C

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32-bit Arm®Cortex®-M0 Microcontroller
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NUMICRO®NUC029LEE/NUC029SEE TECHNICAL REFERENCE MANUAL
4.3 Pin Configuration
4.3.1 NuMicro®NUC029LEE/NUC029SEE Pin Diagram
4.3.1.1 NuMicro®NUC029SEE LQFP 64 pin (7 mm * 7mm)
AD8/ADC5/PA.5
AD7/ADC6/PA.6
VREF
AD0/INT0/PB.14
AD1/PB.13
VBAT
X32_IN
X32_OUT
nRD/I2C1_SCL/PA.11
nWR/I2C1_SDA/PA.10
I2C0_SCL/PA.9
I2C0_SDA/PA.8
UART1_RXD/PB.4
UART1_TXD/PB.5
ALE/UART1_nRTS/PB.6
nCS/UART1_nCTS/PB.7
LDO_CAP
VDD
VSS
AD5/ADC7/PC.7
AD4/ADC8/PC.6
AD3/ADC9/PC.15
AD2/ADC10/PC.14
AD6/ADC11/TM0/TM0_EXT/INT1/PB.15
XT1_OUT/PF.0
XT1_IN/PF.1
nRESET
CLKO/TM0/STADC/PB.8
PA.4/ADC4/AD9 PA.3/ADC3/AD10 PA.2/ADC2/AD11 PA.1/ADC1/AD12 PA.0/ADC0 AVSS ICE_CLK ICE_DAT PA.12/PWM0/AD13 PA.13/PWM1/AD14 PA.14/PWM2/AD15 PA.15/PWM3 PC.8/SPI1_SS0/MCLK PC.9/SPI1_CLK
AVDD
VSS
VDD
PVSS
PC.0/SPI0_SS0
PC.1/SPI0_CLK
PC.2/SPI0_MISO0
PC.3/SPI0_MOSI0
USB_D+
USB_D-
USB_VDD33_CAP
USB_VBUS17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
PC.10/SPI1_MISO0 PC.11/SPI1_MOSI0
PB.9/TM1/UART2_TXD
PB.10/TM2/UART2_RXD
PB.11/TM3/PWM4
PE.5/TM1_EXT/TM1/PWM5
PB.3/UART0_nCTS/TM3_EXT/TM3/nWRH
PB.2/UART0_nRTS/TM2_EXT/TM2/nWRL
PB.1/UART0_TXD
PB.0/UART0_RXD
NUC029SEE
LQFP 64-pin
Figure 4.3-1 NuMicro®NUC029SEE LQFP 64-pin Diagram