Nuvoton NuMicro MS51 32K Series Product manual

MS51
Nov. 28, 2019 Page 1of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
1T 8051
8-bit Microcontroller
NuMicro®Family
MS51 32K Series
MS51FC0AE
MS51XC0BE
MS51EC0AE
MS51TC0AE
MS51PC0AE
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
1GENERAL DESCRIPTION ............................................................................10
2FEATURES....................................................................................................11
3PARTS INFORMATION.................................................................................15
3.1 Package Type .............................................................................................................. 15
3.2 MS51 Series Selection Gude .................................................................................... 15
3.3 MS51 Series Selection Code..................................................................................... 16
4PIN CONFIGURATION ..................................................................................17
4.1 MS51 32K Series Multi Function Pin Diagram........................................................ 17
4.1.1 QFN 33-pin Package Pin Diagram .............................................................................17
4.1.2 LQFP 32-pin Package Pin Diagram ...........................................................................18
4.1.3 TSSOP 28-pin Package Pin Diagram ........................................................................19
4.1.4 TSSOP 20-pin Package Pin Diagram ........................................................................19
4.1.5 QFN 20-pin Package Pin Diagram .............................................................................20
4.2 MS51 32K Series Pin Description............................................................................. 21
5BLOCK DIAGRAM.........................................................................................25
5.1 MS51 32K Series Block Diagram.............................................................................. 25
6FUNCTIONAL DESCRIPTION.......................................................................26
6.1 Memory Organization.................................................................................................. 26
6.1.1 Overview..........................................................................................................................26
6.1.2 Program Memory............................................................................................................26
6.1.3 Data Flash Memory........................................................................................................28
6.1.4 Security Protection Memory (SPROM) .......................................................................28
6.1.5 CONFIG bytes ................................................................................................................28
6.1.6 Data Memory...................................................................................................................34
6.1.7 Special Function Register (SFR)..................................................................................37
6.2 System Manager........................................................................................................ 201
6.2.1 Clock System ................................................................................................................201
6.2.2 Power Management.....................................................................................................211
6.2.3 Power Monitoring..........................................................................................................213
6.2.4 Reset ..............................................................................................................................219
6.2.5 Timed Access Protection (TA) ....................................................................................227
6.2.6 Interrupt System ...........................................................................................................230
6.3 Flash Memory Control .............................................................................................. 249
6.3.1 In-Application-Programming (IAP) .............................................................................249
6.3.2 In-Circuit-Programming (ICP).....................................................................................265
6.3.3 On-Chip-Debugger (OCD) ..........................................................................................265
6.3.4 96-Bit Unique Code......................................................................................................267

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6.3.5 CONFIG Bytes..............................................................................................................267
6.4 General Purpose I/O (GPIO) ................................................................................... 272
6.4.1 Gpio Mode.....................................................................................................................272
6.4.2 Read-Modify-Write Instructions..................................................................................274
6.4.3 Pin Interrupt (PIT).........................................................................................................275
6.4.4 Control Registers of GPIO ..........................................................................................276
6.5 Timer............................................................................................................................ 287
6.5.1 Timer/Counter 0 And 1.................................................................................................287
6.5.2 Timer2 And Input Capture ...........................................................................................296
6.5.3 TIMER 3.........................................................................................................................314
6.6 pulse Width Modulated (PWM)................................................................................ 318
6.6.1 Overview........................................................................................................................318
6.6.2 Functional Description .................................................................................................319
6.6.3 PWM Interrupt...............................................................................................................327
6.6.4 Control Register of PWM.............................................................................................330
6.7 Watchdog Timer (WDT)............................................................................................ 352
6.7.1 Overview........................................................................................................................352
6.7.2 Time-Out Reset Timer..................................................................................................354
6.7.3 General Purpose Timer ...............................................................................................355
6.7.4 Control Registers of Watchdog Timer ......................................................................357
6.8 Self Wake-Up Timer (WKT)...................................................................................... 359
6.8.1 Overview........................................................................................................................359
6.8.2 Control register of WKT...............................................................................................360
6.9 Serial Port (UART0 & UART1) ................................................................................ 363
6.9.1 Overview........................................................................................................................363
6.9.2 Operating Modes..........................................................................................................363
6.9.3 Baud Rate......................................................................................................................365
6.9.4 Framing Error Detection ..............................................................................................369
6.9.5 Multiprocessor Communication..................................................................................369
6.9.6 Automatic Address Recognition .................................................................................370
6.9.7 Control Register of Serial Port....................................................................................372
6.10 ISO 7816-3 Interface (SC0~2 & UART2 ~ 4) .................................................. 387
6.10.1Overview........................................................................................................................387
6.10.2Operating Modes ..........................................................................................................388
6.10.3ISO 7816-3 Data Transfer ...........................................................................................391
6.10.4Initial Character TS.......................................................................................................391
6.10.5Error Signal and Character Repetition ......................................................................392
6.10.6Block Guard Time and Extra Guard Time .................................................................392
6.10.7Control Registers of SC Controller ............................................................................394
6.11 Inter-Integrated Circuit (I2C) ............................................................................... 408

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6.11.1 Overview........................................................................................................................408
6.11.2 Functional Description .................................................................................................408
6.11.3 Typical Structure of I2C Interrupt Service Routine...................................................418
6.11.4 I2C Time-Out..................................................................................................................421
6.11.5 I2C Interrupt ...................................................................................................................422
6.11.6 Control Registers of I2C...............................................................................................423
6.12 Serial Peripheral Interface (SPI)........................................................................ 429
6.12.1Overview........................................................................................................................429
6.12.2Operating Modes ..........................................................................................................431
6.12.3Clock Formats and Data Transfer ..............................................................................431
6.12.4Slave Select Pin Configuration...................................................................................434
6.12.5Mode Fault Detection...................................................................................................434
6.12.6Write Collision Error .....................................................................................................434
6.12.7Overrun Error ................................................................................................................434
6.12.8SPI Interrupt ..................................................................................................................435
6.12.9Control Register of SPI................................................................................................436
6.13 12-Bit Analog-To -Digital Converter (ADC) ....................................................... 441
6.13.1Overview........................................................................................................................441
6.13.2Functional Description .................................................................................................441
6.13.3Control Registers of ADC ............................................................................................447
6.14 Auxiliary Features................................................................................................ 465
6.14.1Dual DPTRs ..................................................................................................................465
7APPLICATION CIRCUIT..............................................................................469
7.1 Power Supply Scheme ............................................................................................. 469
7.2 Peripheral Application Scheme ............................................................................... 470
7.3 System Reset............................................................................................................. 471
7.3.1 Hardware Reset Sources ............................................................................................471
8ELECTRICAL CHARACTERISTICS............................................................478
9PACKAGE DIMENSIONS............................................................................479
9.1 QFN 33-pin (4.0 x 4.0 x 0.8 mm)............................................................................. 479
9.2 LQFP 32-pin (7.0 x 7.0 x 1.4 mm)........................................................................... 480
9.3 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) ....................................................................... 481
9.4 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) ...................................................................... 482
9.5 QFN 20-pin (3.0 x 3.0 x 0.5mm).............................................................................. 483
10ABBREVIATIONS........................................................................................484
10.1 Abbreviations List ................................................................................................ 484
11INSTRUCTION SET.....................................................................................485
11.1 Instruction Set And Addressing Modes ............................................................ 485

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11.2 Instruction Set ...................................................................................................... 486
12REVISION HISTORY ...................................................................................490

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LIST OF FIGURES
Figure 4.1-1 Pin Assignment of LQFP-32 Package....................................................................... 17
Figure 4.1-2 Pin Assignment of LQFP-32 Package....................................................................... 18
Figure 4.1-3 Pin Assignment of TSSOP28 Package ..................................................................... 19
Figure 4.1-4 Pin Assignment of TSSOP20 Package ..................................................................... 19
Figure 4.1-5 Pin Assignment of QFN20 Package.......................................................................... 20
Figure 5.1-1 Functional Block Diagram.......................................................................................... 25
Figure 6.1-1 MS51 Program Memory Map .................................................................................... 27
Figure 6.1-2 SPROM Memory Mapping And SPROM Security Mode........................................... 28
Figure 6.1-3. CONFIG0 Any Reset Reloading............................................................................... 29
Figure 6.1-4. CONFIG2 Power-On Reset Reloading..................................................................... 31
Figure 6.1-5 Data Memory Map..................................................................................................... 34
Figure 6.1-6 Internal 256 Bytes RAM Addressing.......................................................................... 35
Figure 6.2-1 Clock System Block Diagram .................................................................................. 201
Figure 6.2-2 Brown-out Detection Block Diagram........................................................................ 214
Figure 6.2-3 Boot Selecting Diagram........................................................................................... 224
Figure 6.3-1 CONFIG0 Any Reset Reloading.............................................................................. 268
Figure 6.3-2 CONFIG2 Power-On Reset Reloading.................................................................... 270
Figure 6.4-1 Quasi-Bidirectional Mode Structure......................................................................... 273
Figure 6.4-2 Push-Pull Mode Structure........................................................................................ 273
Figure 6.4-3 Input-Only Mode Structure ...................................................................................... 274
Figure 6.4-4 Open-Drain Mode Structure .................................................................................... 274
Figure 6.4-5 Pin Interface Block Diagram.................................................................................... 275
Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0.......................................................................... 288
Figure 6.5-2 Timer/Counters 0 and 1 in Mode 1.......................................................................... 288
Figure 6.5-3 Timer/Counters 0 and 1 in Mode 2.......................................................................... 288
Figure 6.5-4 Timer/Counter 0 in Mode 3...................................................................................... 289
Figure 6.5-5 Timer 2 Block Diagram............................................................................................ 297
Figure 6.5-6 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram 298
Figure 6.5-7 Timer 2 Compare Mode and Input Capture Module Functional Block Diagram...... 299
Figure 6.5-8 Timer 3 Block Diagram............................................................................................ 314
Figure 6.6-1 PWM0 Block Diagram.............................................................................................. 320
Figure 6.6-2 PWM1/2/3 Block Diagram........................................................................................ 321
Figure 6.6-3 PWM0 and Fault Brake Output Control Block Diagram .......................................... 322
Figure 6.6-4 PWM1/2/3 Control Block Diagram........................................................................... 323
Figure 6.6-5 PWM Edge-aligned Type Waveform....................................................................... 324
Figure 6.6-6 PWM Center-aligned Type Waveform..................................................................... 324

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Figure 6.6-7 PWM0 Complementary Mode with Dead-time Insertion ......................................... 325
Figure 6.6-8 Fault Brake Function Block Diagram....................................................................... 326
Figure 6.6-9 PWM Interrupt Type................................................................................................. 329
Figure 6.7-1 WDT as A Time-Out Reset Timer............................................................................ 355
Figure 6.7-2 Watchdog Timer Block Diagram.............................................................................. 355
Figure 6.8-1 Self Wake-Up Timer Block Diagram........................................................................ 359
Figure 6.9-1 Serial Port Mode 0 Timing Diagram ........................................................................ 363
Figure 6.9-2 Serial Port Mode 1 Timing Diagram ........................................................................ 364
Figure 6.9-3 Serial Port Mode 2 and 3 Timing Diagram.............................................................. 365
Figure 6.10-1 SC Controller Block Diagram................................................................................. 387
Figure 6.10-2 SC Data Character ............................................................................................... 391
Figure 6.10-3 Initial Character TS.............................................................................................. 392
Figure 6.10-4 SC Error Signal..................................................................................................... 392
Figure 6.10-5 Transmit Direction Block Guard Time Operation.................................................. 393
Figure 6.10-6 Receive Direction Block Guard Time Operation.................................................... 393
Figure 6.10-7 Extra Guard Time Operation ................................................................................. 393
Figure 6.11-1 I2C Bus Interconnection......................................................................................... 408
Figure 6.11-2 I2C Bus Protocol .................................................................................................... 409
Figure 6.11-3 START, Repeated START, and STOP Conditions ............................................... 409
Figure 6.11-4 Master Transmits Data to Slave by 7-bit ............................................................... 410
Figure 6.11-5 Master Reads Data from Slave by 7-bit................................................................. 410
Figure 6.11-6 Data Format of One I2C Transfer........................................................................... 410
Figure 6.11-7 Acknowledge Bit.................................................................................................... 411
Figure 6.11-8 Arbitration Procedure of Two Masters................................................................... 411
Figure 6.11-9 Control I2C Bus according to the Current I2C Status............................................. 412
Figure 6.11-10 Flow and Status of Master Transmitter Mode ..................................................... 413
Figure 6.11-11 Flow and Status of Master Receiver Mode ......................................................... 414
Figure 6.11-12 Flow and Status of Slave Receiver Mode............................................................ 416
Figure 6.11-13 Flow and Status of General Call Mode................................................................ 417
Figure 6.11-14 I2C Time-Out Counter.......................................................................................... 422
Figure 6.11-15 Hold Time extend enable..................................................................................... 424
Figure 6.12-1 SPI Block Diagram................................................................................................. 429
Figure 6.12-2 SPI Multi-Master, Multi-Slave Interconnection ...................................................... 430
Figure 6.12-3 SPI Single-Master, Single-Slave Interconnection.................................................. 430
Figure 6.12-4 SPI Clock Formats................................................................................................. 432
Figure 6.12-5 SPI Clock and Data Format with CPHA = 0.......................................................... 433
Figure 6.12-6 SPI Clock and Data Format with CPHA = 1.......................................................... 433

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Figure 6.12-7 SPI Overrun Waveform.......................................................................................... 435
Figure 6.12-8 SPI Interrupt Request............................................................................................ 435
Figure 6.13-1 12-bit ADC Block Diagram..................................................................................... 441
Figure 6.13-2 External Triggering ADC Circuit ........................................................................... 444
Figure 6.13-3 ADC Result Comparator....................................................................................... 444
Figure 6.13-4 ADC Continues mode with DMA .......................................................................... 445
Figure 7.1-1 NuMicro®MS51 Power supply circuit...................................................................... 469
Figure 7.2-1 NuMicro®MS51 Peripheral interface circuit ............................................................ 470
Figure 7.3-1 nRESET Reset Waveform....................................................................................... 472
Figure 7.3-2 Low Voltage Reset (LVR) Waveform....................................................................... 473
Figure 7.3-3 Power-on Reset (POR) Waveform.......................................................................... 476
Figure 7.3-4 Low Voltage Reset (LVR) Waveform....................................................................... 476
Figure 7.3-5 Brown-out Detector (BOD) Waveform..................................................................... 477
Figure 9.1-1 QFN-33 Package Dimension................................................................................... 479
Figure 9.2-1 LQFP-32 Package Dimension................................................................................. 480
Figure 9.3-1 TSSOP-28 Package Dimension.............................................................................. 481
Figure 9.4-1 TSSOP-20 Package Dimension.............................................................................. 482
Figure 9.5-1 QFN-20 Package Dimension................................................................................... 483

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List of Tables
Table 6.1-1 Special Function Register Memory Map..................................................................... 39
Table 6.1-2 SFR Definitions and Reset Values ............................................................................. 47
Table 6.1-3 Instructions That Affect Flag Settings....................................................................... 133
Table 6.2-1 BOF Reset Value...................................................................................................... 215
Table 6.2-2 Minimum Brown-out Detect Pulse Width.................................................................. 218
Table 6.2-3 Interrupt Vectors ....................................................................................................... 230
Table 6.2-4 Interrupt Priority Level Setting .................................................................................. 236
Table 6.2-5 Characteristics of Each Interrupt Source.................................................................. 238
Table 6.3-1 IAP Modes and Command Codes............................................................................ 250
Table 6.4-1 Configuration for Different I/O Modes....................................................................... 272
Table 6.6-1 PWM Pin Define And Enable Control Register......................................................... 319
Table 6.7-1 Watchdog Timer-out Interval Under Different Pre-scalars........................................ 352
Table 6.9-1 Serial Port UART0 Mode / baudrate Description...................................................... 367
Table 6.9-2 Serial Port UART1 Mode / baudrate Description...................................................... 367
Table 6.10-1 Smart Card or UART Pin Define And Enable Control Register.............................. 388
Table 6.12-1 Slave Select Pin Configurations ............................................................................. 438
Table 10.1-1 List of Abbreviations................................................................................................ 484
Table 10.1-1 Instruction set and addressing modes.................................................................... 485
Table 10.1-2 Instruction Set......................................................................................................... 489

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1 GENERAL DESCRIPTION
The MS51 is an embedded Flash type, 8-bit high performance 1T 8051-based microcontroller. The
instruction set is fully compatible with the standard 80C51 and performance enhanced.
The MS51 contains a up to 32 Kbytes of main Flash called APROM, in which the contents of User
Code resides. The MS51 Flash supports In-Application-Programming (IAP) function, which enables
on-chip firmware updates. IAP also makes it possible to configure any block of User Code array to be
used as non-volatile data storage, which is written by IAP and read by IAP or MOVC instruction. There
is an additional Flash called LDROM, in which the Boot Code normally resides for carrying out In-
System-Programming (ISP). The LDROM size is configurable with a maximum of 4 Kbytes. To
facilitate programming and verification, the Flash allows to be programmed and read electronically by
parallel Writer or In-Circuit-Programming (ICP). Once the code is confirmed, user can lock the code for
security.
The MS51 provides rich peripherals including 256 bytes of SRAM, 2 Kbytes of auxiliary RAM (XRAM),
Up to 29 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with three-channel
input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT), one 16-bit auto-
reload Timer3 for general purpose or baud rate generator, two UARTs with frame error detection and
automatic address recognition, three ISO 7816-3 interfaces, one SPI, one I2C, six basic PWM output
channels, six enhanced PWM output channels, eight-channel shared pin interrupt for all I/O, and one
12-bit ADC. The peripherals are equipped with 24 sources with 4-level-priority interrupts capability.
The MS51 is equipped with three clock sources and supports switching on-the-fly via software. The
three clock sources include external clock input, 10 kHz internal oscillator, and one 16 MHz internal
precise oscillator that is factory trimmed to ±1% at room temperature. The MS51 provides additional
power monitoring detection such as power-on reset and 4-level brown-out detection, which stabilizes
the power-on/off sequence for a high reliability system design.
The MS51 microcontroller operation consumes a very low power with two economic power modes to
reduce power consumption －Idle and Power-down mode, which are software selectable. Idle mode
turns off the CPU clock but allows continuing peripheral operation. Power-down mode stops the whole
system clock for minimum power consumption. The system clock of the MS51 can also be slowed
down by software clock divider, which allows for a flexibility between execution performance and
power consumption.
With high performance CPU core and rich well-designed peripherals, the MS51 benefits to meet a
general purpose, home appliances, or motor control system accomplishment.

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2 FEATURES
Core and System
8051
Fully static design 8-bit high performance 1T 8051-based
CMOS microcontroller.
Instruction set fully compatible with MCS-51.
4-priority-level interrupts capability.
Dual Data Pointers (DPTRs).
Brown-out Detector (BOD)
4-level selection, with brown-out interrupt and reset option.
(4.4V / 3.7V / 2.7V / 2.2V)
Low Voltage Reset (LVR)
LVR with 2.0V threshold voltage level
Security
96-bit Unique ID (UID)
128-bit Unique Customer ID (UCID)
128-bytes security protection memory SPROM
Memories
Flash
Up to 32 KBytes of APROM for User Code.
4/3/2/1 Kbytes of Flash for loader (LDROM) configure from
APROM for In-System-Programmable (ISP)
Flash Memory accumulated with pages of 128 Bytes from
APROM by In-Application-Programmable (IAP) means whole
APROM can be use as Data Flash
An additional 128 bytes security protection memory SPROM
Code lock for security by CONFIG
SRAM
256 Bytes on-chip RAM.
Additional 2 KBytes on-chip auxiliary RAM (XRAM) accessed
by MOVX instruction.
Clocks
External Clock Source
4~24 MHz High-speed external crystal oscillator (HXT) for
precise timing operation
Internal Clock Source
Default 16 MHz high-speed internal oscillator (HIRC) trimmed
to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C.
Selectable 24 MHz high-speed internal oscillator (HIRC).
10 kHz low-speed internal oscillator (LIRC) calibrating to ±1%

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by software from high-speed internal oscillator
Timers
16-bit Timer
Two 16-bit Timers/Counters 0 and 1 compatible with standard
8051.
One 16-bit Timer2 with three-channel input capture module
and 9 input pin can be selected.
One 16-bit auto-reload Timer3, which can be the baud rate
clock source of UART0 and UART1.
Watchdog
6-bit free running up counter for WDT time-out interval.
Selectable time-out interval is 6.40 ms ~ 1.638s since
WDT_CLK = 10 kHz (LIRC).
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
Wake-up Timer
16-bit free running up counter for time-out interval.
Clock sources from LIRC
Able self Wake-up wake up from Power-down or Idle mode,
and auto reload count value.
Supports Interrupt
PWM
Up To 12 output pins can be selected
Supports maximum clock source frequency up to 24 MHz
Supports up to Three PWM modules, each module provides 6
output channels.
Supports independent mode for PWM output
Supports complementary mode for 3 complementary paired
PWM output channels
Dead-time insertion with 8-bit resolution
Supports 16-bit resolution PWM counter
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Supports trigger ADC on the following events
Analog Interfaces
Analog-to-Digital
Converter (ADC)
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 8 single-end analog input channels
1 internal channels, they are band-gap voltage (VBG).
Maximum ADC peripheral clock frequency is 1 MHz.
Up to 500 KSPS sampling rate.

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Software Write 1 to ADCS bit.
External pin (STADC) trigger
PWM trigger.
Support continues convert function auto store the A/D
conversion result in XRAM.
Communication Interfaces
UART
Supports up to 2 UARTs: UART0, UART1,
Three sets ISO 7816-3 device configuration as UART
UART baud rate clock from HIRC or HXT.
Full-duplex asynchronous communications
Programmable 9th bit.
TXD and RXD pins of UART0 exchangeable via software.
I2C
1 sets of I2C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I2C interrupt if
the I2C bus hangs up and timer-out counter overflows
Multiple address recognition (four slave addresses with mask
option)
Supports hold time programmable
SPI
1 sets of SPI devices
Supports Master or Slave mode operation
Supports MSB first or LSB first transfer sequence
slave mode up to 12 MHz
ISO-7816
Three sets ISO 7816-3 device
Supports ISO 7816-3 compliant T=0, T=1
Supports full-duplex UART mode.
GPIO
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
Schmitt trigger input / TTL mode selectable.
Each I/O pin configured as interrupt source with edge/level

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trigger setting
Standard interrupt pins INT0







and INT1







.
Supports high drive and high sink current I/O
I/O pin internal pull-up or pull-down resistor enabled in input
mode.
Maximum I/O Speed is 24 MHz
Enabling the pin interrupt function will also enable the wake-up
function
ESD & EFT
ESD
HBM pass 8 kV
EFT
> ± 4.4 kV
Latch-up
150 mA pass

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3 PARTS INFORMATION
3.1 Package Type
MSOP10
TSSOP14
TSSOP20
QFN20
TSSOP28
LQFP32
QFN33
Part
No.
MS51BA9AE
MS51DA9AE
MS51FB9AE
MS51FC0AE
MS51XB9AE
MS51XB9BE
MS51XC0BE
MS51EC0AE
MS51PC0AE
MS51TC0AE
3.2 MS51 Series Selection Gude
Part Number
Flash (KB)
SRAM (KB)
LDROM (KB) [1]
I/O
Timer/
PWM
Connectivity
ADC(12-Bit)
Package
ISO-7816 [2]
UART
SPI
I2C
MS51BA9AE
8
1
4
8
4
5
-
2
-
1
5-ch
MSOP10
MS51DA9AE
8
1
4
12
4
5
-
2
1
1
7-ch
TSSOP14
MS51XB9AE
16
1
4
18
4
6
-
2
1
1
8-ch
QFN20[3]
MS51XB9BE
16
1
4
18
4
6
-
2
1
1
8-ch
QFN20[3]
MS51FB9AE
16
1
4
18
4
6
-
2
1
1
8-ch
TSSOP20
MS51FC0AE
32
2
4
18
4
8
3
2
1
1
10-ch
TSSOP20
MS51XC0BE
32
2
4
18
4
8
3
2
1
1
10-ch
QFN20
MS51EC0AE
32
2
4
26
4
10
3
2
1
1
15-ch
TSSOP28
MS51PC0AE
32
2
4
30
4
12
3
2
2
1
15-ch
LQFP32
MS51TC0AE
32
2
4
30
4
12
3
2
2
1
15-ch
QFN33
Note:
1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
2. ISO-7816 configurable as UART function, GPIO defined as UART2 ~ UART5.
3. Detailed package information please refer to Chapter 7
4. This document is only for 32K flash size part number product

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Nov. 28, 2019 Page 16 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
3.3 MS51 Series Selection Code
MS
51
F
B
9
A
E
Core
Line
Package
Flash
SRAM
Reserve
Temperature
1T 8051
Industry
51: Base
B: MSOP10 (3x3 mm)
D: TSSOP14 (4.4x5.0 mm)
E: TSSOP28 (4.4x9.7 mm)
F: TSSOP20 (4.4x6.5 mm)
I: SOP8 (4x5 mm)
O: SOP20 (300 mil)
P: LQFP32 (7x7 mm)
T: QFN33 (4x4 mm)
U: SOP28 (300 mil)
X: QFN20 (3x3mm)
A: 8 KB
B: 16 KB
C: 32 KB
0: 2 KB
1: 4 KB
2: 8/12 KB
3: 16 KB
6: 32 KB
8: 64 KB
9: 1 KB
A: 96 KB
E:-40 ~ 105°C

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Nov. 28, 2019 Page 17 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
4 PIN CONFIGURATION
Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool -
PinConfigure contains all Nuvoton NuMicro®Family chip series with all part number, and helps users
configure GPIO multi-function correctly and handily.
4.1 MS51 32K Series Multi Function Pin Diagram
4.1.1 QFN 33-pin Package Pin Diagram
Corresponding Part Number: MS51TC0AE
QFN33
33 VSS
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3
UART1_RXD / I2C0_SCL / ICE_CLK / P0.2
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
UART0_RXD / ADC_CH2 / P0.7
UART3_RXD / PWM3_CH1 / P3.4
nRESET / P2.0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
P2.1 / ADC_CH9 / PWM2_CH0
P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD
P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD
P2.4 / ADC_CH12 / T0
P1.3 / STADC / I2C0_SCL / ADC_CH13
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
P3.7 / UART1_TXD
P3.6 / UART1_RXD
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0 P3.2 / PWM3_CH0 P3.1 / PWM2_CH1 P3.5 / SPI0_SS
Top transparent view
Figure 4.1-1 Pin Assignment of LQFP-32 Package

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MS51 32K SERIES TECHNICAL REFERENCE MANUAL
4.1.2 LQFP 32-pin Package Pin Diagram
Corresponding Part Number: MS51PC0AE
LQFP32
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
nRESET / P2.0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
P2.1 / ADC_CH9 / PWM2_CH0
P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD
P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD
P2.4 / ADC_CH12 / T0
P1.3 / STADC / I2C0_SCL / ADC_CH13
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
P3.7 / UART1_TXD
P3.6 / UART1_RXD
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1 P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0 P3.2 / PWM3_CH0 P3.1 / PWM2_CH1 P3.5 / SPI0_SS
PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3
UART1_RXD / I2C0_SCL / ICE_CLK / P0.2
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
UART0_RXD / ADC_CH2 / P0.7
UART3_RXD / PWM3_CH1 / P3.4
Figure 4.1-2 Pin Assignment of LQFP-32 Package

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MS51 32K SERIES TECHNICAL REFERENCE MANUAL
4.1.3 TSSOP 28-pin Package Pin Diagram
Corresponding Part Number: MS51EC0AE
TSSOP28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
PWM1_CH1 / ADC_CH14 / PWM0_BRAKE / I2C0_SDA / PWM0_CH1 / P1.4
ADC_CH13 / I2C0_SCL / STADC / P1.3
T0 / ADC_CH12 / P2.4
UART4_TXD / PWM1_CH0 / ADC_CH11 / P2.3
UART4_RXD / PWM1_CH1 / ADC_CH10 / P2.2
PWM2_CH0 / ADC_CH9 / P2.1
SPI0_SS / P3.5
PWM1_CH0 / UART3_TXD / IC0 / PWM0_CH0 / P1.2
PWM1_CH1 / UART3_RXD / PWM0_CH1 / IC1 / CLKO / ADC_CH7 / P1.1
P1.7 / ADC_CH0 / INT1 / UART2_RXD / SPI0_CLK
P3.0 / ADC_CH1 / OSCIN / INT0 / UART2_TXD / SPI0_MOSI
P2.0 / nRESET
P3.4 / PWM3_CH1 / UART3_RXD
P0.7 / ADC_CH2 / UART0_RXD
P0.6 / ADC_CH3 / UART0_TXD
P0.5 / ADC_CH4 / IC6 / PWM0_CH2 / T0 / UART3_TXD / PWM2_CH0
P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1
P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD
P3.3 / PWM0_CH0 / CLKO / PWM0_BRAKE
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
Figure 4.1-3 Pin Assignment of TSSOP28 Package
4.1.4 TSSOP 20-pin Package Pin Diagram
Corresponding Part Number: MS51FC0AE
TSSOP20
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
UART0_RXD / ADC_CH2 / P0.7
nRESET / P2.0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1
P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
P1.3 / STADC / I2C0_SCL / ADC_CH13
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
Figure 4.1-4 Pin Assignment of TSSOP20 Package

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MS51 32K SERIES TECHNICAL REFERENCE MANUAL
4.1.5 QFN 20-pin Package Pin Diagram
Corresponding Part Number: MS51XC0BE
QFN20
33 VSS
1 2 3 4 5
10
9
8
7
6
15 14 13 12 11
16
17
18
19
20
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
UART0_TXD / ADC_CH3 / P0.6
UART0_RXD / ADC_CH2 / P0.7
nRESET / P2.0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
P1.3 / STADC / I2C0_SCL / ADC_CH13
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
P1.5 / PWM0_CH5 / SPI0_SS / IC7 / UART3_TXD / PWM3_CH1
VDD
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0 P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1 P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0 P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1
Top transparent view
Figure 4.1-5 Pin Assignment of QFN20 Package