Nuvoton ARM Cortex NuMicro M451 Series Product manual

M451
May. 4, 2018 Page 1of 1006 Rev.2.08
M451 SERIES TECHNICAL REFERENCE MANUAL
ARM®Cortex®-M
32-bit Microcontroller
NuMicro®Family
M451 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
1GENERAL DESCRIPTION..........................................................................................19
2FEATURES .................................................................................................................21
NuMicro®M451 Features.................................................................. 212.1
3Abbreviations.............................................................................................................27
4PARTS INFORMATION LIST AND PIN CONFIGURATION.......................................29
NuMicro®M451 Selection Guide......................................................... 294.1
4.1.1 NuMicro®M451 Naming Rule.....................................................................29
4.1.2 NuMicro®M451 Base Series Selection Guide ................................................. 30
4.1.3 NuMicro®M451M Series (M051 Pin Compatible) Selection Guide.........................31
4.1.4 NuMicro®M452 USB Series Selection Guide..................................................32
4.1.5 NuMicro®M453 CAN Series (CAN+USB) Selection Guide..................................33
Pin Configuration............................................................................ 344.2
4.2.1 NuMicro®M451 Base Series LQFP48 Pin Diagram ..........................................34
4.2.2 NuMicro®M451 Base Series LQFP64 Pin Diagram ..........................................35
4.2.3 NuMicro®M451 Base Series LQFP100 Pin Diagram.........................................36
4.2.4 NuMicro®M451M Series (M051 Pin Compatible) LQFP48 Pin Diagram ..................37
4.2.5 NuMicro®M451M Series (M058S Pin Compatible) LQFP64 Pin Diagram ................38
4.2.6 NuMicro®M452 USB Series LQFP48 Pin Diagram ...........................................39
4.2.7 NuMicro®M452 USB Series LQFP64 Pin Diagram ...........................................41
4.2.8 NuMicro®M452 USB Series LQFP100 Pin Diagram..........................................43
4.2.9 NuMicro®M453 CAN Series (CAN+USB) LQFP48 Pin Diagram ........................... 44
4.2.10 NuMicro®M453 CAN Series (CAN+USB) LQFP64 Pin Diagram ........................46
4.2.11 NuMicro®M453 CAN Series (CAN+USB) LQFP100 Pin Diagram....................... 48
Pin Description .............................................................................. 504.3
4.3.1 M451 Base Series LQFP48 Pin Description.................................................... 50
4.3.2 M451 Base Series LQFP64 Pin Description.................................................... 58
4.3.3 M451 Base Series LQFP100 Pin Description..................................................68
4.3.4 M451M Series (M051 Pin Compatible) LQFP48 Pin Description ...........................81
4.3.5 M451M Series (M058S Pin Compatible) LQFP64 Pin Description ......................... 89
4.3.6 M452 USB Series LQFP48 Pin Description ....................................................98
4.3.7 M452 USB Series LQFP64 Pin Description .................................................. 105
4.3.8 M452 USB Series LQFP100 Pin Description................................................. 114
4.3.9 M453 CAN Series(CAN+USB) LQFP48 Pin Description................................... 127
4.3.10 M453 CAN Series(CAN+USB) LQFP64 Pin Description ................................ 135

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4.3.11 M453 CAN Series(CAN+USB) LQFP100 Pin Description............................... 144
4.3.12 GPIO Multi-function Pin Summary .......................................................... 157
5BLOCK DIAGRAM....................................................................................................167
NuMicro®M451 Block Diagram..........................................................1675.1
6FUNCTIONAL DESCRIPTION..................................................................................169
ARM®Cortex®-M4 Core...................................................................1696.1
System Manager...........................................................................1726.2
6.2.1 Overview ........................................................................................... 172
6.2.2 System Reset...................................................................................... 172
6.2.3 Power Modes and Wake-up Sources.......................................................... 179
6.2.4 System Power Distribution ...................................................................... 181
6.2.5 System Memory Map............................................................................. 183
6.2.6 SRAM Memory Organization ................................................................... 186
6.2.7 Register Map ...................................................................................... 190
6.2.8 Register Description.............................................................................. 192
6.2.9 System Timer (SysTick) ......................................................................... 231
6.2.10 Nested Vectored Interrupt Controller (NVIC) .............................................. 235
6.2.11 System Control Register...................................................................... 258
Clock Controller............................................................................2676.3
6.3.1 Overview ........................................................................................... 267
6.3.2 Clock Generator................................................................................... 269
6.3.3 System Clock and SysTick Clock .............................................................. 270
6.3.4 Peripherals Clock ................................................................................. 271
6.3.5Power-down Mode Clock........................................................................ 272
6.3.6 Clock Output....................................................................................... 272
6.3.7 Register Map ...................................................................................... 274
6.3.8 Register Description.............................................................................. 275
Flash Memeory Controller (FMC) .......................................................2996.4
6.4.1 Overview ........................................................................................... 299
6.4.2 Features............................................................................................ 299
6.4.3 Block Diagram..................................................................................... 300
6.4.4 Functional Description ........................................................................... 303
6.4.5 Register Map ...................................................................................... 325
6.4.6 Register Description.............................................................................. 326
External Bus Interface (EBI) .............................................................3436.5

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6.5.1 Overview ........................................................................................... 343
6.5.2 Features............................................................................................ 343
6.5.3 Block Diagram..................................................................................... 344
6.5.4 Basic Configuration............................................................................... 344
6.5.5 Functional Description ........................................................................... 344
6.5.6 Register Map ...................................................................................... 351
6.5.7 Register Description.............................................................................. 352
General Purpose I/O (GPIO).............................................................3566.6
6.6.1 Overview ........................................................................................... 356
6.6.2 Features............................................................................................ 356
6.6.3 Block Diagram..................................................................................... 357
6.6.4 Basic Configuration............................................................................... 357
6.6.5 Functional Description ........................................................................... 358
6.6.6 Register Map ...................................................................................... 360
6.6.7 Register Description.............................................................................. 363
PDMA Controller (PDMA) ................................................................3786.7
6.7.1 Overview ........................................................................................... 378
6.7.2 Features............................................................................................ 378
6.7.3 Block Diagram..................................................................................... 378
6.7.4 Basic Configuration............................................................................... 379
6.7.5 Functional Description ........................................................................... 379
6.7.6 Register Map ...................................................................................... 385
6.7.7 Register Description.............................................................................. 387
Timer Controller (TMR) ...................................................................4166.8
6.8.1 Overview ........................................................................................... 416
6.8.2 Features............................................................................................ 416
6.8.3 Block Diagram..................................................................................... 417
6.8.4 Basic Configuration............................................................................... 418
6.8.5 Functional Description ........................................................................... 418
6.8.6 Register Map ...................................................................................... 423
6.8.7 Register Description.............................................................................. 425
PWM Generator and Capture Timer (PWM) ..........................................4356.9
6.9.1 Overview ........................................................................................... 435
6.9.2 Features............................................................................................ 435
6.9.3 Block Diagram..................................................................................... 437
6.9.4 Basic Configuration............................................................................... 440

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6.9.5 Functional Description ........................................................................... 440
6.9.6 Register Map ...................................................................................... 470
6.9.7 Register Description.............................................................................. 476
Watchdog Timer (WDT)...................................................................5406.10
6.10.1 Overview ........................................................................................ 540
6.10.2 Features ......................................................................................... 540
6.10.3 Block Diagram.................................................................................. 540
6.10.4 Clock Control ................................................................................... 540
6.10.5 Basic Configuration............................................................................ 541
6.10.6 Functional Description......................................................................... 541
6.10.7 Register Map.................................................................................... 543
6.10.8 Register Description........................................................................... 544
Window Watchdog Timer (WWDT) .....................................................5476.11
6.11.1 Overview ........................................................................................ 547
6.11.2 Features ......................................................................................... 547
6.11.3 Block Diagram.................................................................................. 547
6.11.4 Clock Control ................................................................................... 548
6.11.5 Basic Configuration............................................................................ 548
6.11.6 Functional Description......................................................................... 548
6.11.7 Register Map.................................................................................... 551
6.11.8 Register Description........................................................................... 552
Real Time Clock (RTC) ...................................................................5576.12
6.12.1 Overview ........................................................................................ 557
6.12.2 Features ......................................................................................... 557
6.12.3 Block Diagram.................................................................................. 558
6.12.4 Basic Configuration............................................................................ 558
6.12.5 Functional Description......................................................................... 558
6.12.6 Register Map.................................................................................... 565
6.12.7 Register Description........................................................................... 567
UART Interface Controller (UART)......................................................5906.13
6.13.1 Overview ........................................................................................ 590
6.13.2 Features ......................................................................................... 590
6.13.3 Block Diagram.................................................................................. 591
6.13.4 Basic Configuration............................................................................ 594
6.13.5 Functional Description......................................................................... 594
6.13.6 Register Map.................................................................................... 617

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6.13.7 Register Description........................................................................... 619
Smart Card Host Interface (SC).........................................................6466.14
6.14.1 Overview ........................................................................................ 646
6.14.2 Features ......................................................................................... 646
6.14.3 Block Diagram.................................................................................. 646
6.14.4 Basic Configuration............................................................................ 648
6.14.5 Functional description......................................................................... 648
6.14.6 Register Map.................................................................................... 657
6.14.7 Register Description........................................................................... 658
I2C Serial Interface Controller (I2C) .....................................................6846.15
6.15.1 Overview ........................................................................................ 684
6.15.2 Features ......................................................................................... 684
6.15.3 Basic Configuration............................................................................ 684
6.15.4 Block Diagram.................................................................................. 685
6.15.5 Functional Description......................................................................... 685
6.15.6 Register Map.................................................................................... 719
6.15.7 Register Description........................................................................... 720
Serial Peripheral Interface (SPI).........................................................7406.16
6.16.1 Overview ........................................................................................ 740
6.16.2 Features ......................................................................................... 740
6.16.3 Block Diagram.................................................................................. 741
6.16.4 Basic Configuration............................................................................ 742
6.16.5 Functional Description......................................................................... 743
6.16.6 Timing Diagram ................................................................................ 761
6.16.7 Programming Examples ...................................................................... 763
6.16.8 Register Map.................................................................................... 765
6.16.9 Register Description........................................................................... 766
USB Device Controller (USBD)..........................................................7856.17
6.17.1 Overview ........................................................................................ 785
6.17.2 Features ......................................................................................... 785
6.17.3 Block Diagram.................................................................................. 786
6.17.4 Basic Configuration............................................................................ 786
6.17.5 Functional Description......................................................................... 786
6.17.6 Register Map.................................................................................... 790
6.17.7 Register Description........................................................................... 792
USB 1.1 Host Controller (USBH)........................................................8086.18

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6.18.1 Overview ........................................................................................ 808
6.18.2 Features ......................................................................................... 808
6.18.3 Block Diagram.................................................................................. 809
6.18.4 Basic Configuration............................................................................ 810
6.18.5 Functional Description......................................................................... 810
6.18.6 Register Map.................................................................................... 812
6.18.7 Register Description........................................................................... 814
USB On-The-Go (OTG)...................................................................8456.19
6.19.1 Overview ........................................................................................ 845
6.19.2 Features ......................................................................................... 845
6.19.3 Block Diagram.................................................................................. 846
6.19.4 Basic Configuration............................................................................ 846
6.19.5 Functional Description......................................................................... 846
6.19.6 Register Map.................................................................................... 849
6.19.7 Register Description........................................................................... 850
Controller Area Network (CAN)..........................................................8586.20
6.20.1 Overview ........................................................................................ 858
6.20.2 Features ......................................................................................... 858
6.20.3 Basic Configuration............................................................................ 858
6.20.4 Block Diagram.................................................................................. 858
6.20.5 Functional Description......................................................................... 859
6.20.6 Test Mode....................................................................................... 861
6.20.7 CAN Communications......................................................................... 863
6.20.8 Register Map.................................................................................... 881
6.20.9 Register Description........................................................................... 887
CRC Controller (CRC) ....................................................................922
6.21
6.21.1 Overview ........................................................................................ 922
6.21.2 Features ......................................................................................... 922
6.21.3 Block Diagram.................................................................................. 922
6.21.4 Basic Configuration............................................................................ 923
6.21.5 Functional Description......................................................................... 923
6.21.6 Register Map.................................................................................... 924
6.21.7 Register Description........................................................................... 925
Enhanced 12-bit Analog-to-Digital Converter (EADC)...............................9306.22
6.22.1 Overview ........................................................................................ 930
6.22.2 Features ......................................................................................... 930

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6.22.3 Block Diagram.................................................................................. 931
6.22.4 Basic Configuration............................................................................ 931
6.22.5 Operation Procedure .......................................................................... 932
6.22.6 Register Map.................................................................................... 943
6.22.7 Register Description........................................................................... 946
Digital to Analog Converter (DAC) ......................................................9736.23
6.23.1 Overview ........................................................................................ 973
6.23.2 Features ......................................................................................... 973
6.23.3 Block Diagram.................................................................................. 973
6.23.4 Basic Configuration............................................................................ 974
6.23.5 Functional Description......................................................................... 974
6.23.6 Register Map.................................................................................... 978
6.23.7 Register Description........................................................................... 979
Analog Comparator Controller (ACMP) ................................................9866.24
6.24.1 Overview ........................................................................................ 986
6.24.2 Features ......................................................................................... 986
6.24.3 Block Diagram.................................................................................. 987
6.24.4 Basic Configuration............................................................................ 988
6.24.5 Functional Description......................................................................... 988
6.24.6 Register Map.................................................................................... 990
6.24.7 Register Description........................................................................... 991
7APPLICATION CIRCUIT...........................................................................................998
8ELECTRICAL CHARACTERISTICS.........................................................................999
9PACKAGE DIMENSIONS.......................................................................................1000
LQFP 100L (14x14x1.4 mm footprint 2.0 mm)...................................... 10009.1
LQFP 64L (10x10x1.4 mm footprint 2.0 mm) ....................................... 10019.2
LQFP 64L (7x7x1.4 mm footprint 2.0 mm)........................................... 10029.3
LQFP 48L (7x7x1.4mm footprint 2.0mm) ............................................ 10039.4
10 REVISION HISTORY...............................................................................................1004

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List of Figures
Figure 4.1-1 NuMicro®M451 Selection Code................................................................................ 29
Figure 4.2-1 NuMicro®M451 Base Series LQFP 48-pin Diagram................................................. 34
Figure 4.2-2 NuMicro®M451 Base Series LQFP 64-pin Diagram................................................. 35
Figure 4.2-3 NuMicro®M451 Base Series LQFP 100-pin Diagram............................................... 36
Figure 4.2-4 NuMicro®M451M Base Series (Pin Compatible with M051) LQFP 48-pin Diagram 37
Figure 4.2-5 NuMicro®M451M Base Series (Pin Compatible with M058S) LQFP 64-pin Diagram
................................................................................................................................................ 38
Figure 4.2-6 NuMicro®M451 USB Series LQFP 48-pin Diagram (M452LG/M452LE Device Only)
................................................................................................................................................ 39
Figure 4.2-7 NuMicro®M451 USB Series LQFP 48-pin Diagram (M452LD/M452LC Device Only)
................................................................................................................................................ 40
Figure 4.2-8 NuMicro®M451 USB Series LQFP 64-pin Diagram (M452RG/M452RE Device Only)
................................................................................................................................................ 41
Figure 4.2-9 NuMicro®M451 USB Series LQFP 64-pin Diagram (M452RD Device Only) ........... 42
Figure 4.2-10 NuMicro®M451 USB Series LQFP 100-pin Diagram (M452VG/M452VE Device
Only)........................................................................................................................................ 43
Figure 4.2-11 NuMicro®M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LG/M453LE
Device Only)............................................................................................................................ 44
Figure 4.2-12 NuMicro®M451 CAN Series (CAN+USB) LQFP 48-pin Diagram (M453LD/M453LC
Device Only)............................................................................................................................ 45
Figure 4.2-13 NuMicro®M451 CAN Series (CAN+USB) LQFP 64-pin Diagram (M453RG/M453RE
Device Only)............................................................................................................................ 46
Figure 4.2-14 NuMicro®M451 CAN Series (CAN+USB) LQFP 64-pin Diagram (M453RD Device
Only)........................................................................................................................................ 47
Figure 4.2-15 NuMicro®M451 CAN Series (CAN+USB) LQFP 100-pin Diagram
(M453VG/M453VE Device Only)............................................................................................ 48
Figure 4.2-16 NuMicro®M451 CAN Series (CAN+USB) LQFP 100-pin Diagram (M453VD Device
Only)........................................................................................................................................ 49
Figure 5.1-1 NuMicro®M45xG/M45xE Block Diagram ................................................................ 167
Figure 5.1-2 NuMicro®M45xD/M45xC Block Diagram ................................................................ 168
Figure 6.1-1 Cortex®-M4 Block Diagram...................................................................................... 169
Figure 6.2-1 System Reset Sources............................................................................................ 173
Figure 6.2-2 nRESET Reset Waveform....................................................................................... 176
Figure 6.2-3 Power-on Reset (POR) Waveform .......................................................................... 176
Figure 6.2-4 Low Voltage Reset (LVR) Waveform....................................................................... 177
Figure 6.2-5 Brown-out Detector (BOD) Waveform..................................................................... 178
Figure 6.2-6 Power Mode State Machine .................................................................................... 179
Figure 6.2-7 NuMicro®M451 Power Distribution Diagram........................................................... 182
Figure 6.2-8 SRAM Block Diagram.............................................................................................. 186
Figure 6.2-9 SRAM Memory Organization (M45xG/M45xE) ....................................................... 187

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Figure 6.2-10 SRAM Memory Organization (M45xD/M45xC) ..................................................... 188
Figure 6.3-1 Clock Generator Global View Diagram.................................................................... 268
Figure 6.3-2 Clock Generator Block Diagram.............................................................................. 269
Figure 6.3-3 System Clock Block Diagram .................................................................................. 270
Figure 6.3-4 HXT Stop Protect Procedure................................................................................... 271
Figure 6.3-5 SysTick Clock Control Block Diagram..................................................................... 271
Figure 6.3-6 Clock Source of Clock Output ................................................................................. 272
Figure 6.3-7 Clock Output Block Diagram ................................................................................... 273
Figure 6.4-1 Flash Memory Controller Block Diagram................................................................. 300
Figure 6.4-2 Data Flash Shared with APROM............................................................................. 303
Figure 6.4-3 Flash Memory Map.................................................................................................. 308
Figure 6.4-4 System Memory Map with IAP Mode ...................................................................... 309
Figure 6.4-5 LDROM with IAP Mode............................................................................................ 310
Figure 6.4-6 APROM with IAP Mode ........................................................................................... 310
Figure 6.4-7 System Memory Map without IAP mode ................................................................. 311
Figure 6.4-8 Boot Source Selection............................................................................................. 312
Figure 6.4-9 ISP Procedure Example .......................................................................................... 315
Figure 6.4-10 ISP 32-bit Programming Procedure....................................................................... 317
Figure 6.4-11 ISP 64-bit Programming Procedure....................................................................... 317
Figure 6.4-12 Multi-word Programming Time .............................................................................. 318
Figure 6.4-13 Firmware in SRAM for Multi-word Programming................................................... 319
Figure 6.4-14 Multi-word Programming Flow............................................................................... 320
Figure 6.4-15 Fast Flash Programming Verification Flow............................................................ 321
Figure 6.4-16 Verification Flow .................................................................................................... 322
Figure 6.4-17 Checksum for KB Calculation................................................................................ 322
Figure 6.4-18 Checksum Calculation Flow .................................................................................. 324
Figure 6.5-1 EBI Block Diagram................................................................................................... 344
Figure 6.5-2 Connection of 16-bit EBI Data Width with 16-bit Device......................................... 345
Figure 6.5-3 Connection of 8-bit EBI Data Width with 8-bit Device............................................. 346
Figure 6.5-4 Timing Control Waveform for 16-bit Data Width...................................................... 348
Figure 6.5-5 Timing Control Waveform for 8-bit Data Width........................................................ 349
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle........................................................ 350
Figure 6.6-1 GPIO Controller Block Diagram............................................................................... 357
Figure 6.6-2 Push-Pull Output...................................................................................................... 358
Figure 6.6-3 Open-Drain Output .................................................................................................. 358
Figure 6.6-4 Quasi-Bidirectional I/O Mode................................................................................... 359
Figure 6.7-1 PDMA Controller Block Diagram ............................................................................. 378

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Figure 6.7-2 Descriptor Table Entry Structure ............................................................................. 379
Figure 6.7-3 Basic Mode Finite State Machine............................................................................ 381
Figure 6.7-4 Descriptor Table Link List Structure ........................................................................ 382
Figure 6.7-5 Scatter-Gather Mode Finite State Machine............................................................. 382
Figure 6.7-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode ............ 384
Figure 6.8-1 Timer Controller Block Diagra ................................................................................. 417
Figure 6.8-2 Clock Source of Timer Controller ............................................................................ 418
Figure 6.8-3 Continuous Counting Mode..................................................................................... 420
Figure 6.9-1 PWM Generator Overview Block Diagram .............................................................. 437
Figure 6.9-2 PWM System Clock Source Control........................................................................ 437
Figure 6.9-3 PWM Clock Source Control..................................................................................... 438
Figure 6.9-4 PWM Independent Mode Architecture Diagram...................................................... 439
Figure 6.9-5 PWM Complementary Mode Architecture Diagram ................................................ 440
Figure 6.9-6 PWM_CH0 prescaler waveform .............................................................................. 441
Figure 6.9-7 PWM Up Counter Type............................................................................................ 441
Figure 6.9-8 PWM Down Counter Type....................................................................................... 442
Figure 6.9-9 PWM Up-Down Counter Type................................................................................. 442
Figure 6.9-10 PWM CMPDAT Events in Up-Down Counter Type............................................... 443
Figure 6.9-11 PWM Double Buffering Illustration......................................................................... 444
Figure 6.9-12 Period Loading in Up-Count Mode........................................................................ 445
Figure 6.9-13 Immediately Loading in Up-Count Mode............................................................... 446
Figure 6.9-14 Window Loading in Up-Count Mode...................................................................... 447
Figure 6.9-15 Center Loading in Up-Down-Count Mode ............................................................. 448
Figure 6.9-16 PWM One-shot Mode Output Waveform............................................................... 449
Figure 6.9-17 PWM Pulse Generation......................................................................................... 450
Figure 6.9-18 PWM 0% to 100% Pulse Generation..................................................................... 450
Figure 6.9-19 PWM Independent Mode Waveform ..................................................................... 451
Figure 6.9-20 PWM Complementary Mode Waveform................................................................ 452
Figure 6.9-21 PWM Group Function Waveform........................................................................... 453
Figure 6.9-22 PWM SYNC_IN Noise Filter Block Diagram ......................................................... 453
Figure 6.9-23 PWM Counter Synchronous Function Block Diagram........................................... 454
Figure 6.9-24 PWM Synchronous Function with SINSRC=0....................................................... 455
Figure 6.9-25 PWM_CH0 Output Control in Independent Mode ................................................. 455
Figure 6.9-26 PWM_CH0 and PWM_CH1 Output Control in Complementary Mode.................. 456
Figure 6.9-27 Dead-Time Insertion.............................................................................................. 457
Figure 6.9-28 Illustration of Mask Control Waveform................................................................... 457
Figure 6.9-29 Brake Noise Filter Block Diagram.......................................................................... 458

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Figure 6.9-30 Brake Block Diagram for PWM_CH0 and PWM_CH1 Pair................................... 459
Figure 6.9-31 Edge Detector Waveform for PWM_CH0 and PWM_CH1 Pair ............................ 460
Figure 6.9-32 Level Detector Waveform for PWM_CH0 and PWM_CH1 Pair............................ 460
Figure 6.9-33 Brake Source Block Diagram ................................................................................ 461
Figure 6.9-34 Brake System Fail Block Diagram......................................................................... 461
Figure 6.9-35 Initial State and Polarity Control with Rising Edge Dead-Time Insertion .............. 462
Figure 6.9-36 PWM_CH0 and PWM_CH1 Pair Accumulate Interrupt Waveform ....................... 463
Figure 6.9-37 PWM_CH0 and PWM_CH1 Pair Interrupt Architecture Diagram.......................... 464
Figure 6.9-38 PWM_CH0 and PWM_CH1 Pair Trigger EADC Block Diagram........................... 465
Figure 6.9-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform ...................... 466
Figure 6.9-40 PWM_CH0 and PWM_CH1 Pair Trigger DAC Block Diagram.............................. 466
Figure 6.9-41 PWM_CH0 Capture Block Diagram ...................................................................... 467
Figure 6.9-42 Capture Operation Waveform................................................................................ 468
Figure 6.9-43 Capture PDMA Operation Waveform of Channel 0............................................... 469
Figure 6.10-1 Watchdog Timer Block Diagram............................................................................ 540
Figure 6.10-2 Watchdog Timer Clock Control.............................................................................. 541
Figure 6.10-3 Watchdog Timer Time-out Interval and Reset Period Timing ............................... 542
Figure 6.11-1 WWDT Block Diagram........................................................................................... 547
Figure 6.11-2 WWDT Clock Control............................................................................................. 548
Figure 6.11-3 WWDT Reset and Reload Behavior...................................................................... 549
Figure 6.12-1 RTC Block Diagram............................................................................................... 558
Figure 6.12-2 Backup I/O Control Diagram.................................................................................. 564
Figure 6.13-1 UART Clock Control Diagram................................................................................ 592
Figure 6.13-2 UART Block Diagram............................................................................................. 593
Figure 6.13-3 Auto-Baud Rate Measurement.............................................................................. 596
Figure 6.13-4 Transmit Delay Time Operation............................................................................. 597
Figure 6.13-5 UART nCTS Wake-UP Case1............................................................................... 598
Figure 6.13-6 UART nCTS Wake-UP Case2............................................................................... 598
Figure 6.13-7 UART RX Data Wake-Up ...................................................................................... 598
Figure 6.13-8 Auto-Flow Control Block Diagram ......................................................................... 601
Figure 6.13-9 UART nCTS Auto-Flow Control Enabled............................................................... 602
Figure 6.13-10 UART nRTS Auto-Flow Control Enabled ............................................................ 602
Figure 6.13-11 UART nRTS Auto-Flow with Software Control.................................................... 603
Figure 6.13-12 IrDA Control Block Diagram ................................................................................ 603
Figure 6.13-13 IrDA TX/RX Timing Diagram ............................................................................... 604
Figure 6.13-14 Structure of LIN Frame........................................................................................ 605
Figure 6.13-15 Structure of LIN Byte ........................................................................................... 605

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Figure 6.13-16 Break Detection in LIN Mode............................................................................... 607
Figure 6.13-17 LIN Frame ID and Parity Format ......................................................................... 608
Figure 6.13-18 LIN Sync Field Measurement .............................................................................. 610
Figure 6.13-19 UART_BAUD Update Sequence in AR mode if SLVDUEN is 1 ......................... 611
Figure 6.13-20 UART_BAUD Update Sequence in AR mode if SLVDUEN is 0 ......................... 611
Figure 6.13-21 RS-485 nRTS Driving Level in Auto Direction Mode........................................... 615
Figure 6.13-22 RS-485 nRTS Driving Level with Software Control............................................. 615
Figure 6.13-23 Structure of RS-485 Frame ................................................................................. 616
Figure 6.14-1 SC Clock Control Diagram (4-bit Pre-scale Counter in Clock Controller) ............. 647
Figure 6.14-2 SC Controller Block Diagram................................................................................. 647
Figure 6.14-3 SC Data Character ................................................................................................ 648
Figure 6.14-4 SC Activation Sequence........................................................................................ 649
Figure 6.14-5 SC Warm Reset Sequence ................................................................................... 650
Figure 6.14-6 SC Deactivation Sequence.................................................................................... 651
Figure 6.14-7 Basic Operation Flow............................................................................................. 652
Figure 6.14-8 Initial Character TS................................................................................................ 653
Figure 6.14-9 SC Error Signal...................................................................................................... 653
Figure 6.14-10 Transmit Direction Block Guard Time Operation................................................. 655
Figure 6.14-11 Receive Direction Block Guard Time Operation.................................................. 656
Figure 6.14-12 Extended Guard Time Operation......................................................................... 656
Figure 6.15-1 I2C Controller Block Diagram................................................................................. 685
Figure 6.15-2 I2C Bus Timing....................................................................................................... 685
Figure 6.15-3 I2C Protocol............................................................................................................ 686
Figure 6.15-4 START and STOP Conditions............................................................................... 688
Figure 6.15-5 Bit Transfer on the I2C Bus.................................................................................... 690
Figure 6.15-6 Acknowledge on the I2C Bus................................................................................. 690
Figure 6.15-7 Master Transmits Data to Slave ............................................................................ 691
Figure 6.15-8 Master Reads Data from Slave ............................................................................. 691
Figure 6.15-9 Control I2C Bus according to the current I2C Status.............................................. 692
Figure 6.15-10 Master Transmitter Mode Control Flow............................................................... 693
Figure 6.15-11 Master Receiver Mode Control Flow................................................................... 694
Figure 6.15-12 Save Mode Control Flow ..................................................................................... 695
Figure 6.15-13 GC Mode ............................................................................................................. 697
Figure 6.15-14 Arbitration Lost..................................................................................................... 698
Figure 6.15-15 Bus Management Packet Protocol Diagram Element Key.................................. 700
Figure 6.15-167-Bit Addressable Device to Host Communication.............................................. 701
Figure 6.15-177-Bit Addressable Device Responds to an ARA ................................................. 701

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Figure 6.15-18 Bus Management ALERT function...................................................................... 702
Figure 6.15-19 SM Bus Time Out Timing .................................................................................... 703
Figure 6.15-20 I2C Data Shifting Direction................................................................................... 707
Figure 6.15-21 I2C Time-out Count Block Diagram ..................................................................... 711
Figure 6.15-22 EEPROM Random Read..................................................................................... 717
Figure 6.15-23 Protocol of EEPROM Random Read................................................................... 718
Figure 6.16-1 SPI Block Diagram (SPI0) ..................................................................................... 741
Figure 6.16-2 SPI Block Diagram (SPI1/2) .................................................................................. 741
Figure 6.16-3 SPI Peripheral Clock.............................................................................................. 743
Figure 6.16-4 SPI Master Mode Application Block Diagram........................................................ 744
Figure 6.16-5 SPI Slave Mode Application Block Diagram.......................................................... 744
Figure 6.16-632-Bit in One Transaction (Master Mode) ............................................................. 745
Figure 6.16-7 Automatic Slave Selection (SSACTPOL = 0, SPI_CYCLE > 0x2)........................ 746
Figure 6.16-8 Automatic Selection (SSACTPOL = 0, SPI_CYCLE < 0x3).................................. 746
Figure 6.16-9 Byte Reorder Function........................................................................................... 747
Figure 6.16-10 Timing Waveform for Byte Suspend.................................................................... 747
Figure 6.16-11 Two-Bit Transfer Mode System Architecture....................................................... 748
Figure 6.16-12 Two-Bit Transfer Mode Timing (Master Mode).................................................... 749
Figure 6.16-13 Bit Sequence of Dual Output Mode..................................................................... 750
Figure 6.16-14 Bit Sequence of Dual Input Mode........................................................................ 750
Figure 6.16-15 Bit Sequence of Quad Output Mode.................................................................... 751
Figure 6.16-16 Bit Sequence of Quad Input Mode ...................................................................... 751
Figure 6.16-17 FIFO Threshold Comparator ............................................................................... 752
Figure 6.16-18 Transmit FIFO Buffer Example............................................................................ 753
Figure 6.16-19 Receive FIFO Buffer Example............................................................................. 754
Figure 6.16-20 TX Underflow Event and Slave Under Run Event (Slave 3-Wire Mode Disabled)
.............................................................................................................................................. 754
Figure 6.16-21 Two-Bit Transfer Mode FIFO Buffer Example..................................................... 755
Figure 6.16-22 TX Underflow Event (Slave 3-Wire Mode Enabled)............................................ 755
Figure 6.16-23 Slave Mode Bit Count Error................................................................................. 756
Figure 6.16-24 Slave Time-out Event .......................................................................................... 756
Figure 6.16-25 I2S Data Format Timing Diagram......................................................................... 758
Figure 6.16-26 MSB Justified Data Format Timing Diagram....................................................... 759
Figure 6.16-27 PCM Mode A Timing Diagram............................................................................. 759
Figure 6.16-28 PCM Mode B Timing Diagram............................................................................. 759
Figure 6.16-29 FIFO Contents for Various I2S Modes................................................................. 760
Figure 6.16-30 SPI Timing in Master Mode ................................................................................. 761
Figure 6.16-31 SPI Timing in Master Mode (Alternate Phase of SPIn_CLK).............................. 761

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Figure 6.16-32 SPI Timing in Slave Mode ................................................................................... 762
Figure 6.16-33 SPI Timing in Slave Mode (Alternate Phase of SPIn_CLK) ................................ 762
Figure 6.17-1 USB Block Diagram............................................................................................... 786
Figure 6.17-2 NEVWK Interrupt Operation Flow.......................................................................... 787
Figure 6.17-3 Endpoint SRAM Structure ..................................................................................... 788
Figure 6.17-4 Setup Transaction Followed by Data IN Transaction............................................ 789
Figure 6.17-5 Data Out Transfer.................................................................................................. 789
Figure 6.18-1 USB 1.1 Host Controller Block Diagram................................................................ 809
Figure 6.19-1 USB OTG Block Diagram...................................................................................... 846
Figure 6.19-2 USB Device Mode ................................................................................................. 847
Figure 6.19-3 USB Host Mode..................................................................................................... 847
Figure 6.20-1 CAN Peripheral Block Diagram ............................................................................. 859
Figure 6.20-2 CAN Core in Silent Mode ...................................................................................... 861
Figure 6.20-3 CAN Core in Loop Back Mode .............................................................................. 862
Figure 6.20-4 CAN Core in Loop Back Mode Combined with Silent Mode ................................. 862
Figure 6.20-5 Data transfer between IFn Registers and Message.............................................. 865
Figure 6.20-6 Application Software Handling of a FIFO Buffer.................................................... 870
Figure 6.20-7 Bit Timing............................................................................................................... 872
Figure 6.20-8 Propagation Time Segment................................................................................... 873
Figure 6.20-9 Synchronization on “late” and “early” Edges ......................................................... 875
Figure 6.20-10 Filtering of Short Dominant Spikes...................................................................... 876
Figure 6.20-11 Structure of the CAN Core’s CAN Protocol Controller ........................................ 877
Figure 6.21-1 CRC Generator Block Diagram............................................................................. 922
Figure 6.22-1 ADC Converter Block Diagram.............................................................................. 931
Figure 6.22-2 Sample Module 0~3 Block Diagram...................................................................... 932
Figure 6.22-3 Sample Module 4~15 Block Diagram................................................................... 933
Figure 6.22-4 Sample Module 16~18 Block Diagram.................................................................. 933
Figure 6.22-5 EADC Clock Control.............................................................................................. 934
Figure 6.22-6 Example ADC Conversion Timing Diagram, n=0~18............................................ 935
Figure 6.22-7 Sample module Conversion Priority Arbitrator Diagram........................................ 936
Figure 6.22-8 Specific Sample Module A/D EOC Signal for ADINT0~3 Interrupt ....................... 937
Figure 6.22-9 STADC De-bounce Timing Diagram ..................................................................... 938
Figure 6.22-10 PWM-triggered ADC Start Conversion................................................................ 938
Figure 6.22-11 External triggered ADC Start Conversion............................................................ 938
Figure 6.22-12 Conversion Start Delay Timing Diagram............................................................. 939
Figure 6.22-13 A/D Extend Sampling Timing Diagram................................................................ 940
Figure 6.22-14 A/D Conversion Result Monitor Logics Diagram................................................. 941

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Figure 6.22-15 A/D Controller Interrupts...................................................................................... 942
Figure 6.23-1 Digital-to-Analog Converter Block Diagram........................................................... 973
Figure 6.23-2 Data Holding Register Format............................................................................... 974
Figure 6.23-3 DAC Conversion Started by Software Write Trigger............................................. 975
Figure 6.23-4 DAC Conversion Started by Hardware Trigger Event........................................... 975
Figure 6.23-5 DAC PDMA Underrun Condition Example ............................................................ 976
Figure 6.23-6 DAC Continuous Conversion with Software PDMA Mode .................................... 977
Figure 6.23-7 DAC Interrupt Source ............................................................................................ 977
Figure 6.24-1 Analog Comparator Block Diagram....................................................................... 987
Figure 6.24-2 Comparator Controller Interrupt Sources .............................................................. 988
Figure 6.24-3 Comparator Hysteresis Function........................................................................... 989
Figure 6.24-4 Comparator Reference Voltage Block Diagram .................................................... 989

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List of Tables
Table 1-1 Key Features Support Table.......................................................................................... 19
Table 3-1 List of Abbreviations....................................................................................................... 28
Table 4-1 M451 GPIO Multi-function Table ................................................................................. 166
Table 6-1 Reset Value of Registers............................................................................................. 175
Table 6-2 Power Mode Difference Table ..................................................................................... 179
Table 6-3 Clocks in Power Modes ............................................................................................... 181
Table 6-4 Condition of Entering Power-down Mode Again.......................................................... 181
Table 6-5 Address Space Assignments for On-Chip Controllers................................................. 185
Table 6-6 Exception Model .......................................................................................................... 236
Table 6-7 Interrupt Number Table................................................................................................ 238
Table 6-8 Priority Grouping.......................................................................................................... 262
Table 6-9 Power-down Mode Control Table ................................................................................ 277
Table 6-10 ISP Command List..................................................................................................... 314
Table 6-11 Channel Priority Table (M45xG/M45xE Only)............................................................ 380
Table 6-12 Channel Priority Table (M45xD/M45xC Only)............................................................ 380
Table 6-13 PWM System Clock Source Control Registers Setting Table ................................... 438
Table 6-14 PWM Pulse Generation Event Priority for Up-Counter.............................................. 450
Table 6-15 PWM Pulse Generation Event Priority for Down-Counter......................................... 451
Table 6-16 PWM Pulse Generation Event Priority for Up-Down-Counter ................................... 451
Table 6-17 Watchdog Timer Time-out Interval Period Selection................................................. 542
Table 6-18 WWDT Prescaler Value Selection............................................................................. 549
Table 6-19 CMPDAT Setting Limitation....................................................................................... 550
Table 6-20 RTC control registers access attribute....................................................................... 559
Table 6-21 NuMicro®M451 Series UART Feature ...................................................................... 591
Table 6-22 UART Interface Controller Pin ................................................................................... 594
Table 6-23 UART Controller Baud Rate Equation Table............................................................. 594
Table 6-24 UART Controller Baud Rate Parameter Setting Example Table............................... 595
Table 6-25 UART Controller Baud Rate Register Setting Example Table................................... 596
Table 6-26 UART Controller Interrupt Source and Flag List........................................................ 600
Table 6-27 UART Line Control of Word and Stop Length Setting ............................................... 600
Table 6-28 UART Line Control of Parity Bit Setting..................................................................... 600
Table 6-29 LIN Header Selection in Master Mode....................................................................... 606
Table 6-30 SC Host Controller Pin Description............................................................................ 648
Table 6-31 UART Pin Description................................................................................................ 648
Table 6-32 Timer2/Timer1/Timer0 Operation Mode .................................................................... 655
Table 6-33 Reserved SMBus Address......................................................................................... 699

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Table 6-34 I2C Status Code Description ...................................................................................... 709
Table 6-35 SPI/I2S Interface Controller Pin.................................................................................. 743
Table 6-36 Initialization of a Transmit Object............................................................................... 867
Table 6-37 Initialization of a Receive Object................................................................................ 868
Table 6-38 CAN Bit Time Parameters.......................................................................................... 872
Table 6-39 CAN Register Map for Each Bit Function .................................................................. 886
Table 6-40 Last Error Code.......................................................................................................... 891
Table 6-41 Source of Interrupts ................................................................................................... 894
Table 6-42 IF1 and IF2 Message Interface Register ................................................................... 897
Table 6-43 Structure of a Message Object in the Message Memory........................................... 911
Table 6-44 EADC Differential Model Channel Table ................................................................... 941

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1 GENERAL DESCRIPTION
The M451 series includes a total of 33 ARM®Cortex®-M4F based products, including the M451
Base Series, M452 USB Series, M453 CAN Series, and M451M Series which is pin compatible
with M051 LQFP48 and M058S LQFP64. By planning a complete product line, Nuvoton hopes to
fulfill the demand for the ARM®Cortex®-M4F core with products at all levels and realize its
customer commitment: total support for long-term competitiveness enhancement, and to fulfill
their current product development demand and future innovation imagination.
The M451 series embedded with the ARM®Cortex®-M4F core supports DSC (digital signal
controller) and FPU (float point unit) and features high performance computing capability running
up to 72 MHz, built-in 256/128/72/40 KB Flash ROM, 32/16 KB SRAM complying with IEC60730
and independent 4 KB in-system programming Flash ROM for developing more flexible online
upgrade code that support external UART, SPI, I2C, CAN and USB. It also supports EBI to
provide greater flexibility for external memory. The entire M451 series is provided with
outstanding specifications: four 32-bit timers, dual watchdogs, and integrates plenty of peripherals
such as PDMA and RTCs, five UARTs that support 16-byte FIFO, three sets of SPI controllers
that support quad mode, two I²C devices that support SMBus and PMBus, two sets of I2S, two
LINs, CAN bus, ISO-7816-3 interface, full-speed USB OTG, full-speed USB devices, 16-channel
12-bit ADC with 1 MSPS conversion rate, built-in reference voltage (VREF) for circuit generation,
12-bit DAC, two analog comparators and temperature detectors.
The M451 series provides two special designs. One is high-resolution 144 MHz PWM with high-
speed electromechanical control timer and resolution<7ns. In conjunction with a driver ADC, it
delivers hardware brake protection and pulse capture functions to save MCU computing burden
and effectively carry out advanced computing required by motor control, making it exceptionally
outstanding in industrial automation and motor control performance. The other is VAI (Voltage
Adjustment Interface) system to support voltage level adjustment with individual I/O (1.8V-5.5V)
for saving additional cost on adjusting the interface voltage difference of peripheral components.
The M451 series also provides the wide operating voltage (2.5V-5.5V) and 5V-tolerance input I/O
to significantly enhance system stability, industrial operating temperature (-40°C - 105°C),
22.1184 MHz internal RC oscillator (HIRC variation < ±2%) and 32.768 kHz external crystal
oscillator to trim HIRC (HIRC variation < ±0.25%) working at -40˚C- 105˚C to boost system
immunity and adequately fulfill the high precision demand of communications. The M451 series is
specifically suitable for high-performance and high-precision applications, such as industrial
control, system automation, security surveillance, autotronics and digital power control.
Product Line
USB
CAN
UART
I2C
I2S
SPI
PWM
ADC
DAC
RTC
EBI
M453
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●
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M452
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M451
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M451M
(M051 Pin Compatible)
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Table 1-1 Key Features Support Table
The NuMicro®M451 series is suitable for a wide range of applications such as:
Industrial Automation
PLCs
Inverters
Home Automation

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Security Alarm System
Power Metering
Portable Data Collector
Portable RFID Reader
System Supervisors
Smart Card Reader
Printer
Bar Code Scanner
Motor Control
Digital Power