Epson S1C31D50 Owner's manual

Seiko Epson Corporation
S1C31D50TECHNICAL MANUAL
(Rev. 1.00)
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
S1C31D50
Technical Manual
®
Rev. 1.00

Seiko Epson Corporation
S1C31D50TECHNICAL MANUAL
(Rev. 1.00)
Evaluation board/kit and Development tool important notice
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demonstration, or development purposes only. Do not use it for other purposes. It is not
intended to meet the requirements of design for finished products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer
and is not a consumer product. The user should use it properly and in a safe manner. Seiko
Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed
by the use of it. The user should cease to use it when any abnormal issue occurs even during
proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any
notice.
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©SEIKO EPSON CORPORATION 2018, All rights reserved.

Seiko Epson Corporation
S1C31D50TECHNICAL MANUAL
(Rev. 1.00)
Preface
This is a technical manual for designers and programmers who develop a product using the
S1C31D50. This document describes the functions of the IC, embedded peripheral circuit operations,
and their control methods.
Notational conventions and symbols in this manual
Register address
Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit
Area” in the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the
Appendix.
Register and control bit names
In this manual, the register and control bit names are described as shown below to distinguish
from signal and pin names.
XXX register:
Represents a register including its all bits.
XXX.YYY bit:
Represents the one control bit YYY in the XXX register.
XXX.ZZZ[1:0] bits:
Represents the two control bits ZZZ1 and ZZZ0 in the XXX register
Register table contents and symbols
Initial:
Value set at initialization
Reset
Initialization condition. The initialization condition depends on the reset group (H0, H1, or
S0). For more information on the reset groups, refer to “Initialization Conditions (Reset
Groups)” in the “Power Supply, Reset, and Clocks” chapter.
R/W:
R =
Read only bit
W =
Write only bit
WP =
Write only bit with a write protection using the SYSPROT.PROT[15:0] bits
R/W =
Read/write bit
R/WP =
Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits
(reserved): Reserved bit. Do not alter from the initial value.
Control bit read/write values
This manual describes control bit values in a hexadecimal notation except for one-bit values (and
except when decimal or binary notation is required in terms of explanation). The values are
described as shown below according to the control bit width.
Bit
0 or 1
to 4 bits
0x0 to 0xf
5 to 8 bits
0x00 to 0xff
9 to 12 bits
0x000 to 0xfff
13 to 16 bits
0x0000 to 0xffff
Decimal
0 to 9999...
Binary
0b0000... to 0b1111...
Channel number
Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The
peripheral circuit chapters use ‘n’ as the value that represents the channel number in the register
and pin names regard- less of the number of channel actually implemented. Normally, the
descriptions are applied to all channels. If there is a channel that has different functions from others,
the channel number is specified clearly. Example) T16_nCTL register of the 16-bit timer
If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only
If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL
For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in
the “Overview” chapter.
Low power mode
This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer
to sleep mode and deep sleep mode in the Cortex®-M0+ processor, respectively.

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S1C31D50TECHNICAL MANUAL
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1. Overview ________________________________________________________ 1-1
1.1. Features___________________________________________________________ 1-1
1.2. Block Diagram ______________________________________________________ 1-4
1.3. Pins _______________________________________________________________ 1-5
1.3.1. Pin Configuration Diagram________________________________________________ 1-5
1.3.2. PinDescriptions ________________________________________________________ 1-9
2. Power Supply, Reset, and Clocks _____________________________________ 2-1
2.1. Power Generator (PWGA)_____________________________________________ 2-1
2.1.1. Overview______________________________________________________________ 2-1
2.1.2. Pins __________________________________________________________________ 2-2
2.1.3. VD1 Regulator Operation Mode ___________________________________________ 2-2
2.1.4. VD1 Regulator Voltage Mode _____________________________________________ 2-3
2.2. System Reset Controller (SRC) _________________________________________ 2-4
2.2.1. Overview______________________________________________________________ 2-4
2.2.2. Input Pin ______________________________________________________________ 2-4
2.2.3. Reset Sources __________________________________________________________ 2-5
2.2.4. Initialization Conditions(Reset Groups) ______________________________________ 2-6
2.3. Clock Generator (CLG)________________________________________________ 2-7
2.3.1. Overview______________________________________________________________ 2-7
2.3.2. Input/Output Pins ______________________________________________________ 2-8
2.3.3. Clock Sources __________________________________________________________ 2-9
2.3.4. Operations ___________________________________________________________ 2-12
2.4. Operating Mode ___________________________________________________ 2-18
2.4.1. Initial Boot Sequence ___________________________________________________ 2-18
2.4.2. Transition between Operating Modes______________________________________ 2-18
2.5. Interrupts ________________________________________________________ 2-20
2.6. Control Registers ___________________________________________________ 2-21
3. CPU AND DEBUGGER ______________________________________________ 3-1
3.1. Overview __________________________________________________________ 3-1
3.2. CPU Core __________________________________________________________ 3-1
3.3. Debugger__________________________________________________________ 3-1
3.3.1. List of debugger input/output pins _________________________________________ 3-1
3.3.2. External Connection _____________________________________________________ 3-1
4. Memory and Bus__________________________________________________ 4-1
4.1. Overview __________________________________________________________ 4-1
4.2. Bus Access Cycle ____________________________________________________ 4-2
4.3. Flash Memory ______________________________________________________ 4-3
4.3.1. Flash Memory Pin _______________________________________________________ 4-3
4.3.2. Flash Bus Access Cycle Setting _____________________________________________ 4-3
4.3.3. Flash Programming ______________________________________________________ 4-3

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4.4. RAM______________________________________________________________ 4-3
4.5. Peripheral Circuit Control Registers _____________________________________ 4-4
4.5.1. System-Protect Function _________________________________________________ 4-4
4.6. Instruction Cache ___________________________________________________ 4-4
4.7. Memory Mapped Access Area For External Flash Memory __________________ 4-4
4.8. Control Registers ____________________________________________________ 4-5
5. Interrupt ________________________________________________________ 5-1
5.1. Overview __________________________________________________________ 5-1
5.2. Vector Table________________________________________________________ 5-2
5.2.1. Vector Table Offset Address (VTOR) _________________________________________ 5-5
5.2.2. Priority of Interrupts_____________________________________________________ 5-5
5.3. Peripheral Circuit Interrupt Control _____________________________________ 5-5
5.4. NMI ______________________________________________________________ 5-5
6. DMA Controller (DMAC) ____________________________________________ 6-1
6.1. Overview __________________________________________________________ 6-1
6.2. Operations_________________________________________________________ 6-2
6.2.1. Initialization ____________________________________________________________ 6-2
6.3. Priority ____________________________________________________________ 6-2
6.4. Data Structure______________________________________________________ 6-2
6.4.1. Transfer Source End Pointer _______________________________________________ 6-4
6.4.2. Transfer Destination End Pointer ___________________________________________ 6-4
6.4.3. Control Data ___________________________________________________________ 6-4
6.5. DMA Transfer Mode _________________________________________________ 6-6
6.5.1. Basic Transfer __________________________________________________________ 6-6
6.5.2. Auto-Request Transfer ___________________________________________________ 6-6
6.5.3. Ping-Pong Transfer ______________________________________________________ 6-7
6.5.4. Memory Scatter-Gather Transfer __________________________________________ 6-8
6.5.5. Peripheral Scatter-Gather Transfer ________________________________________ 6-11
6.6. DMA Transfer Cycle_________________________________________________ 6-12
6.7. Interrupts ________________________________________________________ 6-12
6.8. Control Registers ___________________________________________________ 6-13
7. I/O Ports (PPORT) _________________________________________________ 7-1
7.1. Overview __________________________________________________________ 7-1
7.2. I/O Cell Structure and Functions _______________________________________ 7-2
7.2.1. Schmitt Input __________________________________________________________ 7-2
7.2.2. Over Voltage Tolerant Fail-Safe Type I/O Cell _________________________________ 7-2
7.2.3. Pull-Up/Pull-Down ______________________________________________________ 7-2
7.2.4. CMOS Output and High Impedance State ___________________________________ 7-3
7.3. Clock Settings ______________________________________________________ 7-3
7.3.1. PPORT Operating Clock __________________________________________________ 7-3
7.3.2. Clock Supply in SLEEP Mode_______________________________________________ 7-3

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7.3.3. Clock Supply During Debugging ____________________________________________ 7-3
7.4. Operations _________________________________________________________ 7-4
7.4.1. Initialization ____________________________________________________________ 7-4
7.4.2. Port Input/Output Control________________________________________________ 7-6
7.5. Interrupts _________________________________________________________ 7-7
7.6. Control Registers ____________________________________________________ 7-8
7.7. Control Register and Port Function Configuration of this IC __________________ 7-14
7.7.1. P0 Port Group_________________________________________________________ 7-14
7.7.2. P1 Port Group _________________________________________________________ 7-15
7.7.3. P2 Port Group _________________________________________________________ 7-16
7.7.4. P3 Port Group _________________________________________________________ 7-17
7.7.5. P4 Port Group _________________________________________________________ 7-18
7.7.6. P5 Port Group _________________________________________________________ 7-19
7.7.7. P6 Port Group _________________________________________________________ 7-20
7.7.8. P7 Port Group _________________________________________________________ 7-21
7.7.9. P8 Port Group _________________________________________________________ 7-22
7.7.10. P9 Port Group _________________________________________________________ 7-23
7.7.11. PA Port Group_________________________________________________________ 7-24
7.7.12. PD Port Group_________________________________________________________ 7-25
7.7.13. Common Registers between Port Groups ___________________________________ 7-26
8. Universal Port Multiplexer (UPMUX)__________________________________ 8-1
8.1. Overview __________________________________________________________ 8-1
8.2. Peripheral Circuit I/O Function Assignment _______________________________ 8-1
8.3. Control Registers ____________________________________________________ 8-2
9. Watchdog Timer (WDT2)____________________________________________ 9-1
9.1. Overview __________________________________________________________ 9-1
9.2. Clock Settings ______________________________________________________ 9-1
9.2.1. WDT2 Operating Clock___________________________________________________ 9-1
9.2.2. Clock Supply in DEBUG Mode _____________________________________________ 9-1
9.3. Operations_________________________________________________________ 9-2
9.3.1. WDT2 Control __________________________________________________________ 9-2
9.3.2. Operations in HALT and SLEEP Modes _______________________________________ 9-3
9.4. Control Registers____________________________________________________ 9-4
10. Real-Time Clock (RTCA) __________________________________________ 10-1
10.1. Overview _______________________________________________________ 10-1
10.2. Output Pin and External Connection _________________________________ 10-1
10.2.1. Output Pin____________________________________________________________ 10-1
10.3. Clock Settings ___________________________________________________ 10-2
10.3.1. RTCA Operating Clock __________________________________________________ 10-2
10.3.2. Theoretical Regulation Function __________________________________________ 10-2
10.4. Operations______________________________________________________ 10-4

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10.4.1. RTCA Control__________________________________________________________ 10-4
10.4.2. Real-Time Clock Counter Operations ______________________________________ 10-5
10.4.3. Stopwatch Control _____________________________________________________ 10-5
10.4.4. Stopwatch Count-up Pattern_____________________________________________ 10-6
10.5. Interrupts ______________________________________________________ 10-7
10.6. Control Registers _________________________________________________ 10-8
11. Supply Voltage Detector (SVD3)___________________________________ 11-1
11.1. Overview _______________________________________________________ 11-1
11.2. Input Pins and External Connection __________________________________ 11-2
11.2.1. Input Pins ____________________________________________________________ 11-2
11.2.2. External Connection ____________________________________________________ 11-2
11.3. Clock Settings ___________________________________________________ 11-3
11.3.1. SVD3 Operating Clock __________________________________________________ 11-3
11.3.2. Clock Supply in SLEEP Mode______________________________________________ 11-3
11.3.3. Clock Supply in DEBUG Mode ____________________________________________ 11-3
11.4. Operations______________________________________________________ 11-4
11.4.1. SVD3 Control__________________________________________________________ 11-4
11.4.2. SVD3Operations_______________________________________________________ 11-4
11.5. SVD3 Interrupt and Reset __________________________________________ 11-6
11.5.1. SVD3 Interrupt ________________________________________________________ 11-6
11.5.2. SVD3 Reset ___________________________________________________________ 11-6
11.6. Control Registers _________________________________________________ 11-7
12. 16-bit Timers (T16) _____________________________________________ 12-1
12.1. Overview _______________________________________________________ 12-1
12.2. Input Pin _______________________________________________________ 12-1
12.3. Clock Settings ___________________________________________________ 12-2
12.3.1. T16 Operating Clock____________________________________________________ 12-2
12.3.2. Clock Supply in SLEEP Mode______________________________________________ 12-2
12.3.3. Clock Supply During Debugging ___________________________________________ 12-2
12.3.4. Event Counter Clock ____________________________________________________ 12-2
12.4. Operations ______________________________________________________ 12-3
12.4.1. Initialization ___________________________________________________________ 12-3
12.4.2. Counter Underflow ____________________________________________________ 12-3
12.4.3. Operations in Repeat Mode _____________________________________________ 12-3
12.4.4. Operations in One-shot Mode____________________________________________ 12-4
12.4.5. Counter Value Read ____________________________________________________ 12-4
12.5. Interrupt _______________________________________________________ 12-4
12.6. Control Registers _________________________________________________ 12-5
13. UART (UART3)__________________________________________________ 13-1
13.1. Overview _______________________________________________________ 13-1
13.2. Input/Output Pins and External Connections __________________________ 13-2
13.2.1. List of Input/Output Pins ________________________________________________ 13-2
13.2.2. ExternalConnections ___________________________________________________ 13-3

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13.2.3. Input Pin Pull-Up Function _______________________________________________ 13-3
13.2.4. Output Pin Open-Drain Output Function____________________________________ 13-3
13.2.5. Input/Output Signal Inverting Function_____________________________________ 13-3
13.3. Clock Settings ___________________________________________________ 13-4
13.3.1. UART3 Operating Clock _________________________________________________ 13-4
13.3.2. Clock Supply in SLEEP Mode______________________________________________ 13-4
13.3.3. Clock Supply During Debugging ___________________________________________ 13-4
13.3.4. Baud Rate Generator ___________________________________________________ 13-4
13.4. Data Format ____________________________________________________ 13-5
13.5. Operations______________________________________________________ 13-6
13.5.1. Initialization __________________________________________________________ 13-6
13.5.2. Data Transmission______________________________________________________ 13-6
13.5.3. Data Reception________________________________________________________ 13-8
13.5.4. IrDA Interface_________________________________________________________ 13-9
13.5.5. Carrier Modulation____________________________________________________ 13-10
13.6. Receive Errors __________________________________________________ 13-11
13.6.1. Framing Error ________________________________________________________ 13-11
13.6.2. Parity Error __________________________________________________________ 13-11
13.6.3. OverrunError ________________________________________________________ 13-11
13.7. Interrupts _____________________________________________________ 13-12
13.8. DMA Transfer Requests___________________________________________ 13-12
13.9. Control Registers ________________________________________________ 13-13
14. Synchronous Serial Interface (SPIA) ________________________________ 14-1
14.1. Overview _______________________________________________________ 14-1
14.2. Input/Output Pins and External Connections __________________________ 14-2
14.2.1. List of Input/Output Pins ________________________________________________ 14-2
14.2.2. ExternalConnections ___________________________________________________ 14-2
14.2.3. Pin Functions in Master Mode and Slave Mode ______________________________ 14-3
14.2.4. Input Pin Pull-Up/Pull-Down Function _____________________________________ 14-3
14.3. Clock Settings ___________________________________________________ 14-4
14.3.1. SPIA Operating Clock ___________________________________________________ 14-4
14.3.2. Clock Supply During Debugging ___________________________________________ 14-5
14.3.3. SPI Clock (SPICLKn) Phase and Polarity _____________________________________ 14-5
14.4. Data Format ____________________________________________________ 14-5
14.5. Operations______________________________________________________ 14-6
14.5.1. Initialization __________________________________________________________ 14-6
14.5.2. Data Transmission in Master Mode________________________________________ 14-6
14.5.3. Data Reception in Master Mode__________________________________________ 14-9
14.5.4. Terminating Data Transfer in Master Mode ________________________________ 14-11
14.5.5. Data Transfer in Slave Mode ____________________________________________ 14-11
14.5.6. Terminating Data Transfer in Slave Mode __________________________________ 14-12
14.6. Interrupts _____________________________________________________ 14-13
14.7. DMA Transfer Requests___________________________________________ 14-14

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14.8. Control Registers ________________________________________________ 14-15
15. Quad Synchronous Serial Interface (QSPI) ___________________________ 15-1
15.1. Overview _______________________________________________________ 15-1
15.2. Input/Output Pins and External Connections __________________________ 15-2
15.2.1. List of Input/Output Pins ________________________________________________ 15-2
15.2.2. ExternalConnections ___________________________________________________ 15-2
15.2.3. Pin Functions in Master Mode and Slave Mode ______________________________ 15-6
15.2.4. Input Pin Pull-Up/Pull-Down Function _____________________________________ 15-6
15.3. Clock Settings ___________________________________________________ 15-7
15.3.1. QSPI Operating Clock ___________________________________________________ 15-7
15.3.2. Clock Supply During Debugging ___________________________________________ 15-7
15.3.3. QSPI Clock (QSPICLKn) Phase and Polarity___________________________________ 15-8
15.4. Data Format ____________________________________________________ 15-8
15.5. Operations _____________________________________________________ 15-10
15.5.1. Register Access Mode _________________________________________________ 15-10
15.5.2. Memory Mapped Access Mode _________________________________________ 15-10
15.5.3. Initialization __________________________________________________________ 15-12
15.5.4. Data Transmission in Master Mode_______________________________________ 15-13
15.5.5. Data Reception in Register Access Master Mode ___________________________ 15-15
15.5.6. Data Reception in Memory Mapped Access Mode __________________________ 15-18
15.5.7. Terminating Memory Mapped Access Operations ___________________________ 15-27
15.5.8. Terminating Data Transfer in Master Mode ________________________________ 15-27
15.5.9. Data Transfer in Slave Mode ____________________________________________ 15-28
15.5.10. Terminating Data Transfer in Slave Mode ________________________________ 15-29
15.6. Interrupts _____________________________________________________ 15-30
15.7. DMA Transfer Requests___________________________________________ 15-32
15.8. Control Registers ________________________________________________ 15-33
16. I2C (I2C) ______________________________________________________ 16-1
16.1. Overview _______________________________________________________ 16-1
16.2. Input/Output Pins and External Connections __________________________ 16-2
16.2.1. List of Input/Output Pins ________________________________________________ 16-2
16.2.2. ExternalConnections ___________________________________________________ 16-2
16.3. Clock Settings ___________________________________________________ 16-3
16.3.1. I2C Operating Clock ____________________________________________________ 16-3
16.3.2. Clock Supply During Debugging ___________________________________________ 16-3
16.3.3. Baud Rate Generator ___________________________________________________ 16-4
16.4. Operations______________________________________________________ 16-5
16.4.1. Initialization __________________________________________________________ 16-5
16.4.2. Data Transmission in Master Mode________________________________________ 16-5
16.4.3. Data Reception in Master Mode__________________________________________ 16-8
16.4.4. 10-bit Addressing in Master Mode _______________________________________ 16-11
16.4.5. Data Transmission in Slave Mode_________________________________________ 16-12
16.4.6. Data Reception in Slave Mode __________________________________________ 16-14
16.4.7. Slave Operations in 10-bit Address Mode __________________________________ 16-15
16.4.8. Automatic Bus Clearing Operation________________________________________ 16-16

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16.4.9. Error Detection_______________________________________________________ 16-17
16.5. Interrupts _____________________________________________________ 16-18
16.6. DMA Transfer Requests___________________________________________ 16-20
16.7. Control Registers ________________________________________________ 16-21
17. 16-bit PWM Timers (T16B) _______________________________________ 17-1
17.1. Overview _______________________________________________________ 17-1
17.2. Input/Output Pins________________________________________________ 17-2
17.3. Clock Settings ___________________________________________________ 17-3
17.3.1. T16B Operating Clock___________________________________________________ 17-3
17.3.2. Clock Supply in SLEEP Mode______________________________________________ 17-3
17.3.3. Clock Supply During Debugging ___________________________________________ 17-3
17.3.4. Event Counter Clock ____________________________________________________ 17-3
17.4. Operations ______________________________________________________ 17-4
17.4.1. Initialization ___________________________________________________________ 17-4
17.4.2. Counter Block Operations _______________________________________________ 17-5
17.4.3. Comparator/Capture Block Operations ____________________________________ 17-8
17.4.4. TOUT Output Control __________________________________________________ 17-18
17.5. Interrupt ______________________________________________________ 17-24
17.6. DMA Transfer Requests___________________________________________ 17-24
17.7. Control Registers ________________________________________________ 17-25
18. IR Remote Controller (REMC3) ____________________________________ 18-1
18.1. Overview _______________________________________________________ 18-1
18.2. Output Pins and External Connections ________________________________ 18-2
18.2.1. List of Output Pins _____________________________________________________ 18-2
18.2.2. ExternalConnections ___________________________________________________ 18-2
18.3. Clock Settings ___________________________________________________ 18-2
18.3.1. REMC3 Operating Clock_________________________________________________ 18-2
18.3.2. Clock Supply in SLEEP Mode______________________________________________ 18-2
18.3.3. Clock Supply During Debugging ___________________________________________ 18-3
18.4. Operations ______________________________________________________ 18-3
18.4.1. Initialization ___________________________________________________________ 18-3
18.4.2. Data Transmission Procedures ____________________________________________ 18-3
18.4.3. REMO Output Waveform________________________________________________ 18-4
18.4.4. Continuous Data Transmission and Compare Buffers __________________________ 18-6
18.5. Interrupts ______________________________________________________ 18-7
18.6. ApplicationExample:DrivingELLamp_________________________________ 18-7
18.7. Control Registers _________________________________________________ 18-8
19. 12-bitA/D Converter (ADC12A)____________________________________ 19-1
19.1. Overview _______________________________________________________ 19-1

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19.2. Input Pins and External Connections _________________________________ 19-2
19.2.1. List of Input Pins _______________________________________________________ 19-2
19.2.2. ExternalConnections ___________________________________________________ 19-2
19.3. Clock Settings ___________________________________________________ 19-2
19.3.1. ADC12A Operating Clock ________________________________________________ 19-2
19.3.2. Sampling Time ________________________________________________________ 19-3
19.4. Operations______________________________________________________ 19-3
19.4.1. Initialization __________________________________________________________ 19-3
19.4.2. Conversion Start Trigger Source ___________________________________________ 19-4
19.4.3. Conversion Mode and Analog Input Pin Settings______________________________ 19-4
19.4.4. A/D Conversion Operations and Control Procedures __________________________ 19-4
19.5. Interrupts ______________________________________________________ 19-7
19.6. DMA Transfer Requests____________________________________________ 19-7
19.7. Control Registers _________________________________________________ 19-8
20. R/F Converter (RFC)_____________________________________________ 20-1
20.1. Overview _______________________________________________________ 20-1
20.2. Input/Output Pins and External Connections __________________________ 20-2
20.2.1. List of Input/Output Pins ________________________________________________ 20-2
20.2.2. ExternalConnections ___________________________________________________ 20-2
20.3. Clock Settings ___________________________________________________ 20-3
20.3.1. RFC Operating Clock____________________________________________________ 20-3
20.3.2. Clock Supply in SLEEP Mode______________________________________________ 20-3
20.3.3. Clock Supply in DEBUG Mode ____________________________________________ 20-3
20.4. Operations ______________________________________________________ 20-4
20.4.1. Initialization ___________________________________________________________ 20-4
20.4.2. Operating Modes ______________________________________________________ 20-4
20.4.3. RFC Counters _________________________________________________________ 20-4
20.4.4. Converting Operations and Control Procedure _______________________________ 20-5
20.4.5. CR Oscillation Frequency Monitoring Function _______________________________ 20-7
20.5. Interrupts ______________________________________________________ 20-8
20.6. Control Registers _________________________________________________ 20-9
21. HW Processor(HWP)&Sound DAC(SDAC)____________________________ 21-1
21.1. Overview _______________________________________________________ 21-1
21.2. Input/Output Pins and External Connections __________________________ 21-2
21.2.1. List of Input/Output Pins ________________________________________________ 21-2
21.2.2. ExternalConnections ___________________________________________________ 21-2
21.3. Function Configulation Flow________________________________________ 21-3
21.4. Sound Play Function ______________________________________________ 21-4
21.4.1. Overall Flow __________________________________________________________ 21-4
21.4.2. Clock Setting__________________________________________________________ 21-5
21.4.3. Sound DAC and external Audio AMP Settings________________________________ 21-5
21.4.4. Sound Play State Transition ______________________________________________ 21-6
21.4.5. Sound Play Configuration________________________________________________ 21-8
21.4.6. Sound Start Command __________________________________________________ 21-9

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21.4.7. Sound Stop Command _________________________________________________ 21-10
21.4.8. Mute Command ______________________________________________________ 21-11
21.4.9. Release Mute Command _______________________________________________ 21-12
21.4.10. Pause Command ___________________________________________________ 21-14
21.4.11. Release Pause Command ____________________________________________ 21-15
21.4.12. Sound Play Error ___________________________________________________ 21-16
21.4.13. Sound Play Interrupt Masking_________________________________________ 21-16
21.4.14. Sound Play Function Registers ________________________________________ 21-17
21.4.15. Sound Flow Example ________________________________________________ 21-20
21.5. Memory Check Function__________________________________________ 21-25
21.5.1. Overall Flow _________________________________________________________ 21-25
21.5.2. Clock Setting_________________________________________________________ 21-25
21.5.3. Memory Check State Transition _________________________________________ 21-26
21.5.4. Memory Check Configuration ___________________________________________ 21-28
21.5.5. RAM Check R/W Start Command ________________________________________ 21-29
21.5.6. RAM Check March-C Start Command _____________________________________ 21-30
21.5.7. FLASH CHECKSUM Start Command _______________________________________ 21-31
21.5.8. FLASH CRC Start Command _____________________________________________ 21-32
21.5.9. Memory Check Error __________________________________________________ 21-33
21.5.10. Memory Check Interrupt Masking _____________________________________ 21-33
21.5.11. Memory Check Function Registers _____________________________________ 21-34
21.6. Control Registers ________________________________________________ 21-36
22. Peripheral Circuit Control Registers _________________________________ B-1
23. Electrical Characteristics_________________________________________ 23-1
23.1. Absolute Maximum Ratings ________________________________________ 23-1
23.2. Recommended Operating Conditions ________________________________ 23-1
23.3. Current Consumption _____________________________________________ 23-2
23.4. System Reset Controller (SRC) Characteristics __________________________ 23-5
23.5. Clock Generator (CLG) Characteristics ________________________________ 23-6
23.6. Flash Memory Characteristics_______________________________________ 23-9
23.7. Input/Output Port (PPORT) Characteristics ____________________________ 23-9
23.8. Supply Voltage Detector (SVD3) Characteristics________________________ 23-10
23.9. UART (UART3) Characteristics______________________________________ 23-12
23.10. Synchronous Serial Interface (SPIA) Characteristics_____________________ 23-13
23.11. Quad Synchronous Serial Interface (QSPI) Characteristics _________________ 23-15
23.12. I2C (I2C) Characteristics __________________________________________ 23-16
23.13. 12-bit A/D Converter (ADC12A) Characteristics _______________________ 23-17
23.14. R/F Converter (RFC) Characteristics _________________________________ 23-18
24. Basic External Connection Diagram ________________________________ 24-1
25. Package ______________________________________________________ 25-1

Seiko Epson Corporation
S1C31D50TECHNICAL MANUAL
(Rev. 1.00)
26. Appendix _____________________________________________________ 26-1

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Seiko Epson Corporation
S1C31D50TECHNICAL MANUAL
(Rev. 1.00)
1. Overview
1.1. Features
The S1C31D50 is a 32-bit ARM® Cortex®-M0+ MCU which integrates a specific hardware block called
the HW Processor. The HW Processor can perform 2ch Voice/Audio Play, Voice Speed Conversion, and
Self Memory Check without using any CPU resource. The S1C31D50 is suitable for home electronics,
white goods, and battery-based products which require voice and audio playback.
With the HW Processor, low memory footprint and multi-language support are achievable because of
its integrated high-compression algorithm for voice and audio.
Table 1.1.1 Features
Model S1C31D50
CPU
CPU core
ARM® 32-bit RISC CPU core Cortex®-M0+
Other
Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included
Embedded Flash memory
Capacity
192K bytes (for both instructions and data)
Erase/program count
1,000 times (min.) * When being programmed by the dedicated flash loader
Other
On-board programming function
Flash programming voltage can be generated internally.
Embedded RAMs
General-purpose RAM
8K bytes + 14K bytes (when HW Processor is not active)
Instruction cache
512 bytes
HW Processor
Sound Play FUNCTION
Sound Algorithm
EPSON high quality & High compress algorithm
Playchannels
2ch mixing support(suitable for background music + Voice play
Sampling Frequency
15.625kHz, (suitable for background music + Voice play)
Bitrate
16/24/32/40 kbps
Voice Speed Conversion
75% - 125% (5% step)
Self Memory Check FUNCTION
On Chip RAM Check
W/R Check, MARCH-C
On Chip Flash check
Checksum, CRC
External SPI-Flash Check
Checksum, CRC
Sound DAC
Sampling Frequency
15.625kHz
Serial interfaces
UART (UART3)
3 channels
Baud-rate generator included, IrDA1.0 supported
Open drain output, signal polarity, and baud rate division ratio are configurable.
Infrared communication carrier modulation output function
Synchronous serial interface (SPIA)
3 channels
2 to 16-bit variable data length
The 16-bit timer (T16) can be used for the baud-rate generator in master mode.
Quad synchronous serial interface (QSPI)
1 channel
Supports single, dual, and quad transfer modes.
Low CPU overhead memory mapped access mode that can directly read data from
the external flash memory with XIP (eXecute-In-Place) mode.
I
2
C (I2C)
3 channels
Baud-rate generator included
DMA Controller (DMAC)
Number of channels
4 channels
Data transfer path
Memory to memory, memory to peripheral, and peripheral to memory
Transfer mode
Basic, ping-pong, scatter-gather
DMA trigger source
UART3, SPIA, QSPI, I2C, T16B, ADC12A, and software

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S1C31D50TECHNICAL MANUAL
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Clock generator (CLG)
System clock source
4 sources (IOSC/OSC1/OSC3/EXOSC)
System clock frequency (operating
frequency)
VD1 voltage mode = mode0: 16 MHz (max.)
VD1 voltage mode = mode1: 1.8 MHz (max.)
IOSC oscillator circuit (boot clock
source)
VD1 voltage mode = mode0: 8/2/1 MHz (typ.) software selectable
VD1 voltage mode = mode1: 1.8/0.9 MHz (typ.) software selectable
10 µs (typ.) starting time (time from cancelation of SLEEP state to vector table read
by the CPU)
OSC1 oscillator circuit
32.768 kHz (typ.) crystal oscillator
32kHz (typ.) embedded oscillator
Oscillation stop detection circuit included
OSC3 oscillator circuit
16 MHz (max.) crystal/ceramic oscillator
16/8/4MHz(typ) embedded oscillator
EXOSC clock input
16 MHz (max.) square or sine wave input
Other
Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
I/O port (PPORT)
Number of general-purpose I/O ports
PKG48pin : 39bits(max.)
PKG64pin : 55bits(max.)
PKG80pin : 71bits(max.)
PKG100pin : 91bits(max.)
Pins are shared with the peripheral I/O.
Number of input interrupt ports
PKG48pin : 33bits(max.)
PKG64pin : 49bits(max.)
PKG80pin : 65bits(max.)
PKG100pin : 85bits(max.)
Number of ports that support
universal port multiplexer(UPMUX)
PKG48pin : 16bits(max.)
PKG64pin : 24bits(max.)
PKG80pin : 27bits(max.)
PKG100pin : 32bits(max.)
A peripheral circuit I/O function selected via software can be assigned to each port.
Timers
Watchdog timer (WDT2)
Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
Real-time clock (RTCA)
128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
16-bit timer (T16)
8 channels
Generates the SPIA and QSPI master clocks, and the ADC12A operating clock/
trigger signal.
16-bit PWM timer (T16B)
2 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 4 ports/channel
Supply voltage detector (SVD3)
Number of channels
1 channel
Detection voltage
VDD or an external voltage (2 external detection ports are available.)
Detection level
VDD: 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
Other
Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
12-bit A/D converter (ADC12A)
Conversion method
Successive approximation type
Resolution
12 bits
Number of conversion channels
1 channel
Number of analog signal inputs
8 ports/channel (max)
R/F converter（RFC）
Conversion method
CR oscillation type 24-bit counters
Number of conversion channels
1 channel
Supported sensors
DC bias resistive sensors
IR remote controller (REMC3)
Number of transmitter channels
1 channel
Other
EL lamp drive waveform can be generated (by the hardware) for an application
ex- ample.
Output inversion function
Reset
#RESET pin
Reset when the reset pin is set to low.
Power-on reset
Reset at power on.
Brown-out reset
Reset when the power supply voltage drops (when VDD ≤1.45 V (typ.) is detected).
Watchdog timer reset
Reset when the watchdog timer overflows (can be enabled/disabled using a
register).
Supply voltage detector reset
Reset when the supply voltage detector detects the set voltage level (can be
enabled/ disabled using a register).
Interrupt
Non-maskable interrupt
6 systems (Reset, NMI, HardFault, SVCall, PendSV, SysTic)
Programmable interrupt
External interrupt: 3 systems
Internal interrupt: 27 systems

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S1C31D50TECHNICAL MANUAL
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Power supply voltage
VDD operating voltage
1.8 to 5.5 V * If VDD > 3.6 V, the VD1 voltage mode must be mode0.
VDD operating voltage for Flash
programming
2.4 to 5.5 V (when VPP is supplied externally)
2.7 to 5.5 V (when VPP is generated internally)
SPI-Flash interface power supply
VDDQSPI
3.0 to 3.6V（possible to set main VDD:5v, SPI-Flash power supply :3.3v）
Operating temperature
Operating temperature range
-40 to 85 °C
Current consumption (Typ. value)
SLEEPmode
*1
0.46 µA
IOSC = OFF, OSC1 = OFF, OSC3 = OFF
0.95 µA
IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF, RTCA = ON
HALT mode *2
1.8 µA
IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = OFF
RUN mode
250 µA/MHz
VD1 voltage mode = mode0, CPU = IOSC
155 µA/MHz
VD1 voltage mode = mode1, CPU = IOSC
Shipping form
1
TQFP12-48 ( 7mm x 7mm, 0.5mm pitch)
2
QFP13-64 (10mm x 10mm, 0.5mm pitch)
3
TQFP14-80 (12mm x 12mm, 0.5mm pitch)
4
QFP15-100 (14mm x 14mm, 0.5mm pitch)
*1 SLEEP mode refers to deep sleep mode in the Cortex®-M0+ processor.
*2 HALT mode refers to sleep mode in the Cortex®-M0+ processor.

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S1C31D50TECHNICAL MANUAL
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1.2. Block Diagram
Figure 1.2.1 S1C31D50 Block Diagram
CPU core, Interrupt
controller, and debugger
(Cortex-M0+)
SWCLK
SWD
Flash memory
192K bytes
MTB
RAM
8K bytes
DMA
controller
4 Ch.
Synchronous
serial
interface
(SPIA) 3 Ch.
I2C
(I2C) 3 Ch.
HW Processor
I/O port01
(PPORT)
Watchdog
timer
(WDT2)
Real-time
clock
(RTCA)
Supply
voltage
detector
(SVD3) 1 Ch.
16-bit timer
(T16) 8Ch.
16-bit PWM
timer
(T16B) 2 Ch.
UART
(UART3) 3 Ch.
Clock
generator
(CLG)
IOSC
oscillator
OSC1
oscillator
OSC3
oscillator
EXOSC
oscillator
System reset
controller
(SRC)
Power-on
reset/
Brown-out
reset
(POR/BOR)
Power generator
(PWGA)
System clock
Interrupt signal
DMA request
Cache
controller
Cache RAM
512 bytes
12bit A/D
convertor
(ADC12A) 1
Ch.
ADIN00-07
I/O port23
(PPORT)
I/O
portOthers
(PPORT)
VREFA0
#RESET
EXCL00-01
CAP10-13
SDACOUT_P
SDACOUT_N
P00-07
P10-17
#ADTRG
QSDIO00-03
QSPICLK0
#QSPISS0
SDI0-2
SDO0-2
SPICLK0-2
USIN0-2
#SPISS0-2
SDA0-2
SCL0-2
USOUT0-2
P20-27
P30-37
P40-47
P50-57
P60-67
P70-77
P80-87
P90-95
PA0-A6
VDD
VSS
VDDQSPI
Vpp
RAM
14K bytes
Sound_DAC
1 Ch.
EXSVD0-1
IR remote
controller
(REMC3)
1Ch.
REMO
CLPLS
EXCL10-11
R/F converter
(RFC) 1 Ch.
SENB0
REF0
RFCLKO0
RFIN0
SENA0
TOUT10-13
Quad
synchronous
serial
interface
(QSPI) 1 Ch.
CAP00-03
TOUT00-03
16-bit peripheral bus
32-bit AHB bus
PD0-D5
RTC1S
FOUT
OSC1
OSC2
OSC3
OSC4
EXOSC

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S1C31D50TECHNICAL MANUAL
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1.3. Pins
1.3.1. Pin Configuration Diagram
TQFP12-48
VSS
VD1
PD3/OSC4
PD2/OSC3
SDACOUT_N/P51
SDACOUT_P/P50
P23/RFIN0/UPMUX
P22/REF0/UPMUX
P21/SENA0/UPMUX
P20/SENB0/UPMUX
P62/EXSVD1
P61/EXSVD0
36 35 34 33 32 31 30 29 28 27 26 25
#RESET 37 24 P46/RTC1S
VDD 38 23 P45/#ADTRG
OSC1 39 22 P40/VREFA
OSC2 40 21 P17/UPMUX/ADIN0
P83/EXOSC 41 20 P16/UPMUX/ADIN1
P84/EXCL00 42 19 P15/UPMUX/ADIN2
P85/EXCL01 43 18 P14/UPMUX/ADIN3
P72/EXCL10 44 17 P13/UPMUX/ADIN4
P73/EXCL11 45 16 P06/UPMUX
SWCLK/PD0 46 15 P05/UPMUX
SWD/PD1 47 14 P04/UPMUX
TEST 48 13 P03/UPMUX
1 2 3 4 5 6 7 8 9 10 11 12
P30/RFCLKO0/UPMUX
P31/REMO/UPMUX
P32/CLPLS/UPMUX
VPP
P90/QSPICLK0
P91/QSDIO00
P92/QSDIO01
P93/QSDIO02
P94/QSDIO03
P95/#QSPISS0
VDDQSPI
PA3/FOUT
TQFP12-48
Figure 1.3.1.1 S1C31D50 Pin Configuration Diagram (TQFP12-48)

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S1C31D50TECHNICAL MANUAL
(Rev. 1.00)
QFP13-64
VSS
VD1
PD3/OSC4
PD2/OSC3
SDACOUT_N/P51
SDACOUT_P/P50
P27/UPMUX
P26/UPMUX
P25/UPMUX
P24/UPMUX
P23/RFIN0/UPMUX
P22/REF0/UPMUX
P21/SENA0/UPMUX
P20/SENB0/UPMUX
P62/EXSVD1
P61/EXSVD0
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
#RESET 49 32 P46/RTC1S
VDD 50 31 P45/#ADTRG
OSC1 51 30 P44
OSC2 52 29 P43
P81 53 28 P40/VREFA
P82 54 27 P17/UPMUX/ADIN0
P83/EXOSC 55 26 P16/UPMUX/ADIN1
P84/EXCL00 56 25 P15/UPMUX/ADIN2
P85/EXCL01 57 24 P14/UPMUX/ADIN3
P70 58 23 P13/UPMUX/ADIN4
P71 59 22 P12/UPMUX/ADIN5
P72/EXCL10 60 21 P11/UPMUX/ADIN6
P73/EXCL11 61 20 P06/UPMUX
SWCLK/PD0 62 19 P05/UPMUX
SWD/PD1 63 18 P04/UPMUX
TEST 64 17 P03/UPMUX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P30/RFCLKO0/UPMUX
P31/REMO/UPMUX
P32/CLPLS/UPMUX
P33/UPMUX
P34/UPMUX
VPP
P90/QSPICLK0
P91/QSDIO00
P92/QSDIO01
P93/QSDIO02
P94/QSDIO03
P95/#QSPISS0
VDDQSPI
PA1
PA2
PA3/FOUT
QFP13-64
Figure 1.3.1.2 S1C31D50 Pin Configuration Diagram (QFP13-64)

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TQFP14-80pin
VSS
VD1
PD3/OSC4
PD2/OSC3
P53
P52
SDACOUT_N/P51
SDACOUT_P/P50
P27/UPMUX
P26/UPMUX
P25/UPMUX
P24/UPMUX
P23/RFIN0/UPMUX
P22/REF0/UPMUX
P21/SENA0/UPMUX
P20/SENB0/UPMUX
P64
P63
P62/EXSVD1
P61/EXSVD0
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
#RESET 61 40 P46/RTC1S
VDD 62 39 P45/#ADTRG
OSC1 63 38 P44
OSC2 64 37 P43
P80 65 36 P42
P81 66 35 P41
P82 67 34 P40/VREFA
P83/EXOSC 68 33 P17/UPMUX/ADIN0
P84/EXCL00 69 32 P16/UPMUX/ADIN1
P85/EXCL01 70 31 P15/UPMUX/ADIN2
P86 71 30 P14/UPMUX/ADIN3
P87 72 29 P13/UPMUX/ADIN4
P70 73 28 P12/UPMUX/ADIN5
P71 74 27 P11/UPMUX/ADIN6
P72/EXCL10 75 26 P10/UPMUX/ADIN7
P73/EXCL11 76 25 P07/UPMUX
P74 77 24 P06/UPMUX
SWCLK/PD0 78 23 P05/UPMUX
SWD/PD1 79 22 P04/UPMUX
TEST 80 21 P03/UPMUX
12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PD4
P30/RFCLKO0/UPMUX
P31/REMO/UPMUX
P32/CLPLS/UPMUX
P33/UPMUX
P34/UPMUX
P35/UPMUX
VPP
P90/QSPICLK0
P91/QSDIO00
P92/QSDIO01
P93/QSDIO02
P94/QSDIO03
P95/#QSPISS0
VDDQSPI
PA0
PA1
PA2
PA3/FOUT
PA4
TQFP14-80
Figure 1.3.1.3 S1C31D50 Pin Configuration Diagram (TQFP14-80)