ADLINK Technology cPCI-6840 Series User manual

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Advance Technologies; Automate the World.
Manual Rev. 2.20
Revision Date: August 5, 2008
Part No: 50-15031-2030
cPCI-6840 Series
6U CompactPCI Pentium M
Single Board Computer
User’s Manual
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Revision History
Revision Release Date Description of Change(s)
2.00 2005/01/19 Initial Release
2.10 2005/06/15 Correct specification errors, typos
2.20 2008/08/05 Update CPU support, GbE Controller version, Baseboard Management Controller, add
cPCI-R6841P, IPMI instructions
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Preface iii
cPCI-6840
Preface
Copyright 2008 ADLINK Technology Inc.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.In no
event will the manufacturer be liable for direct, indirect, special,
incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global
environmental preservation through compliance with the Euro-
pean Union's Restriction of Hazardous Substances (RoHS) direc-
tive and Waste Electrical and Electronic Equipment (WEEE)
directive. Environmental protection is a top priority for ADLINK.
We have enforced measures to ensure that our products, manu-
facturing processes, components, and raw materials have as little
impact on the environment as possible. When products are at their
end of life, our customers are encouraged to dispose of them in
accordance with the product disposal and/or recovery programs
prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.
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iv Preface
Using this Manual
Audience and Scope
The cPCI-6840 User’s Manual is intended for hardware
technicians and systems operators with knowledge of installing,
configuring and operating industrial grade CompactPCI modules.
Manual Organization
This manual is organized as follows:
Chapter 1, Introduction: Introduces the cPCI-6840, its
specifications, features, and package contents.
Chapter 2, Jumpers and Connectors: Presents the board
layout, connector pin assignments, and jumper setup.
Chapter 3, Getting Started: Explains how to install necessary
components on the cPCI-6840.
Chapter 4, Windows Driver Installation: Describes the
driver installation procedures.
Chapter 5, Utilities: Describes the operation of the
cPCI-6840’s watchdog timer and PXE Environment.
Chapter 6, IPMI User Guide: Describes the Intelligent
Platform Management Interface.
Important Safety Instructions: Presents safety instructions
all users must follow for the proper setup, installation and
usage of equipment and/or software.
Getting Service: Contact information for ADLINK’s worldwide
offices.
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Preface v
cPCI-6840
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
NOTE:
NOTE:
Additional information, aids, and tips that help users per-
form tasks.
CAUTION:
Information to prevent minor physical injury, component
damage, data loss, and/or program corruption when try-
ing to complete a task.
WARNING:
Information to prevent serious physical injury, compo-
nent damage, data loss, and/or program corruption
when trying to complete a specific task.
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vi Preface
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Table of Contents vii
cPCI-6840
Table of Contents
Revision History...................................................................... ii
Preface.................................................................................... iii
Table of Contents.................................................................. vii
List of Tables.......................................................................... ix
List of Figures........................................................................ xi
1 Introduction ........................................................................ 1
1.1 Main Functions .................................................................... 3
1.2 Features............................................................................... 8
1.3 Product List.......................................................................... 9
1.4 Specifications..................................................................... 11
1.5 Unpacking Checklist .......................................................... 18
2 Jumpers and Connectors................................................ 19
2.1 cPCI-6840 and cPCI-6840V Board Outline ....................... 20
2.2 cPCI-6840/V Connector Pin Assignments......................... 22
2.3 cPCI-6840/V Switch and Jumper Settings......................... 34
2.4 RTM Board Outline............................................................ 36
2.5 RTM Connectors Pin Assignments.................................... 38
2.6 RTM Switch and Jumper Setting....................................... 45
3 Getting Started ................................................................. 47
3.1 CPU and Heatsink ............................................................. 48
3.2 Memory Module Installation............................................... 49
3.3 HDD Installation on Main Board – for cPCI-6840.............. 50
3.4 HDD Installation on Main Board – for cPCI-6840V............ 52
3.5 HDD Installation on RTM................................................... 54
3.6 CF Installation on RTM...................................................... 54
3.7 PCI Mezzanine Card (PMC) Installation............................ 54
3.8 RTM Installation................................................................. 55
3.9 Main Board Installation ..................................................... 55
4 Windows Driver Installation............................................ 57
4.1 Chipset Drivers Installation................................................ 57
4.2 VGA Driver Installation ...................................................... 58
4.3 LAN Driver Installation....................................................... 58
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viii Table of Contents
5 Utilities............................................................................... 59
5.1 Watchdog Timer................................................................. 59
5.2 Intel Preboot Execution Environment (PXE)...................... 64
6 IPMI User Guide ................................................................ 65
6.1 Introduction........................................................................ 65
6.2 Summary of Commands Supported by BMR-AVR-cPCI... 65
6.3 OEM Commands Summary Table..................................... 67
6.4 CompactPCI Address Map ................................................ 71
6.5 IPMI Sensors List............................................................... 71
6.6 Known Issues..................................................................... 72
6.7 Relevant Documents.......................................................... 72
Important Safety Instructions............................................... 73
Getting Service...................................................................... 75
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List of Tables ix
cPCI-6840
List of Tables
Table 1-1: cPCI-6840 Configurations ........................................ 9
Table 1-2: Power Ratings ........................................................ 14
Table 1-3: I/O Connectivity Table ............................................ 17
Table 2-1: Ethernet LED Status ............................................... 22
Table 2-2: Switch and Jumper Functions ................................ 34
Table 2-3: JP1 Settings ........................................................... 34
Table 2-4: JP3 Settings ........................................................... 35
Table 2-5: RTM Switch and Jumper Settings .......................... 45
Table 2-6: LAN Dip Switch Settings ......................................... 45
Table 2-7: CF Master/Slave Jumper Settings .......................... 46
Table 2-8: cPCI-R6841(P) Switch Settings .............................. 46
Table 2-9: JP3 Settings ........................................................... 46
Table 3-1: DDR SDRAM Memory Capacity ............................. 49
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xListofTables
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List of Figures xi
cPCI-6840
List of Figures
Figure 1-1: cPCI-6840 Block Diagram ......................................... 2
Figure 2-1: cPCI-6840 Front and Top View ............................... 20
Figure 2-2: cPCI-6840V Front and Top View............................. 21
Figure 2-3: cPCI-R6840 Board Layout....................................... 36
Figure 2-4: cPCI-R6841P Diagram............................................ 37
Figure 3-1: Heatsink installation................................................. 48
Figure 3-2: cPCI-6840 2.5” Hard Disk Installation ..................... 51
Figure 3-3: cPCI-6840V 2.5” Hard Disk Installation................... 53
Figure 5-1: WDT Block Diagram................................................ 59
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xii List of Figures
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Introduction 1
cPCI-6840
1 Introduction
The cPCI-6840 is a 6U CompactPCI single board computer based
on Intel® Pentium® M processor, 855GME and 6300ESB chipset.
The Pentium® M processor comes with 1MB L2 cache in FC-
mPGA package. The operating frequency ranges from 1.3GHz up
to 1.6GHz. The cPCI-6840 is designed to be forward compatible
with future 1.7GHz or higher speed Pentium® M compatible pro-
cessor. The combination of the longevity of the Intel® 855GME
and 6300ESB chipset and low power consumption of the Pen-
tium® M CPU make the cPCI-6840 the best solution for embed-
ded applications.
The 855GME supports 400MHz FSB and DDR333 memory up to
2GB. Two 200 pins SO-DIMM sockets support up to a maximum
2GB DIMM with 144-bit wide PC2700 registered DDR memory. A
32-bit 3D graphic controller is integrated to provide analog VGA or
LVDS output.
The low power consumption 6300ESB south bridge provides dual
PCI buses (PCI 64 bit/66-MHz and 32-bit/33MHz) to maximize I/O
bandwidth. The I/O features are highly integrated, including four
USB 2.0 port, two UART, two E-IDE channels, two Serial ATA
ports, and a watchdog timer.
The 6300ESB’s PCI 64 bit/66 MHz bus connects to two PMC
sites, a dual port GbE controller 82546GB, and the universal PCI-
to-PCI bridge PLX PCI-6540. The two 64-bit/66MHz PMC sites
provide extreme expansion capability and flexibility for varieties of
applications. The upper PMC site provides the rear I/O (Jn4 of
PMC) capability for either SCSI PMC or telecom PMC modules.
The CompactPCI bus is based on the universal PCI-to-PCI bridge
chip PCI-6540 (made by PLX Technology), providing either a
transparent or non-transparent PCI interface. cPCI-6840 can be
used as either a system slot or peripheral slot. cPCI-6840 can also
be a server blade for stand alone operation on any non-system
slot (without PCI bus). The cPCI-6840 is hot-swappable on periph-
eral slot or non-PCI bus slot which provide the best MTTR perfor-
mance for telecom applications.
The cPCI-6840 is equipped with three Gigabit Ethernet (GbE)
ports. Two GbE ports use the 82546GB dual ports GbE controllers
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2Introduction
on the 66MHz PCI bus to achieve the full communication band-
width between the LAN and CPU. These two ports are connected
to J3 (or rear I/O) which conform to the PICMG 2.16 specification.
The third LAN port uses a 82541PI GbE controller on the 32-
bit/33MHz PCI bus.
A Management Controller (BMC) (which follows the Intelligent
Platform Management Interface (IPMI) v1.0 specification), is built
into the system to meet the demands of high reliability and ser-
viceability.
Please refer to the following block diagram for the cPCI-6840
architecture.
Figure 1-1: cPCI-6840 Block Diagram
CPU
PENTIUM M
SOUTH BRIDGE
HANCE RAPIDS
6300ESB
NORTH
BRIDGE
855GME
DDR SODIMM x2
TOTAL MAX 2GB
J3
RGB DB-15
OUTPUT
GIGA LAN
82546
DUAL PORT
Upper
PMC Lower
PMC
UNIVERSAL
BRIDGE
PLX PCI6540
J5
J3
PIM
or
RIO
PICMG 2.16
OR
REAR IO
GIGA LAN
82541
SINGLE PORT
BMC FWH
CPCI
BACKPLANE
J3USB2.0 2/3
USB2.0 0/1
SIDE J5
PIDE
SATA J5
SERIAL
PORT 1 SERIAL PORT 0
J5
PSB
100MHz
4x
DDR 100MHz 2x
SINGLE CHANNEL
HI1.5
66MHz
4x PCI
33MHz/32bits
PCI
66MHz/64bits
PCI
66/64
GIGA
LAN
PMC
REAR IO
LPC
33MHz/4bits
SERIAL
PORT
SERIAL
ATA
UATA
100
USB
2.0
RGB
RGB DB-15
OUTPUT
J3
LVDS A
LVDS A
CHRONTEL
CH7301A-T
DVO TO DVI
J3
TMDS
CONNECTOR
DVO C
SIO
W83627HG
J3
KBMS
KBMS
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Introduction 3
cPCI-6840
1.1 Main Functions
The following sections explain the main functions on cPCI-6840
CPU Support
The cPCI-6840 SBC is designed for the Intel® Pentium® M and
Celeron® M Processors. The standard cPCI-6840 SBC comes
with CPU socket which can be installed with μFC-PGA2 package
CPU, with the following options:
XPentium® M 1.3GHz, 1.4GHz, 1.5GHz, 1.6GHz, 1.7GHz,
1.8GHz, and 2.0GHz
XCeleron® M 1.3GHz
The Low Voltage (LV) or Ultra Low Voltage (ULV) version of the
Pentium® M or Celeron® M Processors, which are in μFCBGA2
packages, can also be mounted on the cPCI-6840 SBC. However,
μFCBGA2 CPU support is reserved for OEM programs only. The
possible CPU options include:
XLV Pentium® M 1.1, 1.2, 1.3GHz
XULV Celeron® M 600MHz
CompactPCI Bus Interface
The PLX Technology PCI-6540 is a tri-mode universal PCI-to-PCI
Bridge and is used to implement the system/peripheral slot on the
cPCI-6840. The tri-mode bridge is capable of operating in Trans-
parent, Non-Transparent or Universal mode. The PCI-6540 Non-
Transparent mode permits independent memory mapping of both
primary and secondary buses with powerful configuration options
to support intelligent subsystems. The Universal mode permits
jumper-less configuration between application to CompactPCI
interface at Peripheral Slot and System Slot. With the Universal
option, the PCI-6540 Bridge can be configured as a transparent
bridge in a System Slot supporting a host, or as a Non-Transpar-
ent bridge in a Peripheral Slot as an intelligent subsystem. These
options allow the cPCI-6840 board to be inserted into both the
Peripheral Slot and the System Slot.
The cPCI-6840 CompactPCI bus supports up to 64 bit/66 MHz
PCI, as well as allowing the host bus and subsystem bus to
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4Introduction
operate at different speeds. Together with 64-bit to 32-bit access
conversion, system architects can utilize the bridge and connect
slower or higher speed controllers on primary or secondary bus,
hence supporting independent speed and data bus frequency on
either side of the PCI bus. The 64-bit/66 MHz PCI bus is backward
compatible with 64-bit/33 MHz PCI, 32-bit/66 MHz PCI and 32-
bit/33 MHz PCI busses. The SBC design is compliant with the
PICMG 2.1 hot-swap specification so it can be hot-swappable in
the peripheral slots. The cPCI-6840 can also be a hot-swappable
server blade for stand alone operation on any non-PCI backplane
without a system slot.
PCI Mezzanine Card (PMC) Interface
The cPCI-6840 supports up to two PMC slots at 64-bit/66 MHz
PCI, providing expansion capability and flexibility for varieties of
applications. The Jn4 rear I/O of the upper PMC site (PMC2) are
implemented by connecting to the CompactPCI J5 connector,
which complies with the PICMG 2.3 specification.
When the ADLINK SCSI PMC module (PMC-8631) is installed in
PMC2 along with the cPCI-R6840 RTM, it can provide SCSI-320
interfaces on the rear panel of the Rear I/O Transition Module
(RTM) for external storage devices. Some telecom PMC modules
may also utilize the J24 rear I/O connection and the PMC Interface
Module (PIM) site on the RTM to provide telecom I/O connection
on the rear panel. The cPCI-R6841P RTM provides a PIM site.
IDE Interfaces
The cPCI-6840 supports dual Ultra ATA100 IDE channels. Primary
IDE is implemented on the cPCI-6840 and Secondary IDE is
routed to the RTM via J5 connector. Two 44-pin connectors for 2.5
inches IDE drives are reserved on both Primary and Secondary
IDE interfaces.
The space of lower PMC site (PMC1) shall be used for installing
the 2.5 inches IDE HDD, flash disk, or a CompactFlash carrier
baord, DB-6840CF. When an application installs a storage device
on the SBC, the PMC1 is occupied. Also note that the PMC1 con-
nectors are not available on the cPCI-6840V because its front
panel is occupied by VGA and PS2 keyboard/mouse connectors.
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Introduction 5
cPCI-6840
On the RTM, the Secondary IDE is implemented on a Compact-
Flash socket and a 44-pin connectors for 2.5 inches IDE drive.
Gigabit Ethernet Ports
The cPCI-6840 has three 10/100/1000Mbps Ethernet (GbE) ports.
Every port is assigned a unique static MAC Address.
The onboard Intel® 82546GB dual-port Gigabit Ethernet controller
provides two Ethernet ports. The 82546GB is connected to the 64-
bit/66 MHz PCI bus to achieve the full communications bandwidth.
The 82546GB supports IEEE 802.3x compliant flow control and
IEEE 802.3ab compliant 10/100/1000 Mbps auto-negotiation. The
two GbE ports are connected to J3 based on PICMG 2.16 specifi-
cations.
The third LAN port uses a 82541PI controller on the 32-bit/33 MHz
PCI bus. The RJ-45 connector of the third LAN port is on the front
panel for system management or serviceability requirement. Users
can disable or enable the third LAN port from the BIOS menu.
Universal Serial Bus (USB)
The cPCI-6840 provides four USB version 2.0 ports. Two ports are
on the front panel and another two ports are on the RTM. The Uni-
versal Serial Bus (USB) provides a common interface to versatile
peripheralssuch as keyboard,mouse, printer, USB flash disk, etc.
Serial I/O
Two serial ports are supported on cPCI-6840. COM1 is available
as a RJ45 connector on the front panel. COM2 is also a standard
RJ-45 connector on the rear panel of RTM. Both ports are be con-
figured as Data Terminal Equipment (DTE). Firmware initializes
the two serial ports as COM1 and COM2 with ISA I/O base
addresses of 3F8h and 2F8h respectively. This default configura-
tion also assigns COM1 to IRQ4 and COM2 to IRQ3. Optional
COM3 and COM4 ports are available for ODM/OEM projects via
the Winbond 83627HG. COM3 may be accessed via a cable, how-
ever COM4 may require a custom RTM.
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6Introduction
Keyboard/Mouse Controller
The cPCI-6840 uses a Winbond W83627HG to implement the
keyboard/mouse controller. The controller is fully 8042 compatible.
The cPCI-6840V provides a combo PS2 connector on the front
panel. Both cPCI-6840 and 6840V route the keyboard and mouse
signals to the J3.
Power Ramp Circuitry
The cPCI-6840 features a power controller with power ramp cir-
cuitry to allow the board's voltages to be ramped in a controlled
fashion. The power ramp circuitry eliminates any large voltage or
current spikes caused by hot-swapping boards. This controlled
ramping is a requirement of the CompactPCI hot-swap specifica-
tion, PICMG 2.1 Version 1.0. The cPCI-6840's power controller
unconditionally resets the board when it detects that the 3.3V, 5V,
and 12V supplies are below an acceptable operating limit. These
limits are defined as 4.75V (5V supply), 3.0V (3.3V supply), and
10.0V (+12V supply).
Watchdog Timer
Application can utilize watchdog timer to monitor system operation
and to recover the operation when an abnormal and unexpected
occurrence arises. The timeout period of the watchdog timer can
be programmed from one micro second to ten minutes. Failure to
strobe the watchdog timer within the programmed time period may
result in an interrupt or reset request. A register bit can be enabled
to indicate if the watchdog timer caused the interrupt or reset
event. This watchdog timer register can be cleared by the system
or auto-cleared after power-up, enabling system software to take
appropriate action if the watchdog generated the reboot. Please
refer Chapter 5, "Watchdog Timer," for more information.
Hardware Monitoring
The cPCI-6840 series use Winbond W83627HG to detect system
voltages and temperatures. When it detects the voltages or tem-
peratures over the safety range, it will inform the south bridge
6300ESB to send the signals out halting the system in order to
protect the CPU board.
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Introduction 7
cPCI-6840
Operating System Support
The cPCI-6840 is compatible with Microsoft® Windows 2000, Win-
dows 2003 Server, Windows XP, Red Hat Linux 9 and VxWorks
5.5. The device drivers for Windows are included in the ADLINK
CD. For Linux support and VxWork BSP, please contact ADLINK.
Baseboard Management
A baseboard management controller is implemented such that the
system manager can control or get status form cPCI-6840 through
the Intelligent Platform Management Bus (IPMB). The firmware is
based on the Intelligent Platform Management Interface (IPMI)
specification version 1.5. Please refer to Chapter 6 for the IPMI
User Guide.
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