Nvidia Jetson AGX Orin Series Installation and operating manual

DA-11040-001_v0.7 |July 2022
PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and
Compliance Guide
Application Note

PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and Compliance Guide DA-11040-001_v0.7 | ii
Document History
DA-11040-001_v0.7
Version Date Description of Change
0.7 July 29, 2022 Preliminary release

PRELIMINARY INFORMATION
Jetson AGX Orin Series Tuning and Compliance Guide DA-11040-001_v0.7 | iii
Table of Contents
USB 2.0 Tuning Guide ................................................................................................1
Required Equipment .................................................................................................................... 1
Host Mode Testing Registers ...................................................................................................... 1
Test Mode Programming Sequence............................................................................................ 2
USB 2.0 Eye Diagram Registers.................................................................................................. 3
Tuning Procedure and Registers ................................................................................................ 4
HS_CURR_LEVEL Offset Adjustment Procedure ................................................................... 5
Software Verification.................................................................................................................... 6
USB 3.2 Compliance Test Guide.................................................................................7
Compliance Testing...................................................................................................................... 7
USB 3.2 TX and RX Compliance Tests......................................................................................... 7
Putting the Orin module USB 3.2 Controller in Compliance Mode ....................................... 8
Putting the Orin module USB 3.2 Controller in Loop-Back Mode......................................... 9
PCIe Compliance Testing Reference........................................................................10
References.................................................................................................................................. 10
Patch Attachments..................................................................................................................... 11
Electrical Characterization........................................................................................................ 11
Prerequisites .......................................................................................................................... 11
De-Embedding or Device Removal.................................................................................... 11
Mid-Bus Probing................................................................................................................. 12
Oscilloscopes.......................................................................................................................... 12
BERT........................................................................................................................................ 12
Cables...................................................................................................................................... 13
Probes ..................................................................................................................................... 13
Mode Pulse Generation.......................................................................................................... 13
Breakout Boards .................................................................................................................... 14
Software .................................................................................................................................. 15
Setup and Characterization ....................................................................................................... 15
DUT Setup ............................................................................................................................... 15
Breakout Boards .................................................................................................................... 16
REFCLK Measurement and Characterization....................................................................... 16
REFCLK Measurement Probe Selection ........................................................................... 17
Single-Ended REFCLK AC Measurements........................................................................ 17
General Setup Considerations ....................................................................................... 18
Rise-Fall Matching ......................................................................................................... 18
Vmax and Vmin................................................................................................................ 19

PRELIMINARY INFORMATION
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Vcross Max, Min, Delta using Manual Approach........................................................... 19
Vcross Max, Min, Delta with Jitter Application Software.............................................. 19
Differential REFCLK AC Measurements ........................................................................... 19
Edge Rate Max and Min, Falling and Rising.................................................................. 19
Vih, Vil, Tperiod, % Duty Cycle........................................................................................ 20
Tstable............................................................................................................................. 20
Tx Characterization DUT Test Setup ..................................................................................... 20
Tx Test ................................................................................................................................. 22
Rx DUT Test Setup.................................................................................................................. 24
Rx Tests............................................................................................................................... 24
Protocol-aware BERT..................................................................................................... 24
HDMI Tuning Guide ..................................................................................................25
Abbreviations and Definitions.................................................................................................... 25
Required Equipment .................................................................................................................. 26
Test Fixture ............................................................................................................................. 26
Oscilloscope............................................................................................................................ 27
Probes ..................................................................................................................................... 28
DC Power Supply.................................................................................................................... 30
Software...................................................................................................................................... 30
Compliance Test Software..................................................................................................... 30
Software Tools........................................................................................................................ 31
Method for Tuning ...................................................................................................................... 31
Procedures.............................................................................................................................. 31
DUT...................................................................................................................................... 31
Oscilloscope ........................................................................................................................ 32
Objectives................................................................................................................................ 33
Voltage Swing Target.............................................................................................................. 34
Registers..................................................................................................................................... 34
Final Steps.................................................................................................................................. 35
Sanity Check ........................................................................................................................... 35
Updating the Software............................................................................................................ 35
Final Check ............................................................................................................................. 35
DisplayPort and Embedded DisplayPort Tuning Guide ............................................36
Abbreviations and Definitions.................................................................................................... 36
Required Equipment .................................................................................................................. 37
Test Fixtures ........................................................................................................................... 37
Oscilloscope and Probes........................................................................................................ 37
Unigraf DPR-100 or UCD-400................................................................................................ 38
Software .................................................................................................................................. 38

PRELIMINARY INFORMATION
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Method for Tuning ...................................................................................................................... 38
Drive Strength......................................................................................................................... 39
Pre-Emphasis......................................................................................................................... 39
Post Cursor2........................................................................................................................... 39
Procedures ................................................................................................................................. 39
DUT.......................................................................................................................................... 39
Oscilloscope and AUX Channel Controller............................................................................ 39
Objectives................................................................................................................................ 40
DisplayPort.......................................................................................................................... 40
Embedded DisplayPort....................................................................................................... 40
Registers..................................................................................................................................... 41
Final Steps.................................................................................................................................. 42
Sanity Check ........................................................................................................................... 42
Updating the Software............................................................................................................ 42
Final Check ............................................................................................................................. 42
Ethernet Compliance Test Guide .............................................................................43
Required Equipment .................................................................................................................. 43
Oscilloscope and Probes........................................................................................................ 44
Software .................................................................................................................................. 44
Measurement ............................................................................................................................. 44

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List of Figures
Figure 1. Device Removed from PCB for Characterization Example......................................12
Figure 2. Use of CBB as a Mode Pulse Generator ...................................................................14
Figure 3. SMA Differential Breakout Board..............................................................................14
Figure 4. SE DUT for REFCLK AC Measurement .....................................................................17
Figure 5. Breakout Board 50 Ω Differential Measurement Use ..............................................21
Figure 6. Orin Probing Diagram with PCIe Device Removed...................................................21
Figure 7. Differential Data Signal Waveform............................................................................22
Figure 8. Gen1 Data Signal at 2.5 GT/s Showing user interface = 400 ps...............................23
Figure 9. Source Eye Diagram: CK-D0......................................................................................25
Figure 10. Voltage Swing and Margin Results............................................................................33
List of Tables
Table 1. Host Mode Test Registers............................................................................................2
Table 2. NVIDIA Orin USB Registers..........................................................................................3
Table 3. TXEQ and RXEQ Pre-Emphasis....................................................................................4
Table 4. USB_CALIB and USB_CALIB_EXT Fuses....................................................................4
Table 5. Recommended Test Software....................................................................................15
Table 6. Abbreviations and Definitions ....................................................................................25
Table 7. Partial List of Acceptable HDMI Test Fixtures Type A..............................................27
Table 8. Partial List of Acceptable Oscilloscopes for HDMI 1.4 Tuning ................................27
Table 9. Partial List of Acceptable Oscilloscopes for HDMI 2.0 Tuning ................................28
Table 10. Partial List of Acceptable Oscilloscopes for HDMI 2.1 Tuning ................................28
Table 11. Partial List of Acceptable Probes..............................................................................29
Table 12. Partial List of Acceptable Probes for HDMI 2.1........................................................29
Table 13. Partial List of Acceptable Test Software...................................................................30
Table 14. Partial List of Acceptable Test Software for HDMI 2.1.............................................31
Table 15. Orin SOR Registers.....................................................................................................34
Table 16. Abbreviations and Definitions ....................................................................................36
Table 17. DisplayPort Configurations........................................................................................40
Table 18. Embedded DisplayPort Configurations .....................................................................40
Table 19. Orin SOR Registers.....................................................................................................41
Table 20. Glossary and Acronyms..............................................................................................43
Table 21. Orin RGMII Interface...................................................................................................43

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USB 2.0 Tuning Guide
This chapter describes the steps and lists the registers needed to tune the USB 2.0 high-speed
eye diagram for the Jetson AGX Orin™series modules. The USB Implementers Forum (USB IF)
provides complete test specifications and instructions on their website for high-speed host
and device mode testing.
Note: All occurrences of Orin module refer to Jetson AGX Orin series modules.
NVIDIA typically uses Tektronix oscilloscopes for USB characterizations. The test procedures
for Tektronix oscilloscopes are available from the USB-IF website.
Customers may use oscilloscopes from other vendors to perform USB characterization.
Required Equipment
The following equipment is required:
Tektronix TDS694C or faster digital sampling oscilloscope.
Tektronix P6247 or P6248 or equivalent differential probe.
High-speed USB Electrical Test Fixture.
Oscilloscope USB test software.
Software tool to access register and memory space on the Jetson AGX Orin module or to
build a special image to force the enable of the USB test mode.
Host Mode Testing Registers
Table 1 lists the USB 2.0 registers that must be toggles in order to force Test J, Test K, Test
SE0 NAK, and Test Packet on the respective USB ports.
Host Mode Testing Registers
Table 1 lists the USB 2.0 registers that must be toggled to force Test J, Test K, Test SE0 NAK,
and Test Packet on the respective USB ports.

USB 2.0 Tuning Guide
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Table 1. Host Mode Test Registers
Description Register Name and Setting
Normal Operations T_XUSB_XHCI_OP_PORTPMSCHS_x[31:28] = 0000b
Test J T_XUSB_XHCI_OP_PORTPMSCHS_x[31:28] = 0001b
Test K T_XUSB_XHCI_OP_PORTPMSCHS_x[31:28] = 0010b
Test SE0 NAK T_XUSB_XHCI_OP_PORTPMSCHS_x[31:28] = 0011b
Test Packet T_XUSB_XHCI_OP_PORTPMSCHS_x[31:28] = 0100b
Force Enable T_XUSB_XHCI_OP_PORTPMSCHS_x[31:28] = 0101b
The xUSB USB 2.0 port register addresses are as follows:
Port 0: 0x03610464: T_XUSB_XHCI_OP_PORTPMSCHS_4
Port 1: 0x03610474: T_XUSB_XHCI_OP_PORTPMSCHS_5
Port 2: 0x03610484: T_XUSB_XHCI_OP_PORTPMSCHS_6
Port 3: 0x03610494: T_XUSB_XHCI_OP_PORTPMSCHS_7
Note: NVIDIA uses the equipment listed for this guide. Contact the vendor for compliance
Oscilloscope and software.
Test Mode Programming Sequence
The programming sequence for enabling USB 2.0 test mode is as follows:
1. Connect any USB device (see Note) to the port. This will prevent the controller from
entering power down mode.
Note: The phrase “any USB device” refers to any real device, such as HS uDISK or LS mouse.
2. Disable the auto suspend for the controllers. For example, the following command under
Linux Kernel.
Note: These operations require root privileges.
echo on > /sys/bus/usb/devices/usb1/power/control
3. Set Port Power (PP) to Disabled state by setting T_XUSB_XHCI_OP_PORTSC[9] = 0
Port 0: 0x03610460: T_XUSB_XHCI_OP_PORTSC_4
Port 1: 0x03610470: T_XUSB_XHCI_OP_PORTSC_5
Port 2: 0x03610480: T_XUSB_XHCI_OP_PORTSC_6
Port 3: 0x03610490: T_XUSB_XHCI_OP_PORTSC_7

USB 2.0 Tuning Guide
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4. Set RS (Run/Stop) bit in the T_XUSB_XHCI_OP_USBCMD_0[0] = 0.
0x03610020: T_XUSB_XHCI_OP_USBCMD_0
5. Wait for the HCHalted (HCH) bit in the T_XUSB_XHCI_OP_USBSTS_0[0] = 1.
0x03610024: T_XUSB_XHCI_OP_USBSTS_0
6. Set the xUSB Port Test Control registers in PORTPMSCHS register. See “Host Mode
Testing Registers” section.
Note: Per USB 2.0 specification, only a single downstream facing port can be in test_mode at a
given time.
7. Disable Pad PD (power down) by clearing the
T_XUSB_PADCTL_USB2_OTG_PADx_CTL_0_0[26] = 0.
Port 0: 0x03520088: T_XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0
Port 1: 0x035200C8: T_XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0
Port 2: 0x03520108: T_XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0
Port 3: 0x03520148: T_XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0
8. Plug in the test fixture to start the USB 2.0 eye diagram test.
USB 2.0 Eye Diagram Registers
Table 2 lists the NVIDIA Orin™USB registers that are needed to tune the USB 2.0 eye diagram.
See “Tuning Procedure and Registers” section on how to use these registers during
characterization.
Table 2. NVIDIA Orin USB Registers
Register Name Bit Field Description
XUSB_PADCTL_USB2_OTG_PAD0_CTL_0_0 (Address 0x03520088) for Port 0
XUSB_PADCTL_USB2_OTG_PAD1_CTL_0_0 (Address 0x035200C8) for Port 1
XUSB_PADCTL_USB2_OTG_PAD2_CTL_0_0 (Address 0x03520108) for Port 2
XUSB_PADCTL_USB2_OTG_PAD3_CTL_0_0 (Address 0x03520148) for Port 3
HS_SLEW (See Note 1) 8:6 HSSLEW (high-speed slew rate control)
HS_CURR_LEVEL (See Note 2) 5:0 Setup (high-speed drive strength control)
XUSB_PADCTL_USB2_OTG_PAD0_CTL_1_0 (Address 0x0352008C) for Port 0
XUSB_PADCTL_USB2_OTG_PAD1_CTL_1_0 (Address 0x035200CC) for Port 1
XUSB_PADCTL_USB2_OTG_PAD2_CTL_1_0 (Address 0x0352010C) for Port 2
XUSB_PADCTL_USB2_OTG_PAD3_CTL_1_0 (Address 0x0352014C) for Port 3
RPD_CTRL 30:26 RPD_CTRL (15K host pull-down)
TERM_RANGE_ADJ 6:3 ATERM (high-speed termination control)

USB 2.0 Tuning Guide
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Register Name Bit Field Description
XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0 (Address 0x03520284)
HS_SQUELCH_LEVEL 2:0 HSSQUELCH (squelch level control for device RX testing)
XUSB_PADCTL_USB2_OTG_PAD0_CTL_3_0 (Address 0x03520094) for Port 0
XUSB_PADCTL_USB2_OTG_PAD1_CTL_3_0 (Address 0x035200D4) for Port 1
XUSB_PADCTL_USB2_OTG_PAD2_CTL_3_0 (Address 0x03520114) for Port 2
XUSB_PADCTL_USB2_OTG_PAD3_CTL_3_0 (Address 0x03520154) for Port 3
HS_RXEQ (See Note 3) 8:6 HS_RXEQ (device RX testing)
HS_TXEQ (See Note 3) 3:1 HS_TXEQ (device TX testing)
Notes:
1. HS_SLEW where 0’b000 = slowest and 0’b111 = fastest
2. HS_CURR_LEVEL where 0’b000000 = highest current level and 0’b111111 = lowest current level
3. If system has inner cable, consult with AE for recommendations and perform certificate and functional test
verification.
Table 3. TXEQ and RXEQ Pre-Emphasis
HS_TXEQ[2:0] AC Gain HS_RXEQ[2.0] SQ Level
00 +0 dB (default) 00 -0 dB (default)
01 +1.3 dB 01 -1.2 dB
10 +2.5 dB 10 -2.0 dB
11 +3.5 dB 11 -3.5 dB
Tuning Procedure and Registers
During production, each Orin SoC is calibrated based on the silicon process, the
corresponding USB drive strength (HS_CURR_LEVEL), HS termination (TERM_RANGE_ADJ),
and a 15K host pull-down (RPD_CTL). As a result, fuses are burnt on each chip.
Table 4 lists the breakdown for the USB_CALIB and USB_CALIB_EXT fuses. Reading from the
respective addresses will provide the default drive strength, HS termination, and 15K host
pull-down value.
Table 4. USB_CALIB and USB_CALIB_EXT Fuses
Register Name Bit Field Description
USB_CALIB fuse (Address 0x038201F0)
USB_CALIB 28:23 HS_CURR_LEVEL for USB Port 3
USB_CALIB 22:17 HS_CURR_LEVEL for USB Port 2
USB_CALIB 16:11 HS_CURR_LEVEL for USB Port 1
USB_CALIB 10:7 TERM_RANGE_ADJ for all USB ports

USB 2.0 Tuning Guide
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Register Name Bit Field Description
USB_CALIB 5:0 HS_CURR_LEVEL for USB Port 0
USB_CALIB_EXT fuse (Address 0x03820350)
USB_CALIB_EXT 16:13 USB pad TERM_RANGE_ADJ[3:0], for port 3
USB_CALIB_EXT 12:9 USB pad TERM_RANGE_ADJ[3:0], for port 2
USB_CALIB_EXT 8:5 USB pad TERM_RANGE_ADJ[3:0], for port 1
USB_CALIB_EXT 4:0 USB pad RPD_CTL[4:0], share for all ports
During the characterization stage, adjusting the HS_CURR_LEVEL value by modifying the USB
register listed in Table 2 directly should be enough to fulfill compliance requirements. It is
possible to try to increase termination as a last resort.
Note: Although it is possible to try to increase termination as a last resort, NVIDIA does not
recommend adjusting termination values. NVIDIA cautions that if the TERM_RANGE_ADJ is
adjusted, it may result in an impedance mismatch on the board and further attention might be
needed.
Once the characterization stage has completed, if modification to HS_CURR_LEVEL is
necessary, it must be done as an offset to the default fused value to account for silicon
process differences.
! CAUTION: Do not apply a global overwrite HS_CURR_LEVEL value for all silicon. Software should
read the fuse USB drive strength and add an offset to it.
All other settings can be modified directly:
To change high-speed slew rate, write directly to:
XUSB_PADCTL_USB2_OTG_PADx_CTL_0_0 bits 8:6
To change receive squelch level, write directly to:
XUSB_PADCTL_USB2_BIAS_PAD_CTL_0_0 bits 2:0
To compensate for long cable loss, use the XUSB_PADCTL_USB2_OTG_PADx_CTL_3_0
HS_TXEQ/HS_RXEQ bits directly.
HS_CURR_LEVEL Offset Adjustment Procedure
If the default values are not suitable to the customer design, adjust the HS_CURR_LEVEL
register to pass the USB HS eye diagram.
Follow this procedure:
1. Adjust the HS_CURR_LEVEL register as described in the "Tuning Procedure and
Registers" section to pass the USB HS eye diagram.
2. Obtain default value; read USB_CALIB fuse (Address 0x038201F0).
USB_CALIB[5:0] USB pad HS_CURR_LEVEL[5:0] for Port 0

USB 2.0 Tuning Guide
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USB_CALIB[16:11] USB pad HS_CURR_LEVEL[5:0] for Port 1
USB_CALIB[22:17] USB pad HS_CURR_LEVEL[5:0] for Port 2
USB_CALIB[28:23] USB pad HS_CURR_LEVEL[5:0] for Port 3
3. Calculate the offset from fused HS_CURR_LEVEL value and desired value from Step 1.
a). For example, if default value is 0x20 and desired value is 0x1C, then offset = -4
b). For example, if default value is 0x10 and desired value is 0x14, then offset = +4
Note: Maximum allowable offset: ±6 steps.
4. Provide the "tuned offset value" to software team so they can add the offset value when
initializing the registers in Table 2.
Software Verification
NVIDIA strongly recommends a functional check. Connect the DUT to USB hosts and devices
to perform a functional check.
To check if software has implemented the tuned offset correctly, load new software with offset
included into another DUT and make sure that:
HS_CURR_LEVEL = USB_CALIB fuse + tuned offset steps.

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USB 3.2 Compliance Test Guide
This chapter provides high-level guidance for compliance testing of the USB 3.2 PHY. It has a
performance of up to Gen1 (5 Gb/s) and Gen2 (10 Gb/s) in host mode on the Jetson AGX Orin
module. The Jetson AGX Orin module has been tested for specification compliance and has
passed under worst case scenarios. NVIDIA expects that no tuning will be required if
customers follow the routing guidelines published in the relevant design guides.
Compliance Testing
The compliance criteria and test descriptions for USB 3.2 devices, hubs, and host controllers
are based on the specification,
Electrical Compliance Test Specification SuperSpeed Universal
Serial Bus Rev 1.0
.
The
Electrical Compliance Test Specification Enhanced SuperSpeed Universal Serial Bus Rev
1.0a
also provides the compliance criteria and test descriptions for SuperSpeed Plus USB
devices, hubs, and host controllers that conform to the specification,
Universal Serial Bus 3.1
Specification, Rev 1.0
.
NVIDIA recommends that customer refer to the test specification documents mentioned for a
high-level overview of the tests that are performed to check the compliance criteria.
Depending on the brand of equipment being used for the test, customers can then refer to the
manufacturer’s documentation for step-by-step procedures on how to perform the tests.
! CAUTION: When the Jetson AGX Orin module is in USB RCM mode, it may not be in compliance
with the latest USB 3.2 specification.
USB 3.2 TX and RX Compliance Tests
To run the USB 3.2 TX electrical compliance test, the Orin module USB 3.2 controller must be
put in compliance mode.
To run the RX electrical JTOL test, the Orin module must be trained to be in loop-back mode.

USB 3.2 Compliance Test Guide
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Putting the Orin module USB 3.2 Controller in
Compliance Mode
For Gen1 (5 Gb/p) TX Electrical Tests refer to sections TD.1.1, TD.1.3, and TD.1.4. For Gen2 (10
Gb/s) TX Electrical Tests, refer to sections: TD 1.4, TD 1.5, and TD1.7. These sections can be
found in the
Electrical Compliance Test Specification SuperSpeed Universal Serial Bus at the
following link: https://www.usb.org/document-library/electrical-compliance-test-
specification-superspeed-usb-10-gbps-rev-10
Perform the following steps to place the device under test (DUT) into compliance mode:
1. Boot up the DUT. Ensure the USB 3.2 (Gen1 or Gen2) host test fixture is not connected to
the DUT.
2. Install the latest OS (Linux, for example) image for the Orin module.
3. Install the devmem2 tool (for the Linux installed in Step 2, for example) by running the
following command.
$ sudo apt-get install devmem2
4. Launch the USB 3.2 Compliance Test Software on the scope.
5. Disable the auto suspend for the controllers:
$ echo on > /sys/bus/usb/devices/usb1/power/control
$ echo on > /sys/bus/usb/devices/usb2/power/control
6. Enter compliance test mode.
$ ./devmem2 0x03610420 w 0x10340
$ ./devmem2 0x03610430 w 0x10340
$ ./devmem2 0x03610440 w 0x10340
Plug in the USB 3.2 host test fixture to DUT. The other end of fixture should be connected to a
scope such that DUT TX+/- with 50 ohm termination on the scope.
For connection details refer to the “Transmitter Test Topologies” section in
USB 3.0 Electrical
Test Fixture Topologies
, at the following link: https://www.usb.org/document-library/usb-31-
electrical-test-fixture-topology
7. Use ./devmem2 0x3610420 (that is, for L0) command to read back the LTSSM state.
Notes: The Orin module contains three USB 3.2 ports.
The PORTSC offset and pin # are:
•HS_UPHY0_L0_TX/RX (pins F13/E13/B15/B16), offset = 0x420
•HS_UPHY0_L1_TX/RX (pins E12/D12/A14/A15), offset = 0x430
•HS_UPHY0_L2_TX/RX (pins F11/E11/B13/B12), offset = 0x440
Writing 0x10340 will change the internal state of XUSB. Therefore, it is not expected to read back
the same value. However, Bits[8:5] should be set to 0xA for compliance test mode, otherwise
repeat Steps 1 through 7.
8. Connect RX+/- to external Ping.LFPS (20 MHz frequency; two periods) signal generator.

USB 3.2 Compliance Test Guide
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9. Sending a Ping.LFPS to the RX port of the DUT in compliance state will cause the
compliance pattern to transition to the next one. Contact generator vendor for support to
provide required number of Ping.LFPS until controller pumps out the required compliance
pattern.
10. Based on compliance pattern (CP) requirement for the current test, repeat Step 9 to pump
out required CP pattern.
11. Let the test complete.
Putting the Orin module USB 3.2 Controller in Loop-
Back Mode
To run the RX electrical JTOL test, the Orin module must be trained to be loop-back mode.
For Gen1 (5 Gb/s) Electrical Tests, refer to Sections: TD 1.2, TD.1.8, TD.1.9 (for Type-C). For
Gen2 (10 Gb/p) Electrical Tests, refer to Sections: TD.1.2 and TD.1.10 in the
Electrical
Compliance Test Specification SuperSpeed Universal Serial Bus Rev 1.0a
, at the following link:
https://www.usb.org/document-library/electrical-compliance-test-specification-superspeed-
usb-10-gbps-rev-10
Perform the following steps to put the DUT into loop-back mode:
1. Boot up the DUT. Make sure that the USB 3.2 host test fixture is not connected to the DUT.
2. Install the latest Linux image for Orin module.
3. Run the following script to disable power management for USB host controller.
#!/bin/sh
for hub in $(ls -d /sys/bus/usb/devices/usb?); do
echo on > $hub/power/control
done
4. For Gen 1x1 Configure BERT to pump out the loop-back training sequence, refer to Steps 5
through 11 in Section “TD.1.8 Receiver Jitter Tolerance Test at GT/s” or “TD.1.9 Receiver
Jitter Tolerance Test at GT/s (Type-C)” of the following specification:
https://usb.org/sites/default/files/SuperSpeedPHYComplianceTest_Spec1_0a.pdf
For Gen 2x1 upon detecting DUT Power On, refer to Steps 14 through 18 in Section
“TD.1.10 Receiver Jitter Tolerance Test at 10 GT/s” of the following specification:
https://usb.org/sites/default/files/SuperSpeedPHYComplianceTest_Spec1_0a.pdf
5. Connect the USB 3.2 host test fixture to the DUT. For fixture topologies and connections
for Gen1 and Gen2 RX testing, refer to the following: https://www.usb.org/document-
library/usb-31-electrical-test-fixture-topology
6. Start JTOL test after the controller is in loop-back or repeat Steps 1 through 5.
7. Let the test complete.

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PCIe Compliance Testing Reference
Jetson AGX Orin series modules (referred to as Orin module) include several high-speed UPHY
interfaces supporting protocols such as USB-3, PCIe, and UFS. Interface lanes can flexibly be
mapped to PADs to form a mix of different protocols.
The Orin module supports several PCIe controllers. The controllers can be assigned to
multiple UPHY lanes in three different domains (UPHY0, UPHY1, and UPHY2), in a mix with
other controllers such as USB and MGBE in x1, x2, x4, and x8 configurations. Refer to the
Jetson AGX Orin Series Data Sheet , the Jetson AGX Orin Design Guide, and the Orin Technical
Reference Manual
(TRM) for details.
The base requirement for all designs is to adhere to the
Jetson AGX Orin Design Guide layout
guidelines. PCIe shall pass all physical layer (PHY) specifications and conformance with no
change in production (PROD) register settings. Changing the PROD settings is not
recommended.
! CAUTION: Compliance testing and characterization as described in this application note covers
PCIe Gen1 to Gen3 only.
The Tx test procedures described in this application note are not recommended for Gen4 and
up, since they introduce higher amount of noise for measurements greater than Gen3
specifications. For higher speeds, functional testing and in-circuit test methods may be used.
Such as Eye Opening Monitor (EOM)–an NVIDIA built-in UPHY facility, or PCIe “Lane
Margining”–a mandatory support for devices with 16 GT/s or higher.
References
The following are PCIe specifications and NVIDIA documents references for PCIe compliance
testing.
PCISIG specifications:
•PCI Express Architecture PHY Test Specification 3.0 (Gen1, Gen2, and Gen3)
•PCI Express Architecture PHY Test Specification 4.0 (Gen1, Gen2, Gen3, and Gen4)
NVIDIA documents:
•Jetson AGX Orin Design Guide

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Patch Attachments
The following two files are attached to this application note:
319ad28.diff: This file is the patch for disabling power down
9b39010.diff: This file is the patch for disabling the spread Spectrum
To access the files, click the Attachment icon on the left-hand toolbar on this PDF (using
Adobe Acrobat Reader or Adobe Acrobat). Select the files and use the Tool Bar options (Open,
Save) to retrieve the files.
Electrical Characterization
This section details the electrical characterization for the PCIe compliance testing.
Prerequisites
Note the following prerequisites for electrical characterization.
For a given design, boot the design using the OS to make sure all register settings (in
particular, pad register settings) are in line with production environment.
Make sure only the up-to-date modes supported by Jetson AGX Orin for this interface are
used. Refer to the
Jetson AGX Orin Design Guide .
Note that this application note only deals with chip-down. This means that characterization
is performed for devices soldered down to the PCB. In case interfaces are realized through
PCIe slots or connectors, a similar but different approach may be needed. This application
note will highlight some but not all aspects of characterization DUT setup where needed to
avoid pitfalls. For all other information, refer to PCISIG specifications.
De-Embedding or Device Removal
Since this application note covers characterization for chip-down PCIe designs, the
characterization procedure must include handling a chip-down environment. Removing the
device is the standard way of characterizing chip-down PCIe connectivity. For PCIe transmit
characterization, it is required to remove the connected device, while for PCIe device
characterization it is required to remove the Orin module. Solder pads must be connected by
proper interconnects (solder tips for probes or breakout boards) to the scope.
Note that when the Orin module supplies REFCLK to a device and when device is tested with
the Orin module removed, REFCLK must be injected and supplied to the device. For more
REFCLK specifics, see “REFCLK Measurement and Characterization” section.

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The following figure shows part of an Orin module reference design.
Note the following:
Device is removed to probe at the pins.
In the example, the Orin module sourced REFCLK. It shall be injected from external source.
Figure 1. Device Removed from PCB for Characterization Example
Mid-Bus Probing
Note that mid-bus probing is not used by NVIDIA for characterization. Customers may use
access points for probes that may be Rx or Tx coupling caps. Proper access to traces at
coupling caps with the least possible distortion is required. Mid-bus probing is a less intrusive
form of de-embedding. In turn, it requires S-PARAMS to be extracted from layout in between
the coupling cap and the “remaining trace.” Assume one taps into the Orin module Tx lane-n,
the coupling cap will be removed, and Orin module Tx lane-n will be probed at the coupling
cap (Orin module side). The S-PARAM extracted from layout must model the remaining trace
from the coupling cap to the device pins. A scope used in this DUT setup must be able to fold
in real-time filters for convoluting S-PARMS with real-time measurement to model the
“remaining trace” real time.
Oscilloscopes
An oscilloscope is used to measure and capture the signals for Tx characterization. It must
fulfill data signal bandwidth requirements. The oscilloscope bandwidth shall be above Nyquist
frequency. For Gen4 maximum bandwidth must be greater than or equal to 25 GHz and have a
minimum sample rate of 64 GS/s. For Gen3 it must be at least 13 GHz and 32 GS/s.
BERT
A Bit Error Rate Tester (BERT) may be used for Rx testing, for example, the Rx_LINK equalizer
test. The BERT must be capable of acting as a loop-back initiator to drive the DUT lanes
selected for test into loop-back mode with the BERT acting as a link partner using interactive
link training.

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Cables
It is important when probing to use the lowest loss cables possible. For PCIe data lanes (and
REFCLK differential measurement), high-quality SMA cables must be used along with short
SMA-SMB cables (when needed). This is to probe the differential data signal taping into a
breakout board soldered to the PCB exhibiting an SMA connector. Cables, connectors, and
termination such as SMA (male)-SMA (male) cable, SMA (female)-SMP cable, SMP-SMP, SMA
male connector to SMP female connector and so on. SMP 50 Ω termination resistors shall be
good for 25 GHz or greater.
Probes
Probes are used to connect the oscilloscope and BERT to the test fixture or probing points.
Special adapters (breakout boards) and solder tips for probes may be required depending on
selected setup. The following probes may be required:
2× high Impedance and high-bandwidth probes (single-ended) for REFCLK stand
measurements.
50 Ω differential probes for REFCLK differential measurement and PCIe Rx and Tx lane
characterization.
Mode Pulse Generation
For Tx measurement, a 100 MHz and 1 ms pulse must be injected into the corresponding Rx
lane-n of the Tx lane-n to be characterized. Each single mode pulse will switch the Tx lane into
the subsequent preset. The default Tx preset after power-up will be Gen1. For this purpose,
either a PCI-SIG CBB stand-alone, or a signal generator may be used. Here is a brief overview
as to how to use a CBB as mode pulse generator for this purpose:
1. Set clock source to internal; use internal oscillator to generate pulse. See the area circled
in yellow in Figure 2.
2. Connect CBB J5/J85 to Rx lane-n P+ / P- of DUT
3. Connect ATX power supply to connector
4. Fix CBB in a stand or holder
5. Use push button to issue pulse to step through presets. See the area circled in blue in
Figure 2

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Figure 2. Use of CBB as a Mode Pulse Generator
Breakout Boards
NVIDIA uses a proprietary purpose-built breakout board for differential measurement to tap
into the solder pads of the devices taken off the board. It may also be used to inject the 100
MHz and 1 ms trigger pulse on Rx lanes to a DUT. Customers are requested to create or
purchase an equivalent solution or use probe solder tips. The breakout board is a good
example of how to provide connectivity into the DUT.
When using a breakout board, use a breakout channel S-Parameter file used to de-embed the
breakout channel when necessary. When using the S-Parameter file, the scope must be
capable of convoluting real-time measurement with S-Parameters.
Figure 3. SMA Differential Breakout Board