Nvidia JETSON TX2 User manual

JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 1
OEM PRODUCT DESIGN GUIDE
NVIDIA Jetson TX2/TX2i
Abstract
This document contains recommendations and guidelines forEngineers to follow to create a product that is optimized
to achieve the best performance fromthe common interfaces supported by the NVIDIA®Jetson™ TX2/TX2i System-
on-Module (SOM).
This document provides detailed information on the capabilities of the hardwaremodule, whichmay differ from
supported configurations by provided software.Refer to softwarereleasedocumentation for information on supported
capabilities.
Notes:
Jetson TX2 & Jetson TX2i modules utilize Tegra X2 which is a Parker series SoC.

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
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DocumentChange History
Date
Description
MAY, 2017
Initial Release
SEP, 2017
Power
- Added pull-up mention for CARRIER_PWR_ONand updatedfor RESET_OUT# & SLEEP# in Power &
SystemPin Descriptions (Table 5 & Table 90 in Appendix)
- Updated Power Block diagramto showpull-ups on CARRIER_PWR_ON, POWER_BTN# & SLEEP#and
added Auto-power-on block & pull-up for CHARGER_PRSNT#
- Added Deep Sleep (SC7) sequence
USB 3.0
- Added Electrical Spec section
- Updated impedance
- Added Trace Spacing f or TX/RXnon-interleaving section
PCIe
- Removednote under routing guidelines table related to maxtrace length as thiswas intended for chi-down
designs, not module based designs.
PCIe/SATA/HDMI
- Removedmin spacing between turn requirement from Serpentinesection
DSI/CSI guidelines
- Updated max frequency to include separate maxspeedsfor DSI & CSI
- Updated referenceplane
- Updated breakout impedance
- Updated main impedance
- Updated max trace delay to include differentlengths for1.0, 1.5 & 2.5 Gbps
HDMI
- Added pre HDMI 1.4b max length/delay requirements
I2C
- Updated notes under I2C signal Connectionstable to use E_IO_HV, notE_OD_HV.
UART
- Updated UART Connectionsfigure toadd strapping information and addedcaution note belowfigure
Debug
- Removedexternal pull-up on JTAG_GP0 (JTAG_TRST_N)
Strapping
- Updated figure, table & notesto remove mention of RAM_CODE[3:2]straps.
Pads
- Updated Schmitt Trigger Usage section toadd caution when considering changing settings
Checklist
- Corrected on-module termination for CHARGER_PRSNT# & added RESET_OUT#
- Added check for using pins associated with Tegra straps
FEB, 2018
General
- Updated to include Jetson TX2i where appropriate
- Added SDIO pins which are supported by TX2i
- Updated text/figuresto indicate WLAN/BTavailable on TX2 only
Power
- Added separate VDD_INvoltage range for TX2i
- Added note under “Main Power Source/Supply Connections” figure that ground must make contact before
power when applying main power supply.
- Updated power sectionto includedifferences for TX2i
- Added separate Auto-Power-On supportsections for TX2 & TX2i
USB/PCIe/SATA
- Swapped order of lane mapping tables to have the "compatible" table first& modified text/notes to match
HDMI
- Updated HDMI connection figure to have correct lane connections in connectorblock
- Added notes/table entriesindicating only a single CEC controller is available
Audio
- Added DMIC guidelines
Strapping
- Updated note #6 below strappingtable
JUN, 2018
General
- RemovedJetson TX1 mention in document except notein USB, PCIe& SATA section refering to the Jetson
TX1/TX2 Comparison & Migration ANfor differencesin lane mappingsupport.
Abstract

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Date
Description
- Added paragraph related to potential differencesbetween hardware capabilities and support in released
software.
References
- Added Jetson TX2/TX2i & Jetson TX1/TX2 Comparison & Migration App Notes.
Power
- Updated to to add separate Power-Upsequence figures and timing tablesfor Power-button cases& Auto-
power-on cases & note on differencesbetween TX2i in P2597_B04 vsC02.
- Updated Auto-power-on section to removealternate external solutions(kept mechanisms built-in to TX2 &
TX2i modules).
USB 3.0
- Added USB 2.0/3.0 dual-rolw(host/device) connection example.
- Updated Insertion Loss & max trace lengthguidelinesto include device mode.
- Updated minimumAC cap value.
Ethernet
- Updated Magneticsconnections figure to showindividual capsto GNDon CTinputs of magneticsdevice.
HDMI/DP
- Updated eDP/DP connection examplefigure toshowonly Tegra & Module pin namesin Tegra block.
- Updated HDMI connection example figureto correctly align CLK/Data from Tegra to Connector & to show
only Tegra & Module pin names in Tegra block.
CSI
- Updated intro paragraph to indicate 3 quad or 6 dual lane cameras possible & added reference to
configuration table
WLAN/BT
- Updated Mating Antenna connector requirement to include both I-PEX& Hiroseoptions.
Strapping
- Updated Power-on Strapping Breakdown tableto showpull-up on module for Tegra RAM_CODE pins may
be present or not installed.
Pads
- Updated "Module Pins Pulled High on the Module Prior toCARRIER_PWR_ON Active" table to correct pull-
up on module for RESET_OUT# pin.

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Table of Contents
1.0 INTRODUCTION.............................................................................................................................................................................6
1.1 References ...............................................................................................................................................................................6
1.2 Abbreviations and Definitions ..............................................................................................................................................6
2.0 JETSONTX2/TX2I..........................................................................................................................................................................7
2.1 Overview...................................................................................................................................................................................7
3.0 POWER...........................................................................................................................................................................................9
3.1 Supply Allocation..................................................................................................................................................................10
3.2 Main Power Sources/Supplies............................................................................................................................................11
3.3 Power Sequencing................................................................................................................................................................11
3.4 Power Discharge...................................................................................................................................................................15
3.5 Module Power-on Type Detection & Control....................................................................................................................15
3.6 Power &Voltage Monitoring...............................................................................................................................................17
3.7 Deep Sleep (SC7) ..................................................................................................................................................................18
3.8 Optional Auto-Power-On Support......................................................................................................................................19
4.0 GENERAL ROUTING GUIDELINES...........................................................................................................................................21
5.0 USB, PCIE& SATA......................................................................................................................................................................23
5.1 USB .........................................................................................................................................................................................25
5.2 PCIe.........................................................................................................................................................................................30
5.3 SATA .......................................................................................................................................................................................33
6.0 GIGABIT ETHERNET...................................................................................................................................................................36
7.0 DISPLAY.......................................................................................................................................................................................38
7.1 MIPI DSI ..................................................................................................................................................................................38
7.2 eDP / DP / HDMI .....................................................................................................................................................................41
8.0 MIPI CSI (VIDEO INPUT).............................................................................................................................................................51
9.0 SDIO/SDCARD/EMMC.................................................................................................................................................................55
9.1 SD Card...................................................................................................................................................................................55
10.0 AUDIO .........................................................................................................................................................................................58
11.0 WLAN/ BT (INTEGRATED) JETSON TX2 ONLY ...............................................................................................................61
12.0 MISCELLANEOUS INTERFACES............................................................................................................................................63
12.1 I2C .........................................................................................................................................................................................63
12.2 SPI .........................................................................................................................................................................................65
12.3 UART .....................................................................................................................................................................................67
12.4 Fan.........................................................................................................................................................................................69
12.5 CAN .......................................................................................................................................................................................69
12.6 Debug....................................................................................................................................................................................71
12.7 Strapping Pins.....................................................................................................................................................................72
13.0 PADS...........................................................................................................................................................................................75

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13.1 MPIO Pad Behavior when Associated Power Rail is Enabled.....................................................................................75
13.2 Internal Pull-ups for CZ Type Pins at Power-on.............................................................................................................75
13.3 Schmitt Trigger Usage .......................................................................................................................................................75
13.4 Pins Pulled/Driven High During Power-on......................................................................................................................75
13.5 Pad Drive Strength..............................................................................................................................................................76
14.0 UNUSED INTERFACETERMINATIONS .................................................................................................................................77
14.1 Unused MPIO Interfaces ....................................................................................................................................................77
14.2 Unused SFIO Interface Pins..............................................................................................................................................77
15.0 DESIGNCHECKLIST ................................................................................................................................................................78
16.0 APPENDIX A: GENERAL LAYOUT GUIDELINES ................................................................................................................86
16.1 Overview...............................................................................................................................................................................86
16.2 Via Guidelines .....................................................................................................................................................................86
16.3 Connecting Vias..................................................................................................................................................................87
16.4 Trace Guidelines.................................................................................................................................................................87
17.0 APPENDIX B: STACK-UPS .....................................................................................................................................................89
17.1 Reference Design Stack-Ups............................................................................................................................................89
18.0 APPENDIX C: TRANSMISSIONLINE PRIMER ......................................................................................................................90
18.1 Background.........................................................................................................................................................................90
18.2 Physical Transmission Line Types..................................................................................................................................90
18.3 Driver Characteristics ........................................................................................................................................................91
18.4 Receiver Characteristics....................................................................................................................................................91
18.5 Transmission Lines & Reference Planes........................................................................................................................91
19.0 APPENDIX D: DESIGN GUIDELINE GLOSSARY.................................................................................................................94
20.0 APPENDIX E: JETSON TX2/TX2I PIN DESCRIPTIONS.......................................................................................................95

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1.0 INTRODUCTION
1.1 References
Refer to the documents or models listed in Table 1 formore information. Use the latest revision of all documents at all times.
Table 1. List of Related Documents
Document
Jetson TX2/TX2i Module Data Sheet
Parker Series SoC Technical Reference Manual
Jetson TX1/TX2 Developer Kit Carrier Board Specification
Jetson TX2i Module Pinmux
Jetson TX2 and Jetson TX2i Comparison and Migration Application Note
Jetson TX1 and Jetson TX2 Comparison and Migration Application Note
Jetson TX2i Thermal Design Guide
Jetson TX2 Developer Kit Carrier Board Design Files (P2597_B04)
Jetson TX2 Developer Kit C arrier Board BOM (P2597_B04)
Jetson Developer Kit Camera Module Design Files
Jetson TX1/TX2/TX2i Supported Component List
1.2 Abbreviations and Definitions
Table 2 lists abbreviations that may be used throughout this document and their definitions.
Table 2. Abbreviations and Definitions
Abbreviation
Definition
BT
Bluetooth
CEC
Consumer Electronic Control
CAN
Controller Area Network
DP
Display Port
eDP
Embedded Display Port
eMMC
Embedded MMC
GPS
Global Positioning System
HDMI
High Definition Multimedia Interface
I2C
Inter IC
I2S
Inter IC Sound Interface
LCD
Liquid Crystal Display
LDO
Low Dropout (voltage regulator)
LPDDR4
Low Power Double Data Rate DRAM, Fourth-generation
PCIe (PEX)
Peripheral Component Interconnect Express interface
PCM
Pulse Code Modulation
PHY
Physical Interface (i.e. USB PHY)
PMC
Power Management Controller
PMIC
Power Management IC
RF
Radio Frequency
RTC
Real Time Clock
SATA
 
SDIO
Secure Digital I/O Interface
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver-Transmitter
USB
Universal Serial Bus
WLAN
Wireless Local Area Network

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2.0 JETSONTX2/TX2i
2.1 Overview
The Jetson TX2/TX2i module resides at the center of the embedded system solution and includes:
1. Power (PMIC/Regulators, etc.)
2. Ethernet PHY
3. DRAM (LPDDR4)
4. Power & Voltage Monitors
5. eMMC
6. Thermal Sensor
7. Connects to WLAN and Bluetooth enabled devices (TX2 only)
In addition, a range of interfaces are available at the main connector for use on the carrier board as shownin the follow ing table.
Table 3. Jetson TX2/TX2i Interfaces
Catagory
Function
Catagory
Function
USB
USB 2.0 (3x)
LAN
Gigabit Ethernet
USB 3.0 (up to 3x) see note
CAN
2x
PCIe
Control [x3] (shared Wake)
I2C
8x
PCIe (3 root ports - See note)
UART
5x
SATA
SATA & Device Sleep control
SPI
3x
Camera
CSI (6 x2 or 3 x4), Control, Clock
WLAN/BT/Modem
PEX/UART/I2S, Control/handshake
(external only solution for TX2i)
Display
2x eDP/DP/HDMI
Touch
Touch Clock, Interrupt & Reset
DSI (2 x4), Display/Backlight Control
Sensor
Control & Interrupt
Audio
I2S (4x), Control & Clock
Fan
FAN PWM & Tach Input
Digital Mic & Speaker
Debug
JTAG, UART
SD Card
SD Card or SDIO
System
Power Control, Reset, Alerts
SDIO
SD Card or SDIO (Jetson TX2i only)
Power
Main Input
Note:
Some USB 3.0 or PCIe instances are shared. Refer to Chapter 5.0 USB, PCIe & SATA for details.
Table 4. Jetson TX2/TX2i Connector (8x50) Pin Out Matrix
A
B
C
D
E
F
G
H
1
VDD_IN
VDD_IN
VDD_IN
RSVD
FORCE_RECOV#
AUDIO_MCLK
I2S0_SDIN
I2S0_LRCLK
2
VDD_IN
VDD_IN
VDD_IN
RSVD
SLEEP#
GPIO19_AUD_RST
I2S0_CLK
I2S0_SDOUT
3
GND
GND
GND
RSVD
SPI0_CLK
SPI0_CS0#
GND
GPIO20_AUD_INT
4
GND
GND
GND
RSVD
SPI0_MISO
SPI0_MOSI
DSPK_OUT_CLK
DSPK_OUT_DAT
5
RSVD
RSVD
RSVD
UART7_RX
I2S3_SDIN
I2S3_LRCLK
I2S2_CLK
I2S2_LRCLK
6
I2C_PM_CLK
I2C_PM_DAT
I2C_CAM_CLK
I2C_CAM_DAT
I2S3_CLK
I2S3_SDOUT
I2S2_SDIN
I2S2_SDOUT
7
CHARGING#
CARRIER_STBY#
BATLOW#
GPIO5_CAM_FLASH_EN
CAM2_MCLK
GPIO1_CAM1_PWR#
GPIO4_CAM_STROBE
GPIO3_CAM1_RST#
8
GPIO14_AP_WAKE_MDM
VIN_PWR_BAD#
BATT_OC
UART7_TX
CAM_VSYNC
CAM1_MCLK
GPIO0_CAM0_PWR#
GPIO2_CAM0_RST#
9
GPIO15_AP2MDM_
READY
GPIO17_MDM2AP_
READY
WDT_TIME_OUT#
UART1_TX
UART1_RTS#
CAM0_MCLK
UART3_CTS#
UART3_RX
10
GPIO16_MDM_
WAKE_AP
GPIO18_MDM_COL
DBOOT
I2C_GP2_DAT
UART1_RX
UART1_CTS#
GND
UART3_RTS#
UART3_TX
11
JTAG_GP1
JTAG_TCK
I2C_GP2_CLK
RSVD
RSVD
RSVD
UART0_RTS#
UART0_CTS#
12
JTAG_TMS
JTAG_TDI
I2C_GP3_CLK
RSVD
RSVD
RSVD
UART0_RX
UART0_TX
13
JTAG_TDO
JTAG_GP0
I2C_GP3_DAT
I2S1_LRCLK
RSVD
SPI1_MOSI
SPI1_CLK
GPIO8_ALS_PROX_INT
14
JTAG_RTCK
GND
I2S1_SDIN
I2S1_SDOUT
SPI1_CS0#
SPI1_MISO
GPIO9_MOTION_INT
SPI2_CLK
15
UART2_CTS#
UART2_RX
I2S1_CLK
I2C_GP0_DAT
I2C_GP0_CLK
GND
SPI2_MOSI
SPI2_MISO
16
UART2_RTS#
UART2_TX
FAN_PWM
AO_DMIC_IN_DAT
AO_DMIC_IN_CLK
SPI2_CS1#
SPI2_CS0#
SDCARD_PWR_EN
17
USB0_EN_OC#
FAN_TACH
CAN1_STBY
CAN1_RX
RSVD
SDCARD_CD#
GND
SDCARD_D1
18
USB1_EN_OC#
RSVD
CAN1_TX
CAN0_RX
CAN0_ERR
SDCARD_D3
SDCARD_CLK
SDCARD_D0
19
RSVD
GPIO11_AP_WAKE_BT
CAN1_ERR
CAN0_TX
GND
SDCARD_D2
SDCARD_CMD
GND
20
I2C_GP1_DAT
GPIO10_WIFI_WAKE_AP
CAN_WAKE
GND
CSI5_D1-
SDCARD_WP
GND
CSI4_D1-
21
I2C_GP1_CLK
GPIO12_BT_EN
GND
CSI5_CLK-
CSI5_D1+
GND
CSI4_CLK-
CSI4_D1+
22
GPIO_EXP1_INT
GPIO13_BT_WAKE_AP
CSI5_D0-
CSI5_CLK+
GND
CSI4_D0-
CSI4_CLK+
GND
23
GPIO_EXP0_INT
GPIO7_TOUCH_RST
CSI5_D0+
GND
CSI3_D1-
CSI4_D0+
GND
CSI2_D1-

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A
B
C
D
E
F
G
H
24
LCD1_BKLT_PWM
TOUCH_CLK
GND
CSI3_CLK-
CSI3_D1+
GND
CSI2_CLK-
CSI2_D1+
25
LCD_TE
GPIO6_TOUCH_INT
CSI3_D0-
CSI3_CLK+
GND
CSI2_D0-
CSI2_CLK+
GND
26
GSYNC_HSYNC
LCD_VDD_EN
CSI3_D0+
GND
CSI1_D1-
CSI2_D0+
GND
CSI0_D1-
27
GSYNC_VSYNC
LCD0_BKLT_PWM
GND
CSI1_CLK-
CSI1_D1+
GND
CSI0_CLK-
CSI0_D1+
28
GND
LCD_BKLT_EN
CSI1_D0-
CSI1_CLK+
GND
CSI0_D0-
CSI0_CLK+
GND
29
SDIO_RST#
SDIO_CMD
CSI1_D0+
GND
DSI3_D1+
CSI0_D0+
GND
DSI2_D1+
30
SDIO_D3
SDIO_CLK
GND
DSI3_CLK+
DSI3_D1-
GND
DSI2_CLK+
DSI2_D1-
31
SDIO_D2
GND
DSI3_D0+
DSI3_CLK
GND
DSI2_D0+
DSI2_CLK-
GND
32
SDIO_D1
SDIO_D0
DSI3_D0-
GND
DSI1_D1+
DSI2_D0-
GND
DSI0_D1+
33
DP1_HPD
HDMI_CEC
GND
DSI1_CLK+
DSI1_D1-
GND
DSI0_CLK+
DSI0_D1-
34
DP1_AUX_CH-
DP0_AUX_CH-
DSI1_D0+
DSI1_CLK
GND
DSI0_D0+
DSI0_CLK-
GND
35
DP1_AUX_CH+
DP0_AUX_CH+
DSI1_D0-
GND
DP1_TX3-
DSI0_D0-
GND
DP0_TX3-
36
USB0_OTG_ID
DP0_HPD
GND
DP1_TX2-
DP1_TX3+
GND
DP0_TX2-
DP0_TX3+
37
GND
USB0_VBUS_DET
DP1_TX1-
DP1_TX2+
GND
DP0_TX1-
DP0_TX2+
GND
38
USB1_D+
GND
DP1_TX1+
GND
DP1_TX0-
DP0_TX1+
GND
DP0_TX0-
39
USB1_D
USB0_D+
GND
PEX_RFU_TX+
DP1_TX0+
GND
PEX_RFU_RX+
DP0_TX0+
40
GND
USB0_D-
PEX2_TX+
PEX_RFU_TX-
GND
PEX2_RX+
PEX_RFU_RX-
GND
41
PEX2_REFCLK+
GND
PEX2_TX-
GND
PEX1_TX+
PEX2_RX-
GND
PEX1_RX+
42
PEX2_REFCLK
USB2_D+
GND
USB_SS1_TX+
PEX1_TX-
GND
USB_SS1_RX+
PEX1_RX-
43
GND
USB2_D-
USB_SS0_TX+
USB_SS1_TX-
GND
USB_SS0_RX+
USB_SS1_RX-
GND
44
PEX0_REFCLK+
GND
USB_SS0_TX-
GND
PEX0_TX+
USB_SS0_RX-
GND
PEX0_RX+
45
PEX0_REFCLK
PEX1_REFCLK+
GND
SATA_TX+
PEX0_TX-
GND
SATA_RX+
PEX0_RX-
46
RESET_OUT#
PEX1_REFCLK-
PEX2_CLKREQ#
SATA_TX-
GND
GBE_LINK1000#
SATA_RX-
GND
47
RESET_IN#
GND
PEX1_CLKREQ#
SATA_DEV_SLP
GBE_LINK_ACT#
GBE_MDI1+
GND
GBE_MDI3+
48
CARRIER_PWR_ON
SYS_WAKE#
PEX0_CLKREQ#
PEX_WAKE#
GBE_MDI0+
GBE_MDI1-
GBE_MDI2+
GBE_MDI3-
49
CHARGER_PRSNT#
MOD_PWR_CFG_ID
PEX0_RST#
PEX2_RST#
GBE_MDI0-
GND
GBE_MDI2-
GND
50
VDD_RTC
POWER_BTN#
RSVD
RSVD
PEX1_RST#
GBE_LINK100#
GND
RSVD
Legend
Ground
Power
RSVD on Jetson TX2 (available on TX2i)
Reserved
Redefined for Jetson TX2i
Notes:
1. RSVD (Reserved) pins must be left unconnected.
2. Signals starting with “GPIO_” are standard GPIOs that have been assigned recommended usage. If the assigned usage is
required in a design, it is recommended the matching GPIO be used. If the assigned usage is n ot required, the pins may be
used as GPIOs for other purposes.

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3.0 POWER
Caution
Jetson TX2/TX2i is not hot-pluggable. Before installing or removing the module, the main power
supply (to VDD_IN pins) must be disconnectedand adequate time (recommended > 1 minute) must
be allowed for the various power rails to fully discharge.
Table 5. Jetson TX2/TX2i Power & System Pin Descriptions
Pin #
Module Pin Name
Tegra Signal
Usage/Description
Usage on the
Carrier Board
Direction
Pin Type
A1
VDD_IN

Main power Supplies PMIC & external supplies
Main DC input
Input
5.5V-19.6V (TX2)
9.0V 19.0V (TX2i)
(See note 1)
A2
VDD_IN
B1
VDD_IN
B2
VDD_IN
C1
VDD_IN
C2
VDD_IN
C7
BATLOW#
(PMIC_GPIO6)
Battery Low (PMIC GPIO)
System
Input
CMOS 1.8V
A48
CARRIER_PWR_ON

Carrier Power On. Used as part of the power up sequence.
The module asserts this signal when it is safe for the carrier
board to power up. -up to VDD_3V3_SYS is
present on the module.
Output
Open-Collector 3.3V
B7
CARRIER_STBY#
SOC_PWR_REQ
Carrier Board Standby: The module drives this signal low
when it is in the standby power state.
Output
CMOS 1.8V
A49
CHARGER_PRSNT#
(PMIC ACOK)
Charger Present. Connected on module to PMICACOK
through FET & -up
internally to MBATT (VDD_5V0_SYS). Can optionally be used
to support auto-power-on where the module platform will
power-on when the main power source is connected instead
of waiting for a power button press.
Input
MBATT level 5.0V
(see note 2)
A7
CHARGING#
(PMIC GPIO5)
Charger Interrupt
Input
CMOS 1.8V
C16
FAN_PWM
GPIO_SEN6
Fan PWM
Fan
Output
CMOS 1.8V
B17
FAN_TACH
UART5_TX
Fan Tachometer
Input
CMOS 1.8V
E1
FORCE_RECOV#
GPIO_SW1
Force Recovery strap pin
System
Input
CMOS 1.8V
B50
POWER_BTN#
POWER_ON / (PMIC
EN0)
Power Button. Used to initiate a system power-on.
-up to
VDD_5V0_SYS. Also connected to Tegra POWER_ON pin
-up to VDD_1V8_AP near
Tegra.
Input
CMOS 5.0V
(see note 2)
A47
RESET_IN#
(PMIC NRST_IO)
Reset In. System Reset driven from PMIC to carrier board for
devices requiring full system reset. Also driven from carrier
board to initiate full system reset (i.e. RESET button). A pull-
up is present on module.
Bidir
Open Drain, 1.8V
A46
RESET_OUT#
SYS_RESET_N
Reset Out. Reset from PMIC (through diodes) toTegra &
eMMC reset pins. Driven from carrier board to force reset of
Tegra & eMMC (not PMIC). An external 100pull-up to
1.8V near Tegra (module pin side) & external 
pull-up to 1.8V on the other side of a diode (PMIC
side).
Bidir
CMOS 1.8V
E2
SLEEP#
GPIO_SW2
Sleep Request to the module from the carrier board. An
internal Tegra pull-up is presenton the signal.
Sleep (VOL
DOWN) button
Input
CMOS 1.8V
(see note 2)
B8
VIN_PWR_BAD#

VDD_IN Power Bad. Carrier board indication to the module
that the VDD_IN power is not valid. Carrier board should de-
assert this (drive high) only when VDD_IN has reached its
required voltage level and is stable. This prevents Tegra from
powering up until the VDD_IN power is stable.
System
Input
CMOS 5.0V
C9
WDT_TIME_OUT#
GPIO_SEN7
Watchdog Timeout
Input
CMOS 1.8V
A50
VDD_RTC
(PMIC BBATT)
Real-Time-Clock. Optionally used to provide back-up power
for RTC. Connects to Lithium Cell or super capacitor on
Carrier Board. PMIC is supply when charging cap or coin cell.
Super cap or coin cell is source when system is disconnected
from power.
Battery Back-up
using Super-
capacitor
Bidir
1.65V-5.5V
C8
BATT_OC
BATT_OC
Battery Over-current (& Thermal) warning
Bidir
CMOS 1.8V
B48
SYS_WAKE#
POWER_ON
Power button & SC7 wake interrupt
Power/SC7 wake
Input
CMOS 1.8V
B49
MOD_PWR_CFG_ID

Module power configuration identification. Tied to GND on
Jetson TX2i. Floating on Jetson TX2. Determines the power-
on mechanism used to support both Jetson TX2 & TX2i.
Module power
configuration ID
Output
VDD_IN level

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 10
Note:
1. Power efficiency is higher when the input voltage is lower, such as 9V or 12V. At very low voltages (close to the 5.5V
minimum [TX2 only], the power supported by some of the supplies may be reduced).
2. These pins are handled as Open-Drainon the carrier board.
Figure 1. Power Block Diagram
Jetson TX2/TX2i
DC
Jack A1
A2
B1
B2
C1
C2
A50
Memory/Peripherals
LPDDR4, eMMC,
Ethernet,
WiFi / BT (TX2 only)
Power Subsystem
5V/3.3V Pre-Regs
PMU Switchers/LDOs
CPU/GPU Regs
Ext. LDOs
Load Switches
Tegra
VDD_RTC
VDD_IN
B8
E2
B50
A47
A46
A48
VIN_PWR_BAD#
CARRIER_PWR_ON
RESET_IN#
RESET_OUT#
POWER_BTN#
SLEEP#
CARRIER_STBY#
CHARGER_PRSNT#
MOD_PWR_CFG_ID
B7
From Carrier Board main
power input & discharge circuit
To Carrier Board power subsystem
System Reset to/from Carrier Board
Tegra Force Reset from Carrier Board
Optional Sleep Button
To Carrier Board to disable devices/
rails to be off in sleep mode
SLEEP
Optional Power Button
POWER
SuperCap
orLi Cell
(Optional)
A49 Optional signal from Carrier Board
to support Auto-Power-On
PU
PU
PU
Auto-power-
on Circuit
PU
ACOK
PU
PU
PU
PU
B49
Jetson TX2
Jetson TX2i
To Carrier Board Power-on circuitry
(B49 on Jetson TX2 is RSVD – No Connect)
3.1 Supply Allocation
Table 6 Internal Power Subsystem Allocation
Power Rails
Usage
(V)
Power Supply
Source
VDD_5V0_SYS
Supplies various switchers & load switches that power
the various circuits & peripherals on the module
5.0
5V DC-DC
VDD_IN
VDD_CPU
Tegra MCPU/BCPU
1.0 (Var)
OpenVREG (uP1666QQKF)
VDD_5V0_SYS
VDD_GPU & VDD_SRAM
Tegra GPU & SRAM
1.0 (Var)
OpenVREG (uP1666QQKF)
VDD_5V0_SYS
VDD_SOC (CORE)
Tegra Core
1.0 (Var)
OpenVREG (uP1666QQKF)
VDD_5V0_SYS
VDD_DDR_1V1_PMIC
LPDDR4
1.125
PMIC Switcher SD0
VDD_5V0_SYS
AVDD_DSI_CSI_1V2
Source for some DSI/CSI blocks
1.2
PMIC Switcher SD1
VDD_5V0_SYS
VDD_1V8
Tegra, eMMC, WLAN
1.8
PMIC Switcher SD2
VDD_5V0_SYS
VDD_3V3_SYS
Supplies various LDOs & load switches that in turn
power the various circuits & peripherals on the module
3.3
PMIC Switcher SD3
VDD_5V0_SYS
VDDIO_3V3_AOHV
Tegra VDDIO_AO_HV rail
3.3
PMIC LDO 2
VDD_5V0_SYS
VDDIO_SDMMC1_AP
Tegra SD Card I/O rail
1.8/3.3
PMIC LDO 3
VDD_5V0_SYS
VDD_RTC (See note)
Tegra Real Time Clock/Always-on Rail
1.0 (Var)
PMIC LDO 4
VDD_1V8
VDDIO_SDMMC3_AP
Tegra SDIO rail
1.8/3.3
PMIC LDO 5
VDD_5V0_SYS
VDD_HDMI_1V05
Tegra HDMI / DP rail
1.0
PMIC LDO 7
AVDD_DSI_CSI_1V2
VDD_PEX_1V05
Tegra PCIe / USB 3.0 / SATA rail
1.0
PMIC LDO 8
AVDD_DSI_CSI_1V2
VDD_1V8_AP (&
VDD_1V8_AP_PLL)
Main 1.8V Tegra rail
1.8
Load Switch
VDD_1V8
Note:
This is the Tegra supply, and should not be confused with the module VDD_RTC pin which is the supply that connects to the
PMIC BBATT pin to keep the Real-Time Clock powered.

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 11
3.2 Main Power Sources/Supplies
The figure below shows the pow er connections used on the carrier board, including the DC Jack which connects to the AC/DC
adapter, and the main 5.0V, 3.3V and 1.8V supplies. Also shownare the power control signals that are used to enable these
supplies, or are used to communicate powersequence information to the module or other circuitry on the carrier board (i.e.
discharge circuits).
Figure 2. Main Power Source/Supply Connections
VDD_19V_IN (TX2: 5.5V-19.6V)
(TX2i: 9.0V-19.0V)
VIN_PWR_BAD#
VDD_MOD
TPS53015
DC-DC SWVIN
CARRIER_PWR_ON
PGEN
3V3_SYS_BUCK_EN
TPS53015
DC-DC SWVIN
PGEN VDD_3V3_SYS_PG
VDD_3V3_SYS
To Jetson TX2 VDD_IN
From
Jetson TX2
To Jetson TX2 & Power
Discharge Circuitry
Main Carrier
Board 5V Supply
Main Carrier Board
3.3V Supply
Main 3.3V Power Good –
Routed to Power LED on
Carrier board
DC Jack
G
DS FET
APW8805
OpenVReg
VIN SW
PGOOD
VDD_5V0_IO_SYS
VCC
1V8_IO_PG
EN/FS
VDD_1V8
1V8_IO_VREG_EN
RESET_OUT#
Main Carrier Board
1.8V Supply
To Jetson TX2 (RESET_OUT#)
to keep Tegra in Reset until
1.8V rail Valid
Main 3.3V Power Good –
Routed to Power LED on
Carrier board
From Main
5V supply
U31
U16
U9
VDD_5V0_IO_SYS
G
DS FET
G
S
D
PWR
FET
G
S
D
PWR
FET
MOD_VIN_EN
G
DS FET G DS FET
5V
Red – P2597_C02
(TX2/TX2i)
Carrier Board
Blue – P2597_B04 Carrier Board
From On/Off
Controller
Note
- The figure above is a high-level representation of the connections involved. Refer to the latest carrier board
reference design for details.
- When connecting the main power, the ground must make connectionbefore the main power rail.
3.3 Power Sequencing
In order to ensure reliable and consistent power up sequencing, the pins VIN_PWR_BAD#, CARRIER_PWR_ON, and
RESET_OUT# on the module connector should be connected and used as described below:
VIN_PWR_BAD# signal is generated by the Carrier Board and passed to the module to keep the Tegra processor powered off
until the VDD_IN supply is stable and it is possible to power up any standby circuits on the module. This signal prevents the
Tegra processorfrom poweringup prematurely before the Carrier Board has charged up its decoupling capacitors and pow er to
the module is stable

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 12
CARRIER_PWR_ON signal is generated by the module and passed to the Carrier Board to indicate that the module is powered
up and that the power up sequence forthe Carrier Board circuits can begin.
RESET_OUT# is de-asserted by the Carrier Board after a period sufficientto allow the Carrier Board circuits to power up.
Figure 3. Power Up Sequence –Power-Button Case (Jetson TX2i in P2597_C02)
CARRIER_PWR_ON
POWER_BTN#
VIN_PWR_BAD#
VDD_IN
Carrier Board VDD_1V8 (note 1)
Jetson module System Power (Main 1.8V
rail most IF pins are associated with)
1 2 3 4 5 6 7
RESET_OUT# (note 2)
8
Note:
1. The 1.8V supply on the carrier board associated withMPIO pins common to the module must not be enabled unless the
module main 1.8V rail is on. In addition,the carrier board should keepRESET_OUT# lo w until this 1.8V supply is valid.
On the P2597, this is accomplished by connecting the VDD_1V8 supply PGOOD signal to RESET_OUT#.
2. Inactive when both PMIC Reset is inactive (high) & VDD_1V8 PGOOD is active (high)
3. During run time if any module I/O rail is switchedOFF or ON, the following sequences should be performed. Violating
these sequences will result in extra in-rush current during the rail transition.
- OFF Sequence: The associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0 register must be enabled before the
I/O Rail is powered OFF
- ON Sequence. After an I/O Rail is powered ON, the associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0
  
Table 7. Power Up Sequence Timing Relationships
Timing
Parameter
Min
Typ
Max
Units
Notes
t1-2
VDD_IN On to POWER_BTN# Pull-up (PMIC) active
8.8
ms
1
t2-3
VDD_IN On to VIN_PWR_BAD# inactive
54
ms
2
t3-4
VIN_PWR_BAD# inactive to POWER_BTN# active
0
See Notes
ms
3
t4-5
POWER_BTN# active time
50
ms
3
t4-6
POWER_BTN# active to CARRIER_PWR_ON active
38.6
ms
t5-6
Module System Power On to CARRIER_PWR_ON
8
ms
t6-7
CARRIER_PWR_ON active to Carrier Board System Power Enabled
0
6.6
ms
4
t6-8
CARRIER_PWR_ON to On-Module PMIC Reset Inactive
77.4
ms
5
RESET_IN# active time
50
ms
6
Note:
1. Measured from VDD_IN ramp start to POWER_BTN# ramp start. Carrier board dependent.
2. Typical value using NVIDIA P2597, measured from VDD_IN ramp start to VIN_PWR_BAD# inactive start. Carrier board
dependent.
3. User Dependent if POWER_BTN# connected to button. Otherwise, carrier board dependent.
4. Typical value measured using NVIDIA P2597. Carrier board dependent
5. Typical value using P2597. Carrier board dependent.
6. User Dependent if RESET_IN# connected to button. Otherwise, carrier board dependent. Not shown in Power up
sequence figure.

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 13
Figure 4. Power Up Sequence –Auto-Power-On Case (Jetson TX2i in P2597_B04)
CARRIER_PWR_ON
VIN_PWR_BAD#
VDD_IN
Carrier Board VDD_1V8 (note 1)
Jetson module System Power (Main 1.8V
rail most IF pins are associated with)
1 2 3 4 5 6 7
RESET_OUT# (note 2)
8
Note:
1. The 1.8V supply on the carrier board associated withMPIO pins common to the module must not be enabled unless the
module main 1.8V rail is on. In addition,the carrier board should keepRESET_OUT# low until this 1.8V supply is valid.
On the P2597, this is accomplished by connecting the VDD_1V8 supply PGOOD signal to RESET_OUT#.
2. Inactive when both PMIC Reset is inactive (high) & VDD_1V8 PGOOD is active (high)
3. POWER_BTN# not used for this power-up sequence, but if Jetson TX2i is used in P2597_B04 compatible motherboard,
system will power offif POWER_BTN# is asserted (power-button pressed or equivalent) and power-on sequence will
occur again once POWER_BTN# is de-asserted. This is due to the difference in the PMIC power on signal (edge triggered
on Jetson TX2 PMIC & level sensitive on Jetson TX2i. When Jetson TX2i is used in a P2597_C02 compatible carrier board,
logic on the carrier board simulates edge triggered power-on so the power button will function the same as for Jetson
TX2.
4. During run time if any module I/O rail is switchedOFF or ON, the following sequences should be performed. Violating
these sequences will result in extra in-rush current during the rail transition.
- OFF Sequence: The associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0 register must be enabled before the
I/O Rail is powered OFF
- ON Sequence. After an I/O Rail is powered ON, the associated NO_IOPOWER bit in the PMC APBDEV_PMC_NO_IOPOWER_0
  
Table 8. Power Up Sequence Timing Relationships
Timing
Parameter
Min
Typ
Max
Units
Notes
t2-3
VDD_IN On to VIN_PWR_BAD# inactive
54
ms
1
t3-4
VIN_PWR_BAD# inactive to CARRIER_PWR_ON active
38.6
ms
t5-6
Module System Power On to CARRIER_PWR_ON
8
ms
t6-7
CARRIER_PWR_ON active to Carrier Board System Power Enabled
0
6.6
ms
2
t6-8
CARRIER_PWR_ON to On-Module PMIC Reset Inactive
77.4
ms
3
RESET_IN# active time
50
ms
4
Note:
1. Typical value using NVIDIA P2597, measured from VDD_IN ramp start to VIN_PWR_BAD# inactive start. Carrier board
dependent.
2. Typical value measured using NVIDIA P2597. Carrier board dependent
3. Typical value using P2597. Carrier board dependent.
4. User Dependent if RESET_IN# connected to button. Otherwise, carrier board dependent. Not shown in P ower up
sequence figure.

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 14
Figure 5. Power Down Sequence (Controlled Case)
CARRIER_PWR_ON
VIN_PWR_BAD#
VDD_IN
Carrier Board System Power (1.8V
used for pins shared w/Jetson module)
Jetson Module System Power (Main 1.8V
rail most IF pins are associated with)
RESET_OUT#
1 2 3 4 5 6 7 8 9
Table 9. Power Down Sequence Timing Relationships (Controlled Case)
Timing
Parameter
Min
Typ
Max
Units
Notes
t1-2
RESET_OUT# active to CARRIER_PWR_ON inactive
3.76
mS
1
t2-3
CARRIER_PWR_ON inactive to carrier board system power off
0.46
ms
2
t2-4
CARRIER_PWR_ON inactive to the module System Power (main 1.8V rail) Off
1.24
mS
3
Note:
1. Measured from RESET_OUT# active to CARRIER_PWR_ON to inactive ramp down start.
2. Typical value measured using NVIDIA P2597. Measured from CARRIER_PWR_ON to carrier board VDD_1V8 ramp down
start. Carrier board dependent.
3. Typical value measured using NVIDIA P2597. Meas ured from CARRIER_PWR_ON ramp down start to the module main
1.8V ramp down start.
Figure 6. Power Down Sequence (Uncontrolled Power Removal Case)
CARRIER_PWR_ON
VIN_PWR_BAD#
VDD_IN
Carrier Board System Power
Jetson Module System Power
RESET_OUT#
1 2 3 4 5 6 7 8 9
Table 10. Power Down Sequence Timing Relationships (Uncontrolled Power Removal Case)
Timing
Parameter
Min
Typ
Max
Units
Notes
t1
VDD_IN Removed in uncontrolled manner
t2
  
asserted to start uncontrolled power-down sequence.
RESET_OUT# & CARRIER_PWR_ON are driven low via
PMIC sequence soon after. Carrier board power & the
module power begin to ramp down.
Carrier board power (mainly 1.8V rail
associated with interface pins connected to
the module) should ramp down faster so it is
off before the module main 1.8V rail is off.
Removal of the VDD_IN/VDD_MUX supply causes VIN_PWR_BAD# to go active which causes the module to initiate a
controlled shut down. The controlled shut downtakes ~20ms to complete so the internal PMIC supply needs to stay above
~2.9v for>~20ms. The USB0_OTG_ID pin is a pin whichcan be monitored to see the state of the internal PMIC supply level.

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 15
Figure 7. VIN_PWR_BAD# Detection Test Circuit for Uncontrolled Power -down Case
VIN_PWR_BAD#
VDD_IN
~20%
droop
Voltage measured at
USB0_OTG_ID pin
2.9V
>20ms
3.4 Power Discharge
In order to meet the Power Down requirements, discharge circuitry is required. In the figure below the DISCHARGE signal is
generated, based on a transition of the CARRIER_POWER_ON signal or the removal of the main supply (VDD_MUX/VDD_IN).
When DISCHARGE is asserted, VDD_5V0_IO_SYS, VDD_3V3_SYS, VDD_1V8 and VDD_3V3_SLP are forcedto GND in a
controlled manner. Removal of the VDD_MUX supply also causes VIN_PWR_BAD# to go active which causes the module to
initiate a controlled shut down.
Figure 8. Power Discharge
VDD_MUX
10uF
1uF
GS
D
10k
10uF
10k
10M
0
100k
DISCHARGE
VIN_PWR_BAD#
(Jetson Module Pin B8)
47k
VDD_MUX
CARRIER_PWR_ON
(Jetson Module pin A48)
BAT54ALT1
BAT54CW
MMBT
4403
NTR4003
NT1G
NTR4001
NT1G
E
B
C
GS
D
4.7uF
Tol.
100k
100k
GS
D
GS
D
GS
D
GS
D
GS
D
GS
D
100
VDD_5V0_IO_SYS
47
VDD_3V3_SYS
36
VDD_1V8
47
VDD_3V3_SLP
NTR4003
NT1G
NTR4003
NT1G
NTR4003
NT1G
NTR4003
NT1G
VDD_12V_SLP
VDD_5V0_IO_SLP
100
GS
D
470
FDV301N
NTR4003
NT1G
NTR4003
NT1G
BAT54CW
470
75k
VDD_3V3_SLP
VDD_5V0_IO_SYS
Note
The figure above is based on the carrier board reference design. Refer to the latest carrier board reference design
(P2597_B04 or later) for details.
3.5 Module Power-on Type Detection & Control
The followingdescribes whatis required in a carrier board design to support Jetson TX2 and Jetson TX2i in a design that
requires a power button press to power the system on. If a design requires the system to pow eron immediately after the main
pow er supply is connected/enabled, see the “Optional Auto-Power-On Support” section.
Jetson TX2i uses a different PMIC (MAX20024) than Jetson TX2 (MAX77620). Due to the PMIC architecture differences, if the
platform requires a button press, the Power-on mechanism will need to change, from Edge to level triggered. This will require
the carrier boards to detect w hethera Jetson TX2 module or Jetson TX2i module is installed. A Reserved pin on the connector

NVIDIA JetsonTX2/TX2i OEMProduct Design Guide
JETSONTX2/TX2i OEM PRODUCT| DESIGN GUIDE| 20180618 16
whichis floating on Jetson TX2 will be grounded on the Jetson TX2i as a means to differentiate between the twomodule types.
The module power configuration identification pin (MOD_PWR_CFG_ID) resides on the Module Pin B49.
The updated carrier board, designed to support Jetson TX2i as wellas Jetson TX2 will include logic that will use the state of the
MOD_PWR_CFG_ID pinto determine how the POWER_BTN# signalis handled. If the pin is pulled downdue to a Jetson TX2i
module being installed, the POWER_BTN# pinwill be driven to a steady high (ON) or low (OFF) state. If the pin is floating as
would be the case if a Jetson TX2 module is installed, a momentary pulse willbe generated on the POWER_BTN#pinof the
module to initiate a power-onof the module. With either module type, if the system is already powered,a short press of the
pow er button w ill put the system in sleep mode (softw are dependent) if the system is “aw ake,” w ake the system if in sleep mod e,
or cause a forcepower-off if thePower-on button is held low for approximately 8 to 10 seconds.
Figure 9. Power-on Type Detection & Control
MOD_PWR_CFG_ID
POWER_BTN
TPS7A1650
OUTIN
PGEN
DELAY FB_NC
GNDTPAD
SRC0CS25D
VCCLO*VCC
PBOUTPSHOLD
SR* EN/EN*
GND
INT*
PB*
CSRD
VREF
RST*
G
D
S
FET
G
D
S
FET
VDD_19V_IN
VDD_19V_IN
VDD_19V_IN
5V0_AO
5V0_AO
MOD_VIN_EN
WAKE_L
74LVC1G74
VCCSD
QD
CP Q*
GNDRD
5V0_AO
MOD_PWR_ON_STATE_L
5V0_AO
G
D
S
FET
CARRIER_PWR_ON
5V0_AO
5V0_AO
G
D
S
FET
G
D
S
FET
G
D
S
FET
G
D
S
FET
5V0_AO
ONOFF_CTLR_PBOUT
G
D
S
FET
G
D
S
FET
5V0_AO 5V0_AO
5V0_AO
MOD_PWR_CFG_ID_L POWER_ON
5V0_AO
5V0_AO
5V0_AO
5V0_AO
5V0_AO
From Module
Strap (Pin B49)
From Module
Pin (A48)
From Power
Button
From Module
SYS_WAKE# (Pin
B48 – TX2i only)
To main input
power FET enable
circuit (TX2i only).
To Module
POWER_BTN#
Pin (B50)
G
D
S
FET
G
D
S
FET
Note
The figure above is a high-level representation of the connections involved. Details will be provided in a future carrier
board reference design.

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3.6 Power & Voltage Monitoring
3.6.1 Power Monitor
Power monitors are provided on the module. These monitor the main DC, CPU, GPU/SRAM, SOC (CORE) & DDR Supplies.
The monitors will toggle a WARN (warning) output, or a CRIT (critical) output, depending on the pow er “seen” at the sense
resistors and the thresholds set for each supply.
Figure 10. Power Monitor (GPU/SRAM, SOC & WLAN)
Sense
Resistors
GEN1_I2C_SDA
GEN1_I2C_SCL
INA3221AIRGVR
Power Monitor GPU_INA_P

0805
0.1uF
GPU_INA_M
VDD_3V3_SYS
GPU Supply Monitor
SOC Supply Monitor
Wi-Fi Supply Monitor
(Jetson TX1/TX2 Only)
GEN1_I2C
(PU to 3.3V) SOC_INA_P

0805
SOC_INA_M
WIFI_INA_P

0603
WIFI_INA_M
10
10
10
10
10
10
VIN1P
VIN1N
WARN
CRIT
VS
AO
PV
TC
VPU
GND
SCL
SDA
PAD
VIN2P
VIN2N
VIN3P
VIN3N
Tegra GPIO_MDM6
VDD_IN
VDD_IN
VDD_SYS_SOC_IN
(SOC supply input)
VDD_SYS_GPU_IN
(GPU supply input)
VDD_3V8_WIFI_SENSE
VDD_5V0_SYS
1uF
1uF
1uF
100kVDD_1V8
INA_WIFI_THERM_WARN_L
Figure 11. Power Monitor (VDD_IN, CPU & DDR)
Sense
Resistors
GEN1_I2C_SDA
GEN1_I2C_SCL
INA3221AIRGVR
Power Monitor VDD_IN_SENSE

3012
0.1uF
VDD_IN_PREREG_SENSE
VDD_3V3_SYS
VDD_IN Supply Monitor
CPU Supply Monitor
DDR Supply Monitor
GEN1_I2C
(PU to 3.3V) CPU_INA_P

0805
CPU_INA_M
SRAM_INA_P

0603
SRAM_INA_M
10
10
10
10
10
10
VIN1P
VIN1N
WARN
CRIT
VS
AO
PV
TC
VPU
GND
SCL
SDA
PAD
VIN2P
VIN2N
VIN3P
VIN3N
Tegra BATT_OC
VDD_IN_RS
VDD_IN
VDD_SYS_CPU_IN
(CPU supply input)
VDD_IN
VDD_5V0_SD0
(DDR supply input)
VDD_5V0_SYS
1uF
1uF
1uF
100kVDD_1V8
INA_PREREG_THERM_WARN_L
3.6.2 Voltage Monitor
Jetson TX2i
A voltage monitor circuit is implemented on Jetson TX2i to indicate if the main DC input rail, VDD_IN, “droops” below an
acceptable level. The device used willreact quickly and drive VIN_PWR_BAD# active (low) whichwillforcethe poweroff. The
voltage monitor circuit is implemented witha fastvoltage comparator supplied by VDD_IN witha 5V reference. This device has
an open drain active low output whichis pulled low whenthe VDD_IN voltage drops below the selected threshold (8.04V).

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Figure 12. Voltage Monitor Connections
VDD_IN
47.5k
1%
47.4k,1%
VIN_PWR_BAD#
TPS3808G01
TP
SENSE
CT
VCC
MR*
GND RST*
2.49k
1%
100k
1%
RB521CS30L
Note:
The threshold for VDD_IN, determined by the voltage divider components used in the circuitabove is 8.04V.
Jetson TX2
A voltage monitor circuit is implemented on Jetson TX2 to indicate if the main DC input rail, VDD_IN, “droops” below an
acceptable level. The device used willreact quickly and generate an alert to one of the Tegra SOC_THERM capable pins
(VCOMP_ALERT). The voltage monitor circuit is implemented with a fastvoltage comparator supplied by VDD_IN witha 1.8V
(VDD_1V8) referencecommon withthe Tegra IO domain that receives the output signal. This device has an open drain active
low output whichis pulled low whenthe VDD_IN voltage drops below the selected threshold.
Figure 13. Voltage Monitor Connections
VDD_IN
VDD_1V8
VDD_5V0_SYS
34k,1%34k,1%
49.9k
1%
49.9k
1%
110k,1%110k,1% COMP_SOC_THERM* (Tegra VCOMP_ALERT)VOUT
IN_POS
IN_NEG
VCC
VEE
+

VOUT
IN_POS
IN_NEG
VCC
VEE
+

100k100k1.8V
Note:
The threshold for VDD_IN, determined by the voltage divider components used in the cir cuitabove is 5.75V.
3.7 Deep Sleep (SC7)
Jetson TX2/TX2i supports a low powerstate called Deep Sleep or SC7. This can be entered under softwarecontrol,and exited
using various mechanisms, including w ake capable pins that are listed in the table below.
Table 11. Signal Wake Events
Potential Wake Event (Reference Design Signal)
Module Pin Assigned
Wake #
PCIe Wake Request (PEX_WAKE#)
PEX_WAKE#
1
Bluetooth Wake AP (BT2_WAKE_AP Secondary)
GPIO13_BT_WAKE_AP
8
WLAN Wake AP (WIFI_WAKE_AP - Secondary)
GPIO10_WIFI_WAKE_AP
9
Thermal/Over-current Warning
BATT_OC
10
Audio Codec Interrupt (AUD_INT_L)
GPIO20_AUD_INT
12
DP 0 Hot Plug Detect (DP_AUX_CH0_HPD)
DP0_HPD
19
HDMI Consumer Electronic Control (HDMI_CEC)
HDMI_CEC
20
DP 1 Hot Plug Detect (DP_AUX_CH1_HPD)
DP1_HPD
21
Camera Vertical Sync (CAM_VSYNC)
CAM_VSYNC
23
POWER_BTN#
POWER_BTN#
29
Motion Interrupt (MOTION_INT)
GPIO9_MOTION_INT
46
CAN 1 Error (CAN1_ERR)
CAN1_ERR
47
CAN Wake (CAN_WAKE)
CAN_WAKE
48
CAN 0 Error (CAN0_ERR)
CAN0_ERR
49

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Touch Interrupt (TOUCH_INT)
GPIO6_TOUCH_INT
51
USB VBUS Detect (USB_VBUS_DET)
USB0_VBUS_DET
53
GPIO Expansion 0 Interrupt (GPIO_EXP0_INT)
GPIO_EXP0_INT
54
Modem Wake AP (MDM_WAKE_AP)
GPIO16_MDM_WAKE_AP
55
Battery Low (BATLOW#)
BATLOW#
56
GPIO Expansion 1 Interrupt (GPIO_EXP1_INT)
GPIO_EXP1_INT
58
USB Vbus Enable 0 (USB_VBUS_EN0)
USB_VBUS_EN0
61
USB Vbus Enable 1 (USB_VBUS_EN1)
USB_VBUS_EN1
62
Ambient Light Proximity Interrupt (ALS_PROX_INT)
GPIO8_ALS_PROX_INT
63
Modem Coldboot (MDM_COLDBOOT)
GPIO18_MDM_COLDBOOT
64
Force Recovery (FORCE_RECOV#)
FORCE_RECOV#
67
Sleep (SLEEP_L)
SLEEP#
68
Figure 14. Deep Sleep (SC7) Entry/Exit Sequence
CARRIER_PWR_ON
VIN_PWR_BAD#
VDD_IN
RESET_OUT#
SC7 Entry SC7 Exit
CARRIER_STBY#
(Tegra X2SOC_PWR_REQ)
VDD_3V3_SLP
VDD_5V0_SLP
VDD_12V_SLP
VDD_5V0_HDMI_CON
SC7Entry/Exit Trigger
Carrier Board VDD_1V8
3.8 Optional Auto-Power-On Support
Jetson TX2 and Jetson TX2i both optionally support Auto-Power-On. This allows the platform to power on whenVDD_IN is first
powered,instead of waiting for a powerbutton press. For Jetson TX2, to enable this feature, the CHARGER_PRSNT# pin
should be tied to GND. For Jetson TX2i, whichuses a different PMIC, the POWER_BTN# pin needs to be held high. As there
is a pull-up on the module, the POWER_BTN# pin can be left floating on the carrier board. If a design willsupport both Jetson
TX2 and Jetson TX2i and needs to power on without a button press (Auto-Power-On), the CHARGER_PRSNT# pin should be
tied to GND, and the POWER_BTN# pin should be left unconnected.
3.8.1 Jetson TX2 Auto-Power-On Details
This section provides guidance for modifying a carrier board design to power the platform on whenVDD_IN is firstpowered,
instead of waiting fora power button press. In order to power the systemon without a power button, a specific sequence is
required between the time the VDD_IN poweris connected and the CHARGER_PRSNT# pin on the module is driven low. The
CHARGER_PRSNT# pin connects to the module PMIC and requires a minimum delay of 300ms from the point VDD_IN reaches
its minimum level (5.5V) before it can be driven low. Jetson TX2/TX2i includes circuitry on the module to support Auto-Power-
On. In order to enable this feature, the CHARGER_PRSNT# pin should be tied to GND.

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3.8.2 Jetson TX2i Auto-Power-On Details
Jetson TX2i uses a different PMIC than Jetson TX2. The TX2i PMIC has a level sensitive on input, so in order to power
automatically whenthe main power is applied (Auto-Power-On), all that is required is forthe POWER_BTN# pin to be pulled up.
Since this pin is pulled up on the module, it can be left unconnected forAuto-Power-On to be supported.