Nvidia Jetson Orin NX Guide

DG-10931-001_v0.1 | April 2022
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX
Design Guide

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | ii
Document History
DG-10931-001_v0.1
Version Date Description of Change
0.1 April 25, 2022 Preliminary information – Subject to change

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | iii
Table of Contents
Chapter 1. Introduction...........................................................................................1
1.1 References.......................................................................................................................... 1
1.2 Attachments ....................................................................................................................... 1
1.3 Abbreviations and Definitions............................................................................................ 2
Chapter 2. Jetson Orin NX ......................................................................................3
Chapter 3. Jetson Orin NX Boot Considerations.....................................................8
3.1 QSPI Boot............................................................................................................................ 8
3.2 USB Recovery Mode........................................................................................................... 8
Chapter 4. Developer Kit Feature Considerations ..................................................9
4.1 Button Power MCU............................................................................................................. 9
4.2 USB SuperSpeed Hub ...................................................................................................... 10
4.3 Power over Ethernet ........................................................................................................ 10
4.4 TI TXB0108 Level Shifters ................................................................................................ 10
4.5 Features not to be Implemented..................................................................................... 10
Chapter 5. Modular Connector .............................................................................11
5.1 Module Connector Details ............................................................................................... 11
5.2 Module to Mounting Hardware........................................................................................ 11
5.3 Module Installation and Removal.................................................................................... 12
Chapter 6. Power ..................................................................................................13
6.1 Power Supply and Sequencing ........................................................................................ 14
Chapter 7. USB and PCIe......................................................................................19
7.1 USB ................................................................................................................................... 23
7.1.1 USB 2.0 Design Guidelines........................................................................................ 24
7.1.2 USB 3.2 Design Guidelines........................................................................................ 24
7.1.2.1 Common USB Routing Guidelines ..................................................................... 28
7.2 PCIe................................................................................................................................... 29
7.2.1 PCIe Design Guidelines ............................................................................................. 32
Chapter 8. Gigabit Ethernet ..................................................................................37
Chapter 9. Display.................................................................................................39
9.1 eDP and DP....................................................................................................................... 40
9.1.1 eDP and DP Routing Guidelines................................................................................ 41
9.2 HDMI ................................................................................................................................. 46
Chapter 10. MIPI CSI Video Input............................................................................54
10.1 CSI Design Guidelines...................................................................................................... 56

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | iv
Chapter 11. Audio ...................................................................................................58
Chapter 12. Miscellaneous Interfaces....................................................................61
12.1 I2C ................................................................................................................................. 61
12.1.1 I2C Design Guidelines................................................................................................ 62
12.2 SPI ................................................................................................................................. 63
12.2.1 SPI Design Guidelines................................................................................................ 65
12.3 UART ................................................................................................................................. 66
12.4 CAN ................................................................................................................................. 67
12.5 Fan ................................................................................................................................. 68
12.6 Debug................................................................................................................................ 69
Chapter 13. PADS ...................................................................................................70
13.1 Internal Pull-Ups for Dual Voltage Block Pins Power at 1.8V ....................................... 70
13.2 Schmitt Trigger Usage..................................................................................................... 70
13.3 Pins Pulled or Driven High During Power-On ................................................................ 71
Chapter 14. Unused Interface Terminations ..........................................................72
14.1 Unused Multi-Purpose Standard CMOS Pad Interfaces................................................ 72
14.2 Unused Dedicated Special Purpose Pad Interfaces....................................................... 72
Chapter 15. Design and Bring-Up Checklists.........................................................73
Chapter 16. Jetson Orin NX Pin Descriptions.........................................................74
Chapter 17. General Routing Guidelines ................................................................75
17.1 Signal Naming Convention .............................................................................................. 75
17.2 Routing Guidelines Format.............................................................................................. 76
17.3 Signal Routing Conventions............................................................................................. 76
17.4 Routing Guidelines ........................................................................................................... 76
17.4.1 General PCB Routing Guidelines .............................................................................. 77
17.5 Common High-Speed Interface Requirements.............................................................. 78
17.6 Test Points for High-Speed Interfaces............................................................................ 79
Chapter 18. USB SS and Wireless Coexistence......................................................80
18.1 Mitigation Techniques...................................................................................................... 80

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | v
List of Figures
Figure 2-1. Jetson Orin NX Block Diagram..............................................................................4
Figure 5-1. Jetson Orin NX Module Installed in SODIMM Connector...................................12
Figure 5-2. Module to Connector Assembly Diagram ...........................................................12
Figure 6-1. System Power and Control Block Diagram........................................................16
Figure 6-2. System Power and Control Block Diagram........................................................16
Figure 6-3. Power Up Sequence No Power Button – Auto Power On ..................................17
Figure 6-4. Power Up Sequence with Power Button.............................................................17
Figure 6-5. Power Down Initiated by SHUTDOWN_REQ* Assertion.....................................18
Figure 6-6. Power Down Sudden Power Loss .......................................................................18
Figure 7-1. USB Micro B USB Device and Recovery Connection Example..........................23
Figure 7-2. USB SS Type A Host Only Connection Example .................................................23
Figure 7-3. IL/NEXT Plot .........................................................................................................27
Figure 7-4. TDR Plot................................................................................................................27
Figure 7-5. Via Topology..........................................................................................................27
Figure 7-6. Component Order.................................................................................................27
Figure 7-7. Component Placement ........................................................................................28
Figure 7-8. ESD Layout Recommendations...........................................................................28
Figure 7-9. PCIe Root Port Connections Example.................................................................30
Figure 7-10. PCIe Endpoint Connections Example..................................................................31
Figure 7-11. Zig-Zag Routing Example ....................................................................................33
Figure 7-12. Insertion Loss S-Parameter Plot SDD21............................................................34
Figure 7-13. Insertion Loss S-Parameter Plot SDD11............................................................34
Figure 7-14. AC Cap Voiding .....................................................................................................34
Figure 7-15. Connector Voiding ................................................................................................34
Figure 8-1. Jetson Orin NX Ethernet Connections ................................................................37
Figure 8-2. Gigabit Ethernet Magnetics and RJ45 Connections...........................................38
Figure 9-1. DP and eDP Connection Example .......................................................................40
Figure 9-2. DP++ Connection Example ..................................................................................41
Figure 9-3. eDP and DP Differential Main Link Topology .....................................................41
Figure 9-4. S-Parameter Up to HBR2 ....................................................................................44
Figure 9-5. S-Parameter Up to HBR3 ....................................................................................44
Figure 9-6. Via Topology #1 ....................................................................................................45
Figure 9-7. Via Topology #2 ....................................................................................................45
Figure 9-8. HDMI Connection Example..................................................................................46
Figure 9-9. HDMI CLK and Data Topology .............................................................................47
Figure 9-10. IL/FEXT Plot ..........................................................................................................50
Figure 9-11. TDR Plot................................................................................................................50

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | vi
Figure 9-12. HDMI Via Topology ...............................................................................................50
Figure 9-13. Connector Pin Via.................................................................................................51
Figure 9-14. Via No Breakout ...................................................................................................51
Figure 9-15. Via Breakout on Same Layer as Main Trunk ......................................................51
Figure 9-16. Add On Components – Top ..................................................................................51
Figure 9-17. Add On Components – Bottom ............................................................................51
Figure 9-18. AC Cap Void ..........................................................................................................52
Figure 9-19. RPD, Choke, FET Placement ...............................................................................52
Figure 9-20. ESD Footprint .......................................................................................................52
Figure 9-21. ESD Void................................................................................................................52
Figure 9-22. SMT Pad Trace Entering ......................................................................................52
Figure 9-23. SMT Pad Trace Between......................................................................................52
Figure 9-24. Connector Voiding ................................................................................................53
Figure 10-1. CSI Connection Options .......................................................................................55
Figure 10-2. Available Camera Control Pins ...........................................................................56
Figure 11-1. Audio Connection Example..................................................................................59
Figure 12-1. I2C Connections....................................................................................................62
Figure 12-2. SPI Connections ...................................................................................................64
Figure 12-3. Basic SPI Initiator and Target Connections........................................................64
Figure 12-4. SPI Topologies ......................................................................................................65
Figure 12-5. Jetson Orin NX UART Connections .....................................................................66
Figure 12-6. Jetson Orin NX CAN Connections .......................................................................67
Figure 12-7. Jetson Orin NX Fan Connections.........................................................................68
Figure 12-8. Debug UART Connections....................................................................................69
Figure 17-1. General PCB Routing Guidelines ........................................................................77
Figure 17-2. Common Mode Choke..........................................................................................78
Figure 17-3. Serpentine ............................................................................................................79

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | vii
List of Tables
Table 1-1. Abbreviations and Definitions................................................................................2
Table 2-1. Jetson Orin NX Interfaces......................................................................................3
Table 2-2. Jetson Orin NX Connector 260-Pin SO-DIMM Pinout Matrix...............................4
Table 6-1. Jetson Orin NX Power and System Pin Description...........................................13
Table 7-1. Jetson Orin NX USB 2.0 Pin Description.............................................................19
Table 7-2. Jetson Orin NX USB 3.2 and PCIe Pin Description.............................................20
Table 7-3. USB SS and PCIe Lane Mapping .........................................................................22
Table 7-4. USB 2.0 Interface Signal Routing Requirements ...............................................24
Table 7-5. USB 3.2 Interface Signal Routing Requirements ...............................................24
Table 7-6. Orin USB 2.0 Signal Connections ........................................................................28
Table 7-7. Miscellaneous USB 2.0 Signal Connections .......................................................28
Table 7-8. Orin USB 3.2 Signal Connections ........................................................................29
Table 7-9. PCIe Interface Signal Routing Requirements up to Gen4..................................32
Table 7-10. PCIe Signal Connections......................................................................................35
Table 8-1. Jetson Orin NX Gigabit Ethernet Pin Descriptions.............................................37
Table 8-2. Ethernet MDI Interface Signal Routing Requirements ......................................38
Table 8-3. Ethernet Signal Connections...............................................................................38
Table 9-1. Jetson Orin NX eDP, DP, and HDMI Pin Descriptions........................................39
Table 9-2. DP and HDMI Pin Mapping ..................................................................................40
Table 9-3. eDP and DP Main Link Signal Requirements Including DP_AUX......................42
Table 9-4. eDP and DP Signal Connections .........................................................................45
Table 9-5. HDMI Interface Signal Routing Requirements ...................................................47
Table 9-6. HDMI Signal Connections ....................................................................................53
Table 10-1. Jetson Orin NX CSI Pin Descriptions ..................................................................54
Table 10-2. Jetson Orin NX Camera Miscellaneous Pin Descriptions..................................55
Table 10-3. CSI Configurations ...............................................................................................56
Table 10-4. MIPI CSI Interface Signal Routing Requirements ..............................................56
Table 10-5. MIPI CSI Signal Connections ...............................................................................57
Table 10-6. Miscellaneous Camera Connections ..................................................................57
Table 11-1. Jetson Orin NX Audio Pin Descriptions...............................................................58
Table 11-2. I2S Interface Signal Routing Requirements .......................................................59
Table 11-3. Audio Signal Connection......................................................................................60
Table 12-1. Jetson Orin NX I2C Pin Descriptions...................................................................61
Table 12-2. I2C Interface Signal Routing Requirements .......................................................62
Table 12-3. I2C Signal Connections ........................................................................................63
Table 12-4. Jetson Orin NX SPI Pin Descriptions ..................................................................63
Table 12-5. SPI Interface Signal Routing Requirements.......................................................65

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | viii
Table 12-6. SPI Signal Connections........................................................................................65
Table 12-7. Jetson Orin NX UART Pin Descriptions...............................................................66
Table 12-8. UART Signal Connections ....................................................................................67
Table 12-9. Jetson Orin NX CAN Pin Descriptions.................................................................67
Table 12-10. CAN Interface Signal Routing Requirements.....................................................67
Table 12-11. CAN Signal Connections......................................................................................68
Table 12-12. Jetson Orin NX Fan Pin Descriptions..................................................................68
Table 12-13. Jetson Orin NX Debug UART Pin Descriptions...................................................69
Table 12-14. Debug UART Connections....................................................................................69
Table 13-1. Pins Pulled or Driven High by Orin Prior to SYS_RESET* Inactive....................71
Table 13-2. Pins with External Pull-Ups to Supply on before SYS_RESET* Inactive...........71
Table 14-1. Unused MPIO Pins and Pin Group.......................................................................72
Table 17-1. Signal Type Codes ................................................................................................75
Table 17-2. Common High-Speed Interface Requirements..................................................78

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 1
Chapter 1. Introduction
This design guide contains recommendations and guidelines for engineers to follow to create
a product that is optimized to achieve the best performance from the interfaces supported by
the NVIDIA®Jetson™Orin™NX System-on-Module (SOM).
This design guide provides detailed information on the capabilities of the hardware module,
which may differ from supported configurations by provided software. Refer to software
release documentation for information on supported capabilities.
1.1 References
Refer to the following list of documents or models for more information. Use the latest
revision of all documents.
Jetson Orin NX Data Sheet
Orin (SoC) Technical Reference Manual
Jetson Orin NX Module Pinmux
Jetson Orin NX Thermal Design Guide
Jetson Orin NX SCL (Supported Component List)
1.2 Attachments
The following files are attached to this design guide.
Jetson_Orin_NX_Series_Pin_Descriptions.nvxlsx
Jetson_Orin_NX_Series_Schematic_Checklist.nvxlsx
To access the attached files, click the Attachment icon on the left-hand toolbar on this PDF
(using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options
(Open, Save) to retrieve the documents. Excel files with the .nvxlsx extension will need to be
saved as .xlsx.

Introduction
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 2
1.3 Abbreviations and Definitions
Table 1-1 lists the abbreviations that may be used throughout this design and guide and their
definitions.
Table 1-1. Abbreviations and Definitions
Abbreviation
Definition
CAN Controller Area Network
CEC Consumer Electronic Control
CSI Camera Serial Interface
Diff Differential
DP DisplayPort
eDP Embedded DisplayPort
ESD Electrostatic Discharge
EMI Electromagnetic Interference
FET Field Effect Transistor
GPIO General Purpose Input Output
HDCP High-bandwidth Digital Content Protection
HDMI High Definition Multimedia Interface
I2C Inter IC Interface
I2S Inter IC Sound Interface
LDO Low Dropout (voltage regulator)
LPDDR5 Low Power Double Data Rate DRAM, Fifth generation
MDI Medium-Dependent Interface
MIPI Mobile Industry Processor Interface
mm Millimeter
ms Milliseconds
PCIe Peripheral Component Interconnect Express interface
PCM Pulse Code Modulation
PHY Physical Interface (that is, USB PHY)
ps Pico-Seconds
PMIC Power Management Integrated Circuit
RJ45 8P8C modular connector used in Ethernet and other data links
RTC Real Time Clock
SE Single-Ended
SPI Serial Peripheral Interface
TMDS Transition-Minimized Differential Signaling
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 3
Chapter 2. Jetson Orin NX
The Jetson Orin NX resides at the center of the embedded system solution and includes:
Power (Power Sequencer, Regulators, and so on)
DRAM (LPDDR5)
Gigabit Ethernet Controller
QSPI NOR (Boot device)
In addition, a wide range of interfaces are available at the main connector for use on the
carrier board as shown in Table 2-1 and Figure 2-1.
Table 2-1. Jetson Orin NX Interfaces
Category Function Category Function
USB USB 2.0 interface (3x) LAN Gigabit ethernet
USB 3.2 (3x) I2C 4x
PCIe PCIe (1 x1, 1 x2 or 2 x1, and 1 x4).
Note: NVMe off PCIe used for storage.
UART 3x
Camera CSI (8 lanes 2 x4 or 4 x2) SPI 2x
Control, clock CAN 1x
Display HDMI/eDP/DP (1x) Fan FAN PWM and tach input
DP_AUX/HPD, CEC Debug UART
Audio I2S interface (2x) System Power control, reset, alerts
Initiator clock Power Main input and battery back-up for RTC

Jetson Orin NX
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 4
Figure 2-1. Jetson Orin NX Block Diagram
Jetson Orin NX
Gig abi t
Ethernet
LPDDR5
VDD_IN
(5V-20V)
USB 2.0 3x
GBE_M DI
I2S 2x
I2C 1x–1.8V
CSI: 2 x4 or 4 x2
[E]DP/HDMI 1x
USB 3.2 3x
SPI 2x
I2C 3x–3.3V
PCIe x1 + x2 + x4
CAM MCLK 2x
Power
Subsystem
CPU /GP U & Co re R egs
Orin
Voltage Mo nitors
UART 3x
CAN 1x
AUDIO MCLK
QS PI N OR
General Purpose
Clock s 2x
PWM 3x
DIGITAL MIC
Power Seq.
DP_AUX/DDC
HPD, CEC
PMIC_BBAT
NVMe for
St orage
Table 2-2. Jetson Orin NX Connector 260-Pin SO-DIMM Pinout Matrix
Module Signal Name Jetson Orin NX
Function
Pin # Pin # Module Signal Name Jetson Orin NX
Function
GND
GND
1
2
GND
GND
CSI1_D0_N
CSI1_D0_N
3
4
CSI0_D0_N
CSI0_D0_N
CSI1_D0_P
CSI1_D0_P
5
6
CSI0_D0_P
CSI0_D0_P
GND
GND
7
8
GND
GND
CSI1_CLK_N
CSI1_CLK_N
9
10
CSI0_CLK_N
CSI0_CLK_N
CSI1_CLK_P
CSI1_CLK_P
11
12
CSI0_CLK_P
CSI0_CLK_P
GND
GND
13
14
GND
GND
CSI1_D1_N
CSI1_D1_N
15
16
CSI0_D1_N
CSI0_D1_N
CSI1_D1_P
CSI1_D1_P
17
18
CSI0_D1_P
CSI0_D1_P
GND
GND
19
20
GND
GND
CSI3_D0_N
CSI3_D0_N
21
22
CSI2_D0_N
CSI2_D0_N
CSI3_D0_P
CSI3_D0_P
23
24
CSI2_D0_P
CSI2_D0_P
GND
GND
25
26
GND
GND
CSI3_CLK_N
CSI3_CLK_N
27
28
CSI2_CLK_N
CSI2_CLK_N
CSI3_CLK_P
CSI3_CLK_P
29
30
CSI2_CLK_P
CSI2_CLK_P
GND
GND
31
32
GND
GND
CSI3_D1_N
CSI3_D1_N
33
34
CSI2_D1_N
CSI2_D1_N
CSI3_D1_P
CSI3_D1_P
35
36
CSI2_D1_P
CSI2_D1_P
GND
GND
37
38
GND
GND
DP0_TXD0_N
USBSS1_RX_N
39
40
CSI4_D2_N
PCIE2_RX0_N

Jetson Orin NX
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 5
Module Signal Name
Jetson Orin NX
Function
Pin #
Pin #
Module Signal Name
Jetson Orin NX
Function
DP0_TXD0_P
USBSS1_RX_P
41
42
CSI4_D2_P
PCIE2_RX0_P
GND
GND
43
44
GND
GND
DP0_TXD1_N
USBSS1_TX_N
45
46
CSI4_D0_N
PCIE2_TX0_N
DP0_TXD1_P
USBSS1_TX_P
47
48
CSI4_D0_P
PCIE2_TX0_P
GND
GND
49
50
GND
GND
DP0_TXD2_N
USBSS2_RX_N
51
52
CSI4_CLK_N
PCIE2_CLK_N
DP0_TXD2_P
USBSS2_RX_P
53
54
CSI4_CLK_P
PCIE2_CLK_P
GND
GND
55
56
GND
GND
DP0_TXD3_N
USBSS2_TX_N
57
58
CSI4_D1_N
PCIE2_RX1_N
(PCIE3_RX0_N)
DP0_TXD3_P
USBSS2_TX_P
59
60
CSI4_D1_P
PCIE2_RX1_P
(PCIE3_TX0_P)
GND
GND
61
62
GND
GND
DP1_TXD0_N
DP1_TXD0_N
63
64
CSI4_D3_N
PCIE2_TX1_N
(PCIE3_TX0_N)
DP1_TXD0_P
DP1_TXD0_P
65
66
CSI4_D3_P
PCIE2_TX1_P
(PCIE3_TX0_P)
GND
GND
67
68
GND
GND
DP1_TXD1_N
DP1_TXD1_N
69
70
DSI_D0_N
RSVD
DP1_TXD1_P
DP1_TXD1_P
71
72
DSI_D0_P
RSVD
GND
GND
73
74
GND
GND
DP1_TXD2_N
DP1_TXD2_N
75
76
DSI_CLK_N
RSVD
DP1_TXD2_P
DP1_TXD2_P
77
78
DSI_CLK_P
RSVD
GND
GND
79
80
GND
GND
DP1_TXD3_N
DP1_TXD3_N
81
82
DSI_D1_N
RSVD
DP1_TXD3_P
DP1_TXD3_P
83
84
DSI_D1_P
RSVD
GND
GND
85
86
GND
GND
GPIO00
GPIO00
87
88
DP0_HPD
RSVD
SPI0_MOSI
SPI0_MOSI
89
90
DP0_AUX_N
RSVD
SPI0_SCK
SPI0_SCK
91
92
DP0_AUX_P
RSVD
SPI0_MISO
SPI0_MISO
93
94
HDMI_CEC
HDMI_CEC
SPI0_CS0*
SPI0_CS0*
95
96
DP1_HPD
DP1_HPD
SPI0_CS1*
SPI0_CS1*
97
98
DP1_AUX_N
DP1_AUX_N
UART0_TXD
UART0_TXD
99
100
DP1_AUX_P
DP1_AUX_P
UART0_RXD
UART0_RXD
101
102
GND
GND
UART0_RTS*
UART0_RTS*
103
104
SPI1_MOSI
SPI1_MOSI
UART0_CTS*
UART0_CTS*
105
106
SPI1_SCK
SPI1_SCK
GND
GND
107
108
SPI1_MISO
SPI1_MISO
USB0_D_N
USB0_D_N
109
110
SPI1_CS0*
SPI1_CS0*
USB0_D_P
USB0_D_P
111
112
SPI1_CS1*
SPI1_CS1*
GND
GND
113
114
CAM0_PWDN
CAM0_PWDN
USB1_D_N
USB1_D_N
115
116
CAM0_MCLK
CAM0_MCLK
USB1_D_P
USB1_D_P
117
118
GPIO01
GPIO01
GND
GND
119
120
CAM1_PWDN
CAM1_PWDN
USB2_D_N
USB2_D_N
121
122
CAM1_MCLK
CAM1_MCLK
USB2_D_P
USB2_D_P
123
124
GPIO02
GPIO02
GND
GND
125
126
GPIO03
GPIO03
GPIO04
GPIO04
127
128
GPIO05
GPIO05
GND
GND
129
130
GPIO06
GPIO06
PCIE0_RX0_N
PCIE0_RX0_N
131
132
GND
GND
PCIE0_RX0_P
PCIE0_RX0_P
133
134
PCIE0_TX0_N
PCIE0_TX0_N
GND
GND
135
136
PCIE0_TX0_P
PCIE0_TX0_P
PCIE0_RX1_N
PCIE0_RX1_N
137
138
GND
GND

Jetson Orin NX
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 6
Module Signal Name
Jetson Orin NX
Function
Pin #
Pin #
Module Signal Name
Jetson Orin NX
Function
PCIE0_RX1_P
PCIE0_RX1_P
139
140
PCIE0_TX1_N
PCIE0_TX1_N
GND
GND
141
142
PCIE0_TX1_P
PCIE0_TX1_P
CAN_RX
CAN_RX
143
144
GND
GND
KEY
KEY
KEY
KEY
KEY
KEY
CAN_TX
CAN_TX
145
146
GND
GND
GND
GND
147
148
PCIE0_TX2_N
PCIE0_TX2_N
PCIE0_RX2_N
PCIE0_RX2_N
149
150
PCIE0_TX2_P
PCIE0_TX2_P
PCIE0_RX2_P
PCIE0_RX2_P
151
152
GND
GND
GND
GND
153
154
PCIE0_TX3_N
PCIE0_TX3_N
PCIE0_RX3_N
PCIE0_RX3_N
155
156
PCIE0_TX3_P
PCIE0_TX3_P
PCIE0_RX3_P
PCIE0_RX3_P
157
158
GND
GND
GND
GND
159
160
PCIE0_CLK_N
PCIE0_CLK_N
USBSS_RX_N
USBSS0_RX_N
161
162
PCIE0_CLK_P
PCIE0_CLK_P
USBSS_RX_P
USBSS0_RX_P
163
164
GND
GND
GND
GND
165
166
USBSS_TX_N
USBSS0_TX_N
PCIE1_RX0_N
PCIE1_RX0_N
167
168
USBSS_TX_P
USBSS0_TX_P
PCIE1_RX0_P
PCIE1_RX0_P
169
170
GND
GND
GND
GND
171
172
PCIE1_TX0_N
PCIE1_TX0_N
PCIE1_CLK_N
PCIE1_CLK_N
173
174
PCIE1_TX0_P
PCIE1_TX0_P
PCIE1_CLK_P
PCIE1_CLK_P
175
176
GND
GND
GND
GND
177
178
MOD_SLEEP*
MOD_SLEEP*
PCIE_WAKE*
PCIE_WAKE*
179
180
PCIE0_CLKREQ*
PCIE0_CLKREQ*
PCIE0_RST*
PCIE0_RST*
181
182
PCIE1_CLKREQ*
PCIE1_CLKREQ*
PCIE1_RST*
PCIE1_RST*
183
184
GBE_MDI0_N
GBE_MDI0_N
I2C0_SCL
I2C0_SCL
185
186
GBE_MDI0_P
GBE_MDI0_P
I2C0_SDA
I2C0_SDA
187
188
GBE_LED_LINK
GBE_LED_LINK
I2C1_SCL
I2C1_SCL
189
190
GBE_MDI1_N
GBE_MDI1_N
I2C1_SDA
I2C1_SDA
191
192
GBE_MDI1_P
GBE_MDI1_P
I2S0_DOUT
I2S0_DOUT
193
194
GBE_LED_ACT
GBE_LED_ACT
I2S0_DIN
I2S0_DIN
195
196
GBE_MDI2_N
GBE_MDI2_N
I2S0_FS
I2S0_FS
197
198
GBE_MDI2_P
GBE_MDI2_P
I2S0_SCLK
I2S0_SCLK
199
200
GND
GND
GND
GND
201
202
GBE_MDI3_N
GBE_MDI3_N
UART1_TXD
UART1_TXD
203
204
GBE_MDI3_P
GBE_MDI3_P
UART1_RXD
UART1_RXD
205
206
GPIO07
GPIO07
UART1_RTS*
UART1_RTS*
207
208
GPIO08
GPIO08
UART1_CTS*
UART1_CTS*
209
210
CLK_32K_OUT
CLK_32K_OUT
GPIO09
GPIO09
211
212
GPIO10
GPIO10
CAM_I2C_SCL
CAM_I2C_SCL
213
214
FORCE_RECOVERY*
FORCE_RECOVERY*
CAM_I2C_SDA
CAM_I2C_SDA
215
216
GPIO11
GPIO11
GND
MODULE_ID
217
218
GPIO12
GPIO12
SDMMC_DAT0
PCIE2_RST*
219
220
I2S1_DOUT
I2S1_DOUT
SDMMC_DAT1
PCIE2_CLKREQ*
221
222
I2S1_DIN
I2S1_DIN
SDMMC_DAT2
PCIE3_RST*
223
224
I2S1_FS
I2S1_FS
SDMMC_DAT3
PCIE3_CLKREQ*
225
226
I2S1_SCLK
I2S1_SCLK
SDMMC_CMD
PCIE3_CLK_N
227
228
GPIO13
GPIO13
SDMMC_CLK
PCIE3_CLK_P
229
230
GPIO14
GPIO14
GND
GND
231
232
I2C2_SCL
I2C2_SCL
SHUTDOWN_REQ*
SHUTDOWN_REQ*
233
234
I2C2_SDA
I2C2_SDA
PMIC_BBAT
PMIC_BBAT
235
236
UART2_TXD
UART2_TXD
POWER_EN
POWER_EN
237
238
UART2_RXD
UART2_RXD
SYS_RESET*
SYS_RESET*
239
240
SLEEP/WAKE*
SLEEP/WAKE*
GND
GND
241
242
GND
GND
GND
GND
243
244
GND
GND
GND
GND
245
246
GND
GND
GND
GND
247
248
GND
GND

Jetson Orin NX
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 7
Module Signal Name
Jetson Orin NX
Function
Pin #
Pin #
Module Signal Name
Jetson Orin NX
Function
GND
GND
249
250
GND
GND
VDD_IN
VDD
251
252
VDD_IN
VDD
VDD_IN
VDD
253
254
VDD_IN
VDD
VDD_IN
VDD
255
256
VDD_IN
VDD
VDD_IN
VDD
257
258
VDD_IN
VDD
VDD_IN
VDD
259
260
VDD_IN
VDD
Legend
Ground Power Different Functionality

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 8
Chapter 3. Jetson Orin NX Boot
Considerations
The Jetson Orin NX can boot in two ways:
QSPI – normal operation
USB Recovery Mode – development and production programming
3.1 QSPI Boot
The Jetson Orin NX module normally boots from QSPI. However, the QSPI’s 64 MB of storage
is not expected to contain all the files for a fully functioning system. Secondary storage needs
to be provided through NVMe using PCIe.
3.2 USB Recovery Mode
USB Recovery mode provides an alternate boot device (USB). In this mode, the system is
connected to a host system and boots over USB. This is used when a new image needs to be
flashed. To enter USB recovery mode, the FORCE_RECOVERY* pin is held low when SYS_RESET*
goes high which can be when the system is powered on or SYS_RESET* is asserted after the
system is powered on.
FORCE_RECOVERY* is the SoC RCM0 strap
Only USB0_D_N/P supports USB Recovery Mode
No other signals are required or supported for entering Force Recovery mode. Neither VBus
or USB ID detection is needed. If the force recovery strap is held low coming out of reset,
Jetson Orin NX will configure USB0 as a device and enter recovery mode.
See the USB section (Section 7.1) for an example figure that shows USB0 connected to a USB
Micro B connector.

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 9
Chapter 4. Developer Kit Feature
Considerations
The Jetson Orin NX module is compatible with the NVIDIA Jetson Xavier NX Developer Kit. The
Jetson Xavier NX Developer Kit carrier board design files are provided as a reference design.
Not all the Jetson Orin NX features can be used on the Jetson Xavier NX Developer Kit. In
addition, there are some features on the developer kit that are not supported when used with
the Jetson Orin NX module. This chapter describes details necessary for designers to know to
replicate certain features if desired. In addition, aspects of the design that are specific to the
NVIDIA developer kit usage but not useful or supported on a custom carrier board are also
identified.
Most of the features implemented on the reference design can be duplicated by copying the
connections from the reference design. Some of the following features have aspects that
would require additional information.
Button Power MCU (EFM8SB10F2G)
USB SuperSpeed Hub (Realtek RTS5420)
Power over Ethernet (PoE)
TI TXB0108 level shifters
ID EEPROM (Not to be copied from reference design)
4.1 Button Power MCU
The reference design implements a button power MCU (EFM8SB10F2G). This device is
programmed with firmware that is available on the Jetson Download Center. The posting is
titled
Jetson AGX Xavier and Jetson Xavier NX Power Button Supervisor Firmware . The
connections used on the reference design must be followed exactly and the firmware provided
must be used to ensure correct functionality.

Developer Kit Feature Considerations
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 10
4.2 USB SuperSpeed Hub
The USB SS hub design uses a Realtek RTS5420 device. The hub circuit includes a SPI FLASH
device which holds configuration information. A design intending to duplicate the reference
design hub implementation should include the same SPI FLASH programmed to match, or the
hub should be customized with fuses with the same settings. The configuration in the SPI
FLASH includes the following:
Power enables (DPS1/2/3/4_PWR) set to be active high
Charging feature disabled
SSC valid
4.3 Power over Ethernet
The reference design includes a 4-pin Power over Ethernet (PoE) header (J19) which brings
out the VC power pins of the Ethernet connector. To use this alternate PoE power mechanism
to power a custom carrier board, the design would require a PoE PD controller or converter to
take the high voltage PoE supply (38V-60V) and convert it to the correct voltage for the custom
carrier board.
4.4 TI TXB0108 Level Shifters
The reference design uses these level shifters to shift many of the signals going to the 40-pin
header from 1.8V to 3.3V. The design of these level shifters supports bidirectional signaling
without the use of a direction signal but has some side effects that should be considered. See
the
Jetson Nano Developer Kit 40-Pin Expansion Header GPIO Usage Considerations
Applications Note
for details.
4.5 Features not to be Implemented
The reference design features that should not be copied as they are not required or useful for
a custom carrier board design. The ID EEPROM (P3509 - U17) is a feature that is used for
NVIDIA internal purposes, but not recommended on a custom design. If a similar functionality
is desired for a custom design, avoid using address 7’h57 on the I2C2 interface.

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 11
Chapter 5. Modular Connector
5.1 Module Connector Details
Jetson Orin NX modules connect to the carrier board using a 260-pin SODIMM connector. The
mating connector used on the reference design carrier board will be listed in the Jetson Orin
NX SCL (Supported Components List). The connector listed in the Jetson Xavier NX SCL is the
same, so that document can be referenced. This connector is a DDR4 SODIMM, 260-pin, right-
angle, standard key type. The full height of the connector is 9.2 mm. Refer to the connector
specification for details. Other heights are available.
5.2 Module to Mounting Hardware
The Jetson Orin NX module is installed in the SODIMM connector which has latching
mechanisms to hold the board in place. In addition, it is required that the module is mounted
to the main carrier board PCB using metal standoffs and screws (or equivalent), both for
mechanical integrity and to provide additional grounding points. The recommended standoffs
used on the carrier board are threaded standoffs that are hex, 4.5 mm widths (narrow
diameter) × 6.57 ± 0.1 mm length with M2.5 threads (or equivalent). The screws that match the
described standoffs are M2.5 × 3.7 mm, pad head.
Other SODIMM connector heights are available. If a different height connector is used, the
standoff height will have to be adjusted accordingly to account for the difference in height from
main PCB to module PCB.

Modular Connector
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 12
Figure 5-1. Jetson Orin NX Module Installed in SODIMM Connector
Standoffs
SO-DIMM
Connector
Jetson Orin
NX Module
(Envelop view)
Mounting Screws
5.3 Module Installation and Removal
To install the Jetson Orin NX module correctly, follow the sequence and mounting hardware
instructions:
Here are some suggested assembly guidelines.
1. Assemble any required thermal solution on the module.
2. Install the module
a). Start with baseboard that has suitable standoff to match SODIMM connector height.
b). Insert module fully at an angle of 25-35 degree into the SODIMM connector.
c). Arc down the module board until the SODIMM connector latch engages.
d). Secure the module to the baseboard with screws into the standoff or spacer (shown in
Figure 5-2).
Figure 5-2. Module to Connector Assembly Diagram
Standoff
Mounting Screw
To remove the module correctly, follow the installation sequence in reverse.