NXP Semiconductors K22F series User manual

K22F Sub-Family Reference Manual
Supports: MK22FN512VDC12, MK22FN512VLL12,
MK22FN512VLH12, MK22FN512VMP12, MK22FN512VFX12,
MK22FN512CAP12R, MK22FN512CBP12R, MK22FN256CAP12R
Document Number: K22P121M120SF7RM
Rev. 4, 08/2016

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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................47
1.1.1 Purpose.........................................................................................................................................................47
1.1.2 Audience...................................................................................................................................................... 47
1.2 Conventions.................................................................................................................................................................. 47
1.2.1 Numbering systems......................................................................................................................................47
1.2.2 Typographic notation................................................................................................................................... 48
1.2.3 Special terms................................................................................................................................................48
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................49
2.2 Module Functional Categories......................................................................................................................................49
2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................50
2.2.2 System Modules...........................................................................................................................................51
2.2.3 Memories and Memory Interfaces............................................................................................................... 52
2.2.4 Clocks...........................................................................................................................................................52
2.2.5 Security and Integrity modules.................................................................................................................... 53
2.2.6 Analog modules........................................................................................................................................... 53
2.2.7 Timer modules............................................................................................................................................. 53
2.2.8 Communication interfaces........................................................................................................................... 54
2.2.9 Human-machine interfaces.......................................................................................................................... 55
2.3 Orderable part numbers.................................................................................................................................................55
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................57
3.2 Core modules................................................................................................................................................................ 57
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................57
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3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................59
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................65
3.2.4 FPU Configuration.......................................................................................................................................66
3.2.5 JTAG Controller Configuration...................................................................................................................66
3.3 System modules............................................................................................................................................................ 67
3.3.1 SIM Configuration....................................................................................................................................... 67
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................68
3.3.3 PMC Configuration......................................................................................................................................68
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................69
3.3.5 MCM Configuration.................................................................................................................................... 71
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................71
3.3.7 Peripheral Bridge Configuration..................................................................................................................73
3.3.8 DMA request multiplexer configuration......................................................................................................74
3.3.9 DMA Controller Configuration................................................................................................................... 77
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................78
3.3.11 Watchdog Configuration..............................................................................................................................80
3.4 Clock modules.............................................................................................................................................................. 81
3.4.1 MCG Configuration..................................................................................................................................... 81
3.4.2 OSC Configuration...................................................................................................................................... 82
3.4.3 RTC OSC configuration...............................................................................................................................83
3.5 Memories and memory interfaces.................................................................................................................................84
3.5.1 Flash Memory Configuration.......................................................................................................................84
3.5.2 Flash Memory Controller Configuration..................................................................................................... 87
3.5.3 SRAM Configuration...................................................................................................................................87
3.5.4 System Register File Configuration.............................................................................................................89
3.5.5 VBAT Register File Configuration..............................................................................................................90
3.5.6 EzPort Configuration................................................................................................................................... 91
3.5.7 FlexBus Configuration.................................................................................................................................92
3.6 Security......................................................................................................................................................................... 95
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3.6.1 CRC Configuration...................................................................................................................................... 95
3.6.2 RNG Configuration......................................................................................................................................96
3.7 Analog...........................................................................................................................................................................97
3.7.1 16-bit SAR ADC Configuration.................................................................................................................. 97
3.7.2 CMP Configuration......................................................................................................................................104
3.7.3 12-bit DAC Configuration........................................................................................................................... 106
3.7.4 VREF Configuration....................................................................................................................................107
3.8 Timers........................................................................................................................................................................... 108
3.8.1 PDB Configuration...................................................................................................................................... 108
3.8.2 FlexTimer Configuration............................................................................................................................. 111
3.8.3 PIT Configuration........................................................................................................................................ 117
3.8.4 Low-power timer configuration...................................................................................................................118
3.8.5 RTC configuration....................................................................................................................................... 120
3.9 Communication interfaces............................................................................................................................................ 121
3.9.1 Universal Serial Bus (USB) FS Subsystem................................................................................................. 121
3.9.2 SPI configuration......................................................................................................................................... 126
3.9.3 I2C Configuration........................................................................................................................................ 130
3.9.4 UART Configuration................................................................................................................................... 131
3.9.5 LPUART configuration................................................................................................................................133
3.9.6 I2S configuration..........................................................................................................................................134
3.10 Human-machine interfaces........................................................................................................................................... 137
3.10.1 GPIO configuration......................................................................................................................................137
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................139
4.2 System memory map.....................................................................................................................................................139
4.2.1 Aliased bit-band regions.............................................................................................................................. 141
4.2.2 Flash Access Control Introduction...............................................................................................................142
4.3 Flash Memory Map.......................................................................................................................................................142
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4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................143
4.4 SRAM memory map.....................................................................................................................................................143
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................144
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................144
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................ 144
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................148
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................151
5.2 Programming model......................................................................................................................................................151
5.3 High-Level device clocking diagram............................................................................................................................151
5.4 Clock definitions...........................................................................................................................................................152
5.4.1 Device clock summary.................................................................................................................................153
5.5 Internal clocking requirements..................................................................................................................................... 156
5.5.1 Clock divider values after reset....................................................................................................................157
5.5.2 VLPR mode clocking...................................................................................................................................157
5.6 Clock Gating.................................................................................................................................................................158
5.7 Module clocks...............................................................................................................................................................158
5.7.1 PMC 1-kHz LPO clock................................................................................................................................160
5.7.2 IRC 48MHz clock........................................................................................................................................ 160
5.7.3 WDOG clocking.......................................................................................................................................... 161
5.7.4 Debug trace clock.........................................................................................................................................161
5.7.5 PORT digital filter clocking.........................................................................................................................162
5.7.6 LPTMR clocking..........................................................................................................................................162
5.7.7 RTC_CLKOUT and CLKOUT32K clocking..............................................................................................163
5.7.8 USB FS OTG Controller clocking...............................................................................................................164
5.7.9 UART clocking............................................................................................................................................165
5.7.10 LPUART0 clocking..................................................................................................................................... 165
5.7.11 I2S/SAI clocking..........................................................................................................................................166
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Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................169
6.2 Reset..............................................................................................................................................................................170
6.2.1 Power-on reset (POR).................................................................................................................................. 170
6.2.2 System reset sources.................................................................................................................................... 170
6.2.3 MCU Resets................................................................................................................................................. 174
6.2.4 Reset Pin ..................................................................................................................................................... 175
6.2.5 Debug resets.................................................................................................................................................176
6.3 Boot...............................................................................................................................................................................177
6.3.1 Boot sources.................................................................................................................................................177
6.3.2 Boot options................................................................................................................................................. 177
6.3.3 FOPT boot options.......................................................................................................................................178
6.3.4 Boot sequence.............................................................................................................................................. 179
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................181
7.2 Clocking modes............................................................................................................................................................ 181
7.2.1 Partial Stop...................................................................................................................................................181
7.2.2 DMA Wakeup..............................................................................................................................................182
7.2.3 Compute Operation......................................................................................................................................183
7.2.4 Peripheral Doze............................................................................................................................................184
7.2.5 Clock Gating................................................................................................................................................ 185
7.3 Power Modes Description.............................................................................................................................................185
7.4 Entering and exiting power modes............................................................................................................................... 187
7.5 Power mode transitions.................................................................................................................................................188
7.6 Power modes shutdown sequencing............................................................................................................................. 189
7.7 Flash Program Restrictions...........................................................................................................................................190
7.8 Module Operation in Low Power Modes......................................................................................................................190
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Section number Title Page
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................195
8.2 Flash Security............................................................................................................................................................... 195
8.3 Security Interactions with other Modules.....................................................................................................................196
8.3.1 Security interactions with FlexBus.............................................................................................................. 196
8.3.2 Security Interactions with EzPort................................................................................................................ 196
8.3.3 Security Interactions with Debug.................................................................................................................196
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................199
9.1.1 References....................................................................................................................................................201
9.2 The Debug Port.............................................................................................................................................................201
9.2.1 JTAG-to-SWD change sequence................................................................................................................. 202
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................202
9.3 Debug Port Pin Descriptions.........................................................................................................................................203
9.4 System TAP connection................................................................................................................................................203
9.4.1 IR Codes.......................................................................................................................................................203
9.5 JTAG status and control registers.................................................................................................................................204
9.5.1 MDM-AP Control Register..........................................................................................................................205
9.5.2 MDM-AP Status Register............................................................................................................................ 207
9.6 Debug Resets................................................................................................................................................................ 208
9.7 AHB-AP........................................................................................................................................................................209
9.8 ITM............................................................................................................................................................................... 209
9.9 Core Trace Connectivity...............................................................................................................................................210
9.10 TPIU..............................................................................................................................................................................210
9.11 DWT............................................................................................................................................................................. 210
9.12 Debug in Low Power Modes........................................................................................................................................ 211
9.12.1 Debug Module State in Low Power Modes.................................................................................................211
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9.13 Debug & Security......................................................................................................................................................... 212
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................213
10.2 Signal Multiplexing Integration....................................................................................................................................213
10.2.1 Port control and interrupt module features.................................................................................................. 214
10.2.2 Clock gating................................................................................................................................................. 215
10.2.3 Signal multiplexing constraints....................................................................................................................215
10.3 Pinout............................................................................................................................................................................215
10.3.1 K22F Signal Multiplexing and Pin Assignments.........................................................................................215
10.3.2 K22 Pinouts..................................................................................................................................................222
10.4 Module Signal Description Tables................................................................................................................................228
10.4.1 Core Modules...............................................................................................................................................228
10.4.2 System Modules...........................................................................................................................................229
10.4.3 Clock Modules............................................................................................................................................. 229
10.4.4 Memories and Memory Interfaces............................................................................................................... 230
10.4.5 Analog..........................................................................................................................................................233
10.4.6 Timer Modules.............................................................................................................................................234
10.4.7 Communication Interfaces........................................................................................................................... 235
10.4.8 Human-Machine Interfaces (HMI).............................................................................................................. 238
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................239
11.2 Overview.......................................................................................................................................................................239
11.2.1 Features........................................................................................................................................................ 239
11.2.2 Modes of operation...................................................................................................................................... 240
11.3 External signal description............................................................................................................................................241
11.4 Detailed signal description............................................................................................................................................241
11.5 Memory map and register definition.............................................................................................................................241
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11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................248
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................251
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................251
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 252
11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................252
11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................253
11.5.7 Digital Filter Width Register (PORTx_DFWR).......................................................................................... 253
11.6 Functional description...................................................................................................................................................254
11.6.1 Pin control....................................................................................................................................................254
11.6.2 Global pin control........................................................................................................................................ 255
11.6.3 External interrupts........................................................................................................................................255
11.6.4 Digital filter..................................................................................................................................................256
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................259
12.1.1 Features........................................................................................................................................................ 259
12.2 Memory map and register definition.............................................................................................................................260
12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 261
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................263
12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................. 264
12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................. 266
12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................. 269
12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................. 271
12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................. 273
12.2.8 System Device Identification Register (SIM_SDID)...................................................................................275
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................277
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................279
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................281
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................284
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12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................285
12.2.14 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................287
12.2.15 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 288
12.2.16 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 289
12.2.17 Unique Identification Register High (SIM_UIDH)..................................................................................... 290
12.2.18 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................290
12.2.19 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 291
12.2.20 Unique Identification Register Low (SIM_UIDL)...................................................................................... 291
12.3 Functional description...................................................................................................................................................291
Chapter 13
Kinetis Flashloader
13.1 Chip-Specific Information............................................................................................................................................ 293
13.2 Introduction...................................................................................................................................................................293
13.3 Functional Description..................................................................................................................................................295
13.3.1 Memory Maps..............................................................................................................................................295
13.3.2 Start-up Process............................................................................................................................................295
13.3.3 Clock Configuration.....................................................................................................................................296
13.3.4 Flashloader Protocol.................................................................................................................................... 296
13.3.5 Flashloader Packet Types.............................................................................................................................301
13.3.6 Flashloader Command API..........................................................................................................................308
13.4 Peripherals Supported................................................................................................................................................... 327
13.4.1 I2C Peripheral.............................................................................................................................................. 327
13.4.2 SPI Peripheral.............................................................................................................................................. 329
13.4.3 UART Peripheral......................................................................................................................................... 331
13.4.4 USB peripheral.............................................................................................................................................334
13.5 Get/SetProperty Command Properties..........................................................................................................................336
13.5.1 Property Definitions.....................................................................................................................................338
13.6 Kinetis Flashloader Status Error Codes........................................................................................................................ 339
Chapter 14
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Reset Control Module (RCM)
14.1 Introduction...................................................................................................................................................................341
14.2 Reset memory map and register descriptions............................................................................................................... 341
14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 342
14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 343
14.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 345
14.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 346
14.2.5 Mode Register (RCM_MR)......................................................................................................................... 347
14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................348
14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................349
Chapter 15
System Mode Controller (SMC)
15.1 Introduction...................................................................................................................................................................351
15.2 Modes of operation....................................................................................................................................................... 351
15.3 Memory map and register descriptions.........................................................................................................................353
15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................354
15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................355
15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................357
15.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 358
15.4 Functional description...................................................................................................................................................359
15.4.1 Power mode transitions................................................................................................................................359
15.4.2 Power mode entry/exit sequencing.............................................................................................................. 362
15.4.3 Run modes....................................................................................................................................................364
15.4.4 Wait modes.................................................................................................................................................. 366
15.4.5 Stop modes...................................................................................................................................................366
15.4.6 Debug in low power modes......................................................................................................................... 369
Chapter 16
Power Management Controller (PMC)
16.1 Introduction...................................................................................................................................................................371
16.2 Features.........................................................................................................................................................................371
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16.3 Low-voltage detect (LVD) system................................................................................................................................371
16.3.1 LVD reset operation.....................................................................................................................................372
16.3.2 LVD interrupt operation...............................................................................................................................372
16.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 372
16.4 I/O retention..................................................................................................................................................................373
16.5 Memory map and register descriptions.........................................................................................................................373
16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 374
16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 375
16.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................376
Chapter 17
Low-Leakage Wakeup Unit (LLWU)
17.1 Introduction...................................................................................................................................................................379
17.1.1 Features........................................................................................................................................................ 379
17.1.2 Modes of operation...................................................................................................................................... 380
17.1.3 Block diagram..............................................................................................................................................381
17.2 LLWU signal descriptions............................................................................................................................................ 382
17.3 Memory map/register definition................................................................................................................................... 382
17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................383
17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................384
17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................385
17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................386
17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................ 387
17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................389
17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................391
17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................392
17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 394
17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 395
17.4 Functional description...................................................................................................................................................396
17.4.1 LLS mode.....................................................................................................................................................397
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17.4.2 VLLS modes................................................................................................................................................ 397
17.4.3 Initialization................................................................................................................................................. 397
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................399
18.1.1 Features........................................................................................................................................................ 399
18.2 Memory map/register descriptions............................................................................................................................... 399
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................400
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 400
18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)..................................................................... 401
18.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 401
18.2.5 Compute Operation Control Register (MCM_CPO)................................................................................... 404
18.3 Functional description...................................................................................................................................................405
18.3.1 Interrupts...................................................................................................................................................... 405
Chapter 19
Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................407
19.1.1 Features........................................................................................................................................................ 407
19.2 Memory Map / Register Definition...............................................................................................................................408
19.3 Functional Description..................................................................................................................................................408
19.3.1 General operation.........................................................................................................................................408
19.3.2 Arbitration....................................................................................................................................................409
19.4 Initialization/application information........................................................................................................................... 410
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................411
20.1.1 Features........................................................................................................................................................ 411
20.1.2 General operation.........................................................................................................................................411
20.2 Memory map/register definition................................................................................................................................... 412
20.3 Functional description...................................................................................................................................................412
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20.3.1 Access support............................................................................................................................................. 412
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................413
21.1.1 Overview......................................................................................................................................................413
21.1.2 Features........................................................................................................................................................ 414
21.1.3 Modes of operation...................................................................................................................................... 414
21.2 External signal description............................................................................................................................................415
21.3 Memory map/register definition................................................................................................................................... 415
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 416
21.4 Functional description...................................................................................................................................................417
21.4.1 DMA channels with periodic triggering capability......................................................................................417
21.4.2 DMA channels with no triggering capability...............................................................................................419
21.4.3 Always-enabled DMA sources.................................................................................................................... 420
21.5 Initialization/application information........................................................................................................................... 421
21.5.1 Reset.............................................................................................................................................................421
21.5.2 Enabling and configuring sources................................................................................................................421
Chapter 22
Enhanced Direct Memory Access (eDMA)
22.1 Introduction...................................................................................................................................................................425
22.1.1 eDMA system block diagram...................................................................................................................... 425
22.1.2 Block parts................................................................................................................................................... 426
22.1.3 Features........................................................................................................................................................ 427
22.2 Modes of operation....................................................................................................................................................... 428
22.3 Memory map/register definition................................................................................................................................... 429
22.3.1 TCD memory............................................................................................................................................... 429
22.3.2 TCD initialization........................................................................................................................................ 429
22.3.3 TCD structure...............................................................................................................................................429
22.3.4 Reserved memory and bit fields...................................................................................................................430
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22.3.5 Control Register (DMA_CR).......................................................................................................................441
22.3.6 Error Status Register (DMA_ES)................................................................................................................ 444
22.3.7 Enable Request Register (DMA_ERQ)....................................................................................................... 446
22.3.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................448
22.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 450
22.3.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 451
22.3.11 Clear Enable Request Register (DMA_CERQ)...........................................................................................452
22.3.12 Set Enable Request Register (DMA_SERQ)...............................................................................................453
22.3.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................454
22.3.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 455
22.3.15 Clear Error Register (DMA_CERR)............................................................................................................456
22.3.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 457
22.3.17 Interrupt Request Register (DMA_INT)......................................................................................................458
22.3.18 Error Register (DMA_ERR)........................................................................................................................ 460
22.3.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 463
22.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................466
22.3.21 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 468
22.3.22 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................469
22.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................469
22.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................470
22.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 471
22.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................472
22.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 473
22.3.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................474
22.3.29 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................475
22.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................475
22.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................476
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22.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 477
22.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 478
22.3.34 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 479
22.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................481
22.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 482
22.4 Functional description...................................................................................................................................................483
22.4.1 eDMA basic data flow................................................................................................................................. 483
22.4.2 Fault reporting and handling........................................................................................................................486
22.4.3 Channel preemption..................................................................................................................................... 489
22.4.4 Performance................................................................................................................................................. 489
22.5 Initialization/application information........................................................................................................................... 493
22.5.1 eDMA initialization..................................................................................................................................... 493
22.5.2 Programming errors..................................................................................................................................... 495
22.5.3 Arbitration mode considerations..................................................................................................................496
22.5.4 Performing DMA transfers.......................................................................................................................... 496
22.5.5 Monitoring transfer descriptor status........................................................................................................... 500
22.5.6 Channel Linking...........................................................................................................................................502
22.5.7 Dynamic programming................................................................................................................................ 503
22.5.8 Lockstep.......................................................................................................................................................507
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................509
23.1.1 Features........................................................................................................................................................ 509
23.1.2 Modes of Operation..................................................................................................................................... 510
23.1.3 Block Diagram............................................................................................................................................. 511
23.2 EWM Signal Descriptions............................................................................................................................................ 512
23.3 Memory Map/Register Definition.................................................................................................................................512
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23.3.1 Control Register (EWM_CTRL)................................................................................................................. 512
23.3.2 Service Register (EWM_SERV)..................................................................................................................513
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................513
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................514
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................515
23.4 Functional Description..................................................................................................................................................515
23.4.1 The EWM_out Signal.................................................................................................................................. 515
23.4.2 The EWM_in Signal.................................................................................................................................... 516
23.4.3 EWM Counter..............................................................................................................................................517
23.4.4 EWM Compare Registers............................................................................................................................ 517
23.4.5 EWM Refresh Mechanism...........................................................................................................................517
23.4.6 EWM Interrupt.............................................................................................................................................518
23.4.7 Counter clock prescaler................................................................................................................................518
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................519
24.2 Features.........................................................................................................................................................................519
24.3 Functional overview......................................................................................................................................................520
24.3.1 Unlocking and updating the watchdog.........................................................................................................522
24.3.2 Watchdog configuration time (WCT)..........................................................................................................523
24.3.3 Refreshing the watchdog..............................................................................................................................524
24.3.4 Windowed mode of operation......................................................................................................................524
24.3.5 Watchdog disabled mode of operation.........................................................................................................524
24.3.6 Debug modes of operation........................................................................................................................... 524
24.4 Testing the watchdog.................................................................................................................................................... 525
24.4.1 Quick test..................................................................................................................................................... 526
24.4.2 Byte test........................................................................................................................................................526
24.5 Backup reset generator..................................................................................................................................................527
24.6 Generated resets and interrupts.....................................................................................................................................528
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24.7 Memory map and register definition.............................................................................................................................528
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)........................................................... 529
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................ 531
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................531
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................532
24.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................. 532
24.7.6 Watchdog Window Register Low (WDOG_WINL)................................................................................... 533
24.7.7 Watchdog Refresh register (WDOG_REFRESH)....................................................................................... 533
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................533
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................. 534
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................. 534
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................. 535
24.7.12 Watchdog Prescaler register (WDOG_PRESC).......................................................................................... 535
24.8 Watchdog operation with 8-bit access.......................................................................................................................... 535
24.8.1 General guideline......................................................................................................................................... 535
24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................536
24.9 Restrictions on watchdog operation..............................................................................................................................537
Chapter 25
Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................539
25.1.1 Features........................................................................................................................................................ 539
25.1.2 Modes of Operation..................................................................................................................................... 543
25.2 External Signal Description.......................................................................................................................................... 543
25.3 Memory Map/Register Definition.................................................................................................................................543
25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................544
25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................545
25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................546
25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................547
25.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................548
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25.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................549
25.3.7 MCG Status Register (MCG_S).................................................................................................................. 551
25.3.8 MCG Status and Control Register (MCG_SC)............................................................................................552
25.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 554
25.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................554
25.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................554
25.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................555
25.3.13 MCG Control 12 Register (MCG_C12).......................................................................................................556
25.3.13 MCG Status 2 Register (MCG_S2)............................................................................................................. 556
25.3.13 MCG Test 3 Register (MCG_T3)................................................................................................................ 557
25.4 Functional description...................................................................................................................................................557
25.4.1 MCG mode state diagram............................................................................................................................ 557
25.4.2 Low-power bit usage....................................................................................................................................561
25.4.3 MCG Internal Reference Clocks..................................................................................................................561
25.4.4 External Reference Clock............................................................................................................................ 562
25.4.5 MCG Fixed Frequency Clock .....................................................................................................................563
25.4.6 MCG PLL clock ..........................................................................................................................................563
25.4.7 MCG Auto TRIM (ATM)............................................................................................................................563
25.5 Initialization / Application information........................................................................................................................ 564
25.5.1 MCG module initialization sequence...........................................................................................................564
25.5.2 Using a 32.768 kHz reference......................................................................................................................567
25.5.3 MCG mode switching.................................................................................................................................. 567
Chapter 26
Oscillator (OSC)
26.1 Introduction...................................................................................................................................................................577
26.2 Features and Modes...................................................................................................................................................... 577
26.3 Block Diagram..............................................................................................................................................................578
26.4 OSC Signal Descriptions.............................................................................................................................................. 578
26.5 External Crystal / Resonator Connections.................................................................................................................... 579
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