NXP Semiconductors PN7150 Guide

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PN7150 Hardware Design Guide
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Document information
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Content
Keywords
PN7150, Hardware Design, Power modes, Chip interfaces
Abstract
This document is intended to provide an overview on how to integrate the
NFC Controller PN7150 from hardware perspective.
It presents the different hardware design options offered by the IC and
provides guidelines on how to select the most appropriate ones for a
given implementation.
In particular, this document highlights the different chip power states and
how to operate them in order to minimize the average NFC-related power
consumption.

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Contact information
For additional information, please visit:
http://www.nxp.com
Revision history
Rev
Date
Description
1.2
20180115
Adding information related to WLCSP42 package
Editorial changes
1.1
20160523
Security status changed into “COMPANY PUBLIC”
1.0
20151204
First official version of the document

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1. Introduction
The PN7150 is a full feature NFC Controller designed for integration in devices compliant
with NFC Forum standards.
It is designed based on learning from previous NXP NFC device generation to ease the
integration of the NFC technology in electronic devices by providing:
- A low PCB footprint and a reduced external Bill of Material by enabling as unique
feature the capability to achieve RF standards with small form factor antenna
- An optimized architecture for low power consumption in different modes (standby,
low power polling loop)
- An highly efficient integrated power management unit allowing direct supply from
a battery while a constant output power (operating distance in Poll mode) for
extended battery supply range (2.75 to 5.5V) can be achieved.
It embeds a new generation RF contactless front-end supporting various transmission
modes according to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC 15693, MIFARE
and FeliCa specifications. This new contactless front-end design brings a major
performance step-up with a higher sensitivity.
Detailed chip features set can be found in the PN7150 Product Datasheet [1].
This application note is intended to give an overview of the way the PN7150 must be
integrated into a hardware platform. It presents in particular the different hardware design
options offered by the PN7150 and it provides guidelines on how to select the most
appropriate ones for a given implementation.
An overview of the different chip interfaces is first shown. Then detailed information
related to each interface is depicted and the related configurations are presented.

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2. Interfaces
The purpose of this chapter is to give an overview of the PN7150 interfaces and to show
how the chip is interconnected to the external world.
PN7150 external connections are shown in Fig 1.
Then, PN7150 interfaces are listed in Table 1 and the different configuration options are
mentioned.
Antenna
matching / tuning
circuit
Antenna interface
V BAT
V DD(PAD)
INPUT CLK Optional
CLK request
Power interface
Clock interface
Host controller
Host interface
V DD
V DD(TX)
Antenna
VEN Optional
IRQ
NFCC
Optional
PWR request
Fig 1. Interfaces summary
The PN7150 provides the following interfaces:
Host interface
Clock interface
Power interface
Antenna interface

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Table 1. Interface summary
Interface
Short description
Options
Host interface
Link with host controller
•I²C address configuration
•IRQ or polling
•Reset control
Clock interface
Input clock required when
generating RF field •Input clock characteristics
•
CLK request mechanism
Power interface
Interface to power management
unit (direct battery supply
supported)
•Power management concept
•Decoupling capacitors
Antenna interface
Link to an NFC antenna in order to
enable communication with a
remote contactless device
•Antenna selection
•Antenna matching

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3. Typical application schematics
The purpose of this chapter is to propose an application schematic for PN7150.
The below depicted configuration is based on the following implementation choices:
a. The use of a crystal as input clock source (see 5.1)
b. The use of a standard antenna (see 7.1)
c. The use of VBAT to generate TVDD (see 6.4.1)
Fig 2. Typical Application Schematic in HVQFN package
Fig 3. Typical Application Schematic in WLCSP package

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4. Host interface
4.1 Host interface pinning
Table 2. Host interface pinning
HVQFN pin
WLCSP pin
Symbol
Description
#1
F1
I2CADR0
I2C-bus ADdRess bit 0 input
#3
E2
I2CADR1
I2C-bus ADdRess bit 1 input
#5
D2
I2CSDA
I2C-bus Serial DAta
#7
D1
I2CSCL
I2C-bus Serial Clock Line
#8
C1
IRQ
Interrupt ReQuest output
#10
C3
VEN
V ENable input. Set the device in Hard Power Down
4.2 Host interface pin characteristics
Detailed characteristics of the host interface pins can be found in the PN7150 Product
datasheet [1].
4.3 Digital interface levels
The host controller interface power supply must be connected to the PN7150 on the
VDD(PAD) pin. Both 1.8V and 3V supply levels are supported.
Thus, multiple digital levels between the host controller and the PN7150 can be
supported without the need for level shifters.
For details on the VDD(PAD) range, please refer to the PN7150 Product Datasheet [1].
4.4 I²C bus specificities
Slave address:
In the case where I²C is the selected host interface, the chip will answer to a given I²C
slave address.
This is determined by the combination of a base address and the logical state of
I2CADR0 and I2CADR1 pins: b' 0 1 0 1 0 I2CADR1 I2CADR0’ where I2CADR0 and
I2CADR1 are the least significant bits. For instance, if both I2CADR0 and I2CADR1 are
tied to ground, the 7-bits slave address of the PN7150 is “0x28” (gives 0x50 as 8-bits
write address).
Table 3. I²C slave 8-bits address
I2CADR0 Level
I2CADR1 Level
I2C write address
(R/W bit = 0)
I2C read address
(R/W bit = 1)
0 (GND)
0 (GND)
0x50
0x51
1 (VDD(PAD))
0 (GND)
0x52
0x53
0 (GND)
1 (VDD(PAD))
0x54
0x55
1 (VDD(PAD))
1 (VDD(PAD))
0x56
0x57

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Pull-up selection:
Pull-up resistors to VDD(PAD) are required on the I²C lines SDA and SCL. The resistors
value must be selected to meet the I²C timing requirements based on the line
capacitance, the VDD(PAD) level and the targeted maximum I²C clock speed. More
details can be found in the I²C bus specification [3] document.
4.5 Frames reading synchronization
PN7150 answers / notifications toward the host controller are asynchronous and they can
be triggered by an external event (e.g. detection of a card in the RF field).
Therefore, a mechanism must be put in place so that asynchronous frames from the
PN7150 are well captured by the host controller. For this, 3 implementations can be
foreseen on the host controller side:
1- IRQ pin external interrupt
2- IRQ pin polling
3- Read polling
For 1-, connect pin IRQ of the PN7150 to an external interrupt line on the host controller
side. In this case, when the PN7150 has some data available, the IRQ line will be
asserted and if configured accordingly, a software interrupt is generated on the host
controller side. An I2C read is then managed by the corresponding interrupt handler.
For 2-, the principle is to regularly poll the status of the IRQ pin and when it toggles, to
perform a read on the I2C interface.
For 3-, the principle is to regularly perform some read on the I2C interface and to discard
frames starting with the default value as in this case it would mean that no data is
available from the PN7150. The I²C address will not be acknowledged in case the
PN7150 doesn’t have any meaningful data to send to the host.
Implementation -1 is recommended.
IRQ Signal Specification:
The signal can be configured active high or active low via the NCI Configuration
API. This configuration is stored in non-volatile memory. Details can be found in the
PN7150 User Manual [2].
The signal will be active any time data is available in the PN7150 send buffer
The pad state is maintained during the standby mode
The pad is configured in pull down in hard power down mode
4.6 Reset control (VEN)
The PN7150 HW is activated using the input pin VEN.
When VEN is greater than 1.1V the PN7150 core is supplied from VBAT.

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For VEN lower than 0.4V the PN7150 is in hard power down state and the chip’s internal
core is no more supplied.
The chip is reset when VEN is switched back to a voltage level higher than 1.1V.
It is strongly recommended to foresee a control of VEN pin from the host controller side
so that it can reset PN7150 whenever needed.
The VEN pad state is considered as valid information only when the VDD(PAD) pad is
supplied.
Indeed, VEN signal is supposed to be driven by the host controller with which VDD(PAD)
supply is shared. When the supply is not there, this means that the host controller is not
able to drive a meaningful state on the PN7150 VEN pin.
An internal pull-down resistor can be programmed on the PN7150 internal VEN signal in
order to define a clear pin state when it is not externally driven by the host (details can be
found in PN7150 User Manual [2]). It means that when the device is powered-up with
VBAT and VDD(PAD) supplied to the PN7150, the NFC chip will stand in hard power
down until the host controller explicitly drives the VEN pin to the digital high state (during
its boot sequence).
The full PN7150 power states, considering VBAT, VDD(PAD) and VEN pin level, is given
in PN7150 Product datasheet [1].

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5. Clock interface
The core microcontroller of the PN7150 chip can run without any external clock (based
on an internal oscillator). However, the 13.56MHz RF field carrier accuracy requirements
are not compatible with the use of an internal oscillator. As a consequence, the PN7150
needs either to have an external clock supplied to its XTAL1 pin or to be connected to a
crystal oscillator before starting to emit an RF field.
The PN7150 clock interface must be configured properly to reflect whether it is
connected to a crystal oscillator or to an external clock (in this case, the frequency must
also be configured). This is done through the NCI host interface. Details can be found in
PN7150 User Manual [2].
5.1 Use of crystal oscillator
A 27.12MHz crystal can be used as input clock for PN7150. For instance, when there is
no clock on the system complying with the PN7150 input clock specification. When using
a crystal, frequency accuracy and drive level must be carefully selected according to the
specification provided in the PN7150 Product Datasheet [1].
Fig 4. Crystal based clock configuration
Crystal interface has been verified with several references as given below. Other crystal
units might be suitable for the specified usage, but only the ones below have been
properly checked by NXP.
- NDK:
oNX2016AA 27.12MHz EXS00A-03778 (discontinued)
oNX2016SA 27.12MHz EXS00A-CS06346
oNX2016HA 27.12MHz EXS00A-CH00075
- MURATA:
oXRCGB27M120F3M10R0

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5.2 Use of system clock
5.2.1 Input clock characteristics
When an external system clock is used, the input clock frequency must be one of the
following values: 13MHz, 19.2MHz, 24MHz, 26MHz, 38.4MHz or 52MHz
Please note that the voltage level of the system clock signal provided to PN7150 must be
1.8V.
The system clock used with the PN7150 chip must fulfill the phase noise requirement
described in the datasheet.
The PN7150 input impedance on the XTAL1 pin depends on the input clock frequency:
At 13MHz, it is between 25Kohms and 86Kohms in active mode and between 49Kohms
and 53Kohms in standby or Hard Power Down mode.
At 52MHz, it is between 5Kohms and 7.5Kohms in active mode and between 12Kohms
and 14Kohms in standby or Hard Power Down mode.
Based on this input clock signal, the PN7150 internal PLL generates the required
27.12MHz internal clock for field generation.
Detailed system clock characteristics can be found in the PN7150 Product Datasheet [1].
5.2.2 Clock request mechanism
In order to optimize the device power consumption, the input clock could be provided by
the system only when it is actually needed by the chip (i.e. when the NFCC needs to
generate an RF field). For this, a clock request mechanism has been put in place.
When the PN7150 needs an input clock, it toggles the CLK_REQ pin to the digital high
level and keeps it high as long as the input clock is required. It requires a specific
connection of the CLK_REQ pin which would switch-on the system clock signal
whenever the pin is at the digital high level and switch it off when the pin is set back to
the digital low level.
This feature is enabled according to PN7150 EEPROM configuration (see details in the
PN7150 User Manual [2]).
Fig 5. Clock request through CLK_REQ pin

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Warning: XTAL1 pin is referenced to VDD(PAD) supply. Therefore VDD(PAD) must
always be supplied to the PN7150 when a valid input clock signal is required (i.e. to
generate an RF field)
The dedicated clock request pin (CLK_REQ) can be optionally connected to a clock
buffer. CLK_REQ pin is driven high when the NFCC needs an input clock. Otherwise it is
driven low.
Fig 6. External system clock configuration

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6. Power interface
6.1 Power Management Unit
The PN7150 supports to be directly connected to a battery power supply.
It can operate with a wide voltage input range from 5.5V down to 2.75V.
Detailed current consumption versus the different power mode and min/typical/max
voltage information can be found in the PN7150 Product Datasheet [1].
6.2 External capacitors requirement
The recommended external capacitors (value and voltage it must at least withstand) are
listed below:
Table 4. Decoupling capacitors need
Values
Comments
C
VDD
1µF/2V
C
VDD(PAD)
1µF/2V or 3.3V
Depending on host power supply decoupling needs
C
TVDD
1µF/3.6V
C
VBAT
4.7µF/5.5V
C
VBAT2
100nF/5V
CVMID
100nF/1.8V
A tolerance of 10% or better is recommended for those capacitors. Component de-rating
over voltage and temperature must be carefully considered during the decoupling
capacitors selection process.
6.3 Power application schematic
V BAT
Battery
NFCC
TXLDO
TVDD
4.7µF
1µF
C VBAT
C TVDD
C
VBAT2
100nF
V BAT1 V
BAT2
V DD(TX)
Fig 7. Power application schematic

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6.4 TVDD supply options
The strength of the field emitted by the PN7150 is linked to several parameters such as
the antenna geometrical characteristics, the antenna matching circuit and the voltage
level on TX output buffer.
The voltage level on TX output buffer is coming from TVDD. Typical TVDD influence on
RF reading distance is depicted on the below picture:
Fig 8. Typical reading distance vs TVDD using OM5578 board
TVDD can be regulated by the TXLDO which will be powered internally by the PN7150.
The voltages choice will depend on the configuration used.
Please note that if the product has already been certified, changing one RF
parameter like TVDD setting must lead to a full re-certification.
The programming of the TVDD configuration is described in PN7150 User Manual [2].
6.4.1 Config 1: VBAT used to generate TVDD
The Low drop Out Regulator has been designed to generate a 3.0 V, 3.3 V or 3.6 V
supply voltage to a transmitter with a current load up to 180 mA.
The input supply voltage of this regulator is a battery voltage connected to VBAT1 pin.

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Fig 9. Configuration 1: VBAT used to generate TVDD
TVDD value shall be chosen according the minimum targeted VBAT value for which
reader mode shall work.
Fig 10. Configuration 1: TVDD offset behavior
For example, if chosen TVDD is 3.6V and current to be delivered by the TxLDO is Itx, it
means:
  ≥(3.6+ 1Ω ∗ )ℎ  = 3.6
 2.3 ≤  ≤3.6ℎ  = −1Ω ∗ 
As the maximum current allowed is 180mA, a margin of 180mV between the VBAT and
the chosen TVDD value is needed to work on the regulated area of the LDO.
In Standby state, whenever TVDD is configured for 3V, 3.3V or 3.6V, TVDD is
regulated @2.5V
Table 5. Configuration 1 summary
Reader mode
Card mode
Standby mode
TVDD available voltage
3/3.3/3.6
3/3.3/3.6
2.5

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6.4.2 Config 2: external 5V used to generate TVDD
In this case the TXLDO can provide a TVDD of 3V/3.3V/3.6V/4.5V or 4.75V.
Fig 11. Configuration 2: external 5V used to generate TVDD
Fig 12. Configuration 2: TVDD offset behavior
Depending on the wanted behaviour of the external 5V in card mode, 2 different
programming are available.
Table 6. Configuration 2 summary
Reader mode
Card mode
Standby mode
TVDD available voltage
3/3.3/3.6/4.5/4.75
3/3.3/3.6/4.5/4.75
2.5
6.4.3 TVDD configuration summary
Table 7. Available TVDD value for each configuration
Reader mode
Card mode
Standby mode
Config 1
3/3.3/3.6/4.5/4.75
3/3.3/3.6
2.5
Config 2
3/3.3/3.6/4.5/4.75
3/3.3/3.6/4.5/4.75
2.5

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Table 8. Pros and cons for each TVDD configuration
Pros
Cons
Configuration 1
- No external 5V supply
- No performances improvement thanks to higher
VDD(TX) voltage
Configuration 2
- Maximize the performances in reader mode and
card mode
- Use the internal TXLDO to filter the 5V power
supply
- Higher power consumption compare to
configuration 1
PN7150 can operate at fixed RF field strength in Poll mode with a continuous battery
voltage down to:
a. 3.1V when TVDD is set to 2.7V
b. 3.5V when TVDD is set to 3.1V
The figure below shows 2 typical battery discharge cycles.
Fig 13. Battery discharge curve
2
2,5
3
3,5
4
4,5
0%10%20%30%40%50%60%70%80%90%100%
Battery Voltage [V]
Battery Charge [%]
Battery 1 Voltage [V]
Battery 2 Voltage [V]
RF performance drop if
TVDD <2,7V (input
<2,9V)
RF performance drop if
TVDD <3,1V (input
<3,3V)
Battery 1 @12%
charge
Battery 2 @60%
charge
Battery 1 @5% charge

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7. Antenna interface
7.1 Typical matching circuit
The PN7150 is intended to be connected to an antenna through a matching circuit.
The typical topology for this circuit is depicted below:
Fig 14. Typical antenna matching circuit
The components values are antenna dependent.
L0/ C0are a 2nd order low pass filter used to reduce the spectrum power amplitude in the
high frequency range but without altering the meaningful communication signal.
C1/ C2are used to tune the Poll mode and Listen mode frequency at 13.56MHz and to
adapt the equivalent impedance presented on TX1/TX2 at this frequency (70 ohms
recommended).
Rqis optionally used to reduce the qualify factor of the antenna when it is above 35 (if it is
already below, which is rather common in embedded equipment environment with ferrite
shielding, Rqmust not be placed)
How to select or design a proper antenna for the PN7150 and how to calculate the value
of the matching components is explained in a dedicated application note. Please refer to
the PN7150 Antenna Design and Matching Guide [4].
7.2 Matching circuit BoM optimization
Based on careful technical consideration, the number of matching circuit components
presented on the above schematics can be lowered.

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Fig 15. Optimized matching circuit
7.2.1 Damping resistors
Rqdamping resistors are used to lower the antenna quality factor when it is above 35.
Indeed, a too high quality factor will negatively impact the generated signal shaping.
However, in an embedded environment, the presence of metal (battery, PCB tracks,
electronic components...) tends to significantly reduce the antenna quality factor.
Therefore, although they can be needed on an open-air board environment, it is very
unlikely that these 2 resistors are required for embedded equipment integration.
Proof point:
Once the customer has measured its NFC antenna within its final environment he should
calculate the resulting quality factor as explained in the PN7150 Antenna Design Guide
[4]. If the quality factor is below or equal to 35, Rqresistors can be safely removed.
See circles 1 in above Fig 15.
7.2.2 C2parallel capacitor
Two serial capacitors are used in parallel with the antenna to tune it to 13.56MHz.
The reason to have 2 capacitors in parallel in that the peak to peak voltage at antenna
ends can reach more than 50V depending on the antenna geometrical characteristics
(size, number of turns…)
However, if for a given antenna, the maximum peak to peak voltage measured at
antenna ends is lower, then a single parallel capacitor on Cpcan eventually be used.
Its value needs then to be divided by 2 compared to the ones used in case of 2 serial
capacitors solution.
Proof point:
As the voltage generated at antenna ends for a given external field power will be strongly
linked to the antenna environment, this measurement must be performed within the final
product.

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It must be placed on an ISO/IEC10373-6 PCD assembly test bench and the maximum
external field strength that an ISO/IEC14443 compliant device must withstand (12A/m)
must be generated.
Then, the peak to peak voltage at antenna end must be measured with an oscilloscope
using a low parasitic capacitor probe (2pF max).
Depending on the value measured, the customer can decide whether a single 50V
parallel capacitor is suitable
See circle 2 in above Fig 15.
7.2.3 Rx path
In case a small antenna is connected to the PN7150, the peak to peak voltage generated
at antenna ends will be limited.
Then this offers the possibility to simplify the RF path circuitry by removing the
decoupling Crx caps and connecting directly the Rrx to the antenna ends (see drawing
below)
Proof point:
The measurements needed to decide whether or not, the Crx capacitors can be safely
removed for a given configuration are still under definition.
See circles 3 in above Fig 15.