NXP Semiconductors PN7150 Guide

AN11756
PN7150 Hardware Design Guide
Rev. 1.2 — 15 January 2018
347612
Application note
COMPANY PUBLIC
Document information
Info
Content
Keywords
PN7150, Hardware Design, Power modes, Chip interfaces
Abstract
This document is intended to provide an overview on how to integrate the
NFC Controller PN7150 from hardware perspective.
It presents the different hardware design options offered by the IC and
provides guidelines on how to select the most appropriate ones for a
given implementation.
In particular, this document highlights the different chip power states and
how to operate them in order to minimize the average NFC-related power
consumption.

NXP Semiconductors
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PN7150 Hardware Design Guide
AN11756
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© NXP B.V. 2018. All rights reserved.
Application note
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Contact information
For additional information, please visit:
http://www.nxp.com
Revision history
Rev
Date
Description
1.2
20180115
Adding information related to WLCSP42 package
Editorial changes
1.1
20160523
Security status changed into “COMPANY PUBLIC”
1.0
20151204
First official version of the document

NXP Semiconductors
AN11756
PN7150 Hardware Design Guide
AN11756
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© NXP B.V. 2018. All rights reserved.
Application note
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1. Introduction
The PN7150 is a full feature NFC Controller designed for integration in devices compliant
with NFC Forum standards.
It is designed based on learning from previous NXP NFC device generation to ease the
integration of the NFC technology in electronic devices by providing:
- A low PCB footprint and a reduced external Bill of Material by enabling as unique
feature the capability to achieve RF standards with small form factor antenna
- An optimized architecture for low power consumption in different modes (standby,
low power polling loop)
- An highly efficient integrated power management unit allowing direct supply from
a battery while a constant output power (operating distance in Poll mode) for
extended battery supply range (2.75 to 5.5V) can be achieved.
It embeds a new generation RF contactless front-end supporting various transmission
modes according to NFCIP-1 and NFCIP-2, ISO/IEC 14443, ISO/IEC 15693, MIFARE
and FeliCa specifications. This new contactless front-end design brings a major
performance step-up with a higher sensitivity.
Detailed chip features set can be found in the PN7150 Product Datasheet [1].
This application note is intended to give an overview of the way the PN7150 must be
integrated into a hardware platform. It presents in particular the different hardware design
options offered by the PN7150 and it provides guidelines on how to select the most
appropriate ones for a given implementation.
An overview of the different chip interfaces is first shown. Then detailed information
related to each interface is depicted and the related configurations are presented.

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PN7150 Hardware Design Guide
AN11756
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2. Interfaces
The purpose of this chapter is to give an overview of the PN7150 interfaces and to show
how the chip is interconnected to the external world.
PN7150 external connections are shown in Fig 1.
Then, PN7150 interfaces are listed in Table 1 and the different configuration options are
mentioned.
Antenna
matching / tuning
circuit
Antenna interface
V BAT
V DD(PAD)
INPUT CLK Optional
CLK request
Power interface
Clock interface
Host controller
Host interface
V DD
V DD(TX)
Antenna
VEN Optional
IRQ
NFCC
Optional
PWR request
Fig 1. Interfaces summary
The PN7150 provides the following interfaces:
Host interface
Clock interface
Power interface
Antenna interface

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PN7150 Hardware Design Guide
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Table 1. Interface summary
Interface
Short description
Options
Host interface
Link with host controller
•I²C address configuration
•IRQ or polling
•Reset control
Clock interface
Input clock required when
generating RF field •Input clock characteristics
•
CLK request mechanism
Power interface
Interface to power management
unit (direct battery supply
supported)
•Power management concept
•Decoupling capacitors
Antenna interface
Link to an NFC antenna in order to
enable communication with a
remote contactless device
•Antenna selection
•Antenna matching

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PN7150 Hardware Design Guide
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3. Typical application schematics
The purpose of this chapter is to propose an application schematic for PN7150.
The below depicted configuration is based on the following implementation choices:
a. The use of a crystal as input clock source (see 5.1)
b. The use of a standard antenna (see 7.1)
c. The use of VBAT to generate TVDD (see 6.4.1)
Fig 2. Typical Application Schematic in HVQFN package
Fig 3. Typical Application Schematic in WLCSP package

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PN7150 Hardware Design Guide
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4. Host interface
4.1 Host interface pinning
Table 2. Host interface pinning
HVQFN pin
WLCSP pin
Symbol
Description
#1
F1
I2CADR0
I2C-bus ADdRess bit 0 input
#3
E2
I2CADR1
I2C-bus ADdRess bit 1 input
#5
D2
I2CSDA
I2C-bus Serial DAta
#7
D1
I2CSCL
I2C-bus Serial Clock Line
#8
C1
IRQ
Interrupt ReQuest output
#10
C3
VEN
V ENable input. Set the device in Hard Power Down
4.2 Host interface pin characteristics
Detailed characteristics of the host interface pins can be found in the PN7150 Product
datasheet [1].
4.3 Digital interface levels
The host controller interface power supply must be connected to the PN7150 on the
VDD(PAD) pin. Both 1.8V and 3V supply levels are supported.
Thus, multiple digital levels between the host controller and the PN7150 can be
supported without the need for level shifters.
For details on the VDD(PAD) range, please refer to the PN7150 Product Datasheet [1].
4.4 I²C bus specificities
Slave address:
In the case where I²C is the selected host interface, the chip will answer to a given I²C
slave address.
This is determined by the combination of a base address and the logical state of
I2CADR0 and I2CADR1 pins: b' 0 1 0 1 0 I2CADR1 I2CADR0’ where I2CADR0 and
I2CADR1 are the least significant bits. For instance, if both I2CADR0 and I2CADR1 are
tied to ground, the 7-bits slave address of the PN7150 is “0x28” (gives 0x50 as 8-bits
write address).
Table 3. I²C slave 8-bits address
I2CADR0 Level
I2CADR1 Level
I2C write address
(R/W bit = 0)
I2C read address
(R/W bit = 1)
0 (GND)
0 (GND)
0x50
0x51
1 (VDD(PAD))
0 (GND)
0x52
0x53
0 (GND)
1 (VDD(PAD))
0x54
0x55
1 (VDD(PAD))
1 (VDD(PAD))
0x56
0x57

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Pull-up selection:
Pull-up resistors to VDD(PAD) are required on the I²C lines SDA and SCL. The resistors
value must be selected to meet the I²C timing requirements based on the line
capacitance, the VDD(PAD) level and the targeted maximum I²C clock speed. More
details can be found in the I²C bus specification [3] document.
4.5 Frames reading synchronization
PN7150 answers / notifications toward the host controller are asynchronous and they can
be triggered by an external event (e.g. detection of a card in the RF field).
Therefore, a mechanism must be put in place so that asynchronous frames from the
PN7150 are well captured by the host controller. For this, 3 implementations can be
foreseen on the host controller side:
1- IRQ pin external interrupt
2- IRQ pin polling
3- Read polling
For 1-, connect pin IRQ of the PN7150 to an external interrupt line on the host controller
side. In this case, when the PN7150 has some data available, the IRQ line will be
asserted and if configured accordingly, a software interrupt is generated on the host
controller side. An I2C read is then managed by the corresponding interrupt handler.
For 2-, the principle is to regularly poll the status of the IRQ pin and when it toggles, to
perform a read on the I2C interface.
For 3-, the principle is to regularly perform some read on the I2C interface and to discard
frames starting with the default value as in this case it would mean that no data is
available from the PN7150. The I²C address will not be acknowledged in case the
PN7150 doesn’t have any meaningful data to send to the host.
Implementation -1 is recommended.
IRQ Signal Specification:
The signal can be configured active high or active low via the NCI Configuration
API. This configuration is stored in non-volatile memory. Details can be found in the
PN7150 User Manual [2].
The signal will be active any time data is available in the PN7150 send buffer
The pad state is maintained during the standby mode
The pad is configured in pull down in hard power down mode
4.6 Reset control (VEN)
The PN7150 HW is activated using the input pin VEN.
When VEN is greater than 1.1V the PN7150 core is supplied from VBAT.

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For VEN lower than 0.4V the PN7150 is in hard power down state and the chip’s internal
core is no more supplied.
The chip is reset when VEN is switched back to a voltage level higher than 1.1V.
It is strongly recommended to foresee a control of VEN pin from the host controller side
so that it can reset PN7150 whenever needed.
The VEN pad state is considered as valid information only when the VDD(PAD) pad is
supplied.
Indeed, VEN signal is supposed to be driven by the host controller with which VDD(PAD)
supply is shared. When the supply is not there, this means that the host controller is not
able to drive a meaningful state on the PN7150 VEN pin.
An internal pull-down resistor can be programmed on the PN7150 internal VEN signal in
order to define a clear pin state when it is not externally driven by the host (details can be
found in PN7150 User Manual [2]). It means that when the device is powered-up with
VBAT and VDD(PAD) supplied to the PN7150, the NFC chip will stand in hard power
down until the host controller explicitly drives the VEN pin to the digital high state (during
its boot sequence).
The full PN7150 power states, considering VBAT, VDD(PAD) and VEN pin level, is given
in PN7150 Product datasheet [1].

NXP Semiconductors
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PN7150 Hardware Design Guide
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5. Clock interface
The core microcontroller of the PN7150 chip can run without any external clock (based
on an internal oscillator). However, the 13.56MHz RF field carrier accuracy requirements
are not compatible with the use of an internal oscillator. As a consequence, the PN7150
needs either to have an external clock supplied to its XTAL1 pin or to be connected to a
crystal oscillator before starting to emit an RF field.
The PN7150 clock interface must be configured properly to reflect whether it is
connected to a crystal oscillator or to an external clock (in this case, the frequency must
also be configured). This is done through the NCI host interface. Details can be found in
PN7150 User Manual [2].
5.1 Use of crystal oscillator
A 27.12MHz crystal can be used as input clock for PN7150. For instance, when there is
no clock on the system complying with the PN7150 input clock specification. When using
a crystal, frequency accuracy and drive level must be carefully selected according to the
specification provided in the PN7150 Product Datasheet [1].
Fig 4. Crystal based clock configuration
Crystal interface has been verified with several references as given below. Other crystal
units might be suitable for the specified usage, but only the ones below have been
properly checked by NXP.
- NDK:
oNX2016AA 27.12MHz EXS00A-03778 (discontinued)
oNX2016SA 27.12MHz EXS00A-CS06346
oNX2016HA 27.12MHz EXS00A-CH00075
- MURATA:
oXRCGB27M120F3M10R0