Panasonic Z-421V Quick start guide

Technical Guide
Colour Television
Z-421V Chassis
Circuit Description
Panasonic European Television Division
Matsushita Electric (U.K.) Ltd
Order No. TG-990904

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Contents
1 CIRCUIT DESCRIPTION...........................................................................................................................3
1.1 SMALL SIGNAL PART .................................................................................................................................3
1.1.1 Tuner and IF output Tuner:.............................................................................................................3
1.1.2 Vision IF ..........................................................................................................................................3
1.1.3 Sound...............................................................................................................................................8
1.1.4 Horizontal and vertical synchronization .......................................................................................10
1.1.5 Luminance and chrominance signal processing............................................................................13
1.1.6 Color Decoder...............................................................................................................................15
1.1.7 AFC - Tuning - ATS .......................................................................................................................18
1.2 DIGITAL CONTROL SIGNALS....................................................................................................................20
1.2.1 1-3-1 local keyboard......................................................................................................................20
1.2.2 1-3-2 IR remote control code.........................................................................................................20
1.2.3 I2C bus...........................................................................................................................................22
1.3 HORIZONTAL DEFLECTION - FBT ...........................................................................................................24
1.3.1 General description:......................................................................................................................24
1.3.2 Horizontal deflection.....................................................................................................................24
1.4 VERTICAL DEFLECTION...........................................................................................................................29
1.4.1 Z-421 circuit ..................................................................................................................................29
1.4.2 Drive circuit part...........................................................................................................................30
1.5 VIDEO AMPLIFIER AND ABS...................................................................................................................32
1.5.1 Video output amplification.............................................................................................................32
1.5.2 ABS operation................................................................................................................................34
1.5.3 Beam current limiter......................................................................................................................35
1.5.4 Euro-scart......................................................................................................................................36
1.6 POWER SUPPLY STR-S5707....................................................................................................................37
1.6.1 Vin terminal, start-up circuit..........................................................................................................37
1.6.2 Oscillator, F/B terminal voltage (pin 7).........................................................................................37
1.6.3 Function of INH terminal (pin 6), control of off-time....................................................................37
1.6.4 Drive circuit...................................................................................................................................37
1.6.5 OCP function.................................................................................................................................37
1.6.6 Latch Circuit..................................................................................................................................38
1.6.7 Thermal shutdown circuit..............................................................................................................38
1.6.8 Over-voltage protection circuit......................................................................................................38
1.6.9 Stand-by Mode TOP210.................................................................................................................38
1.6.10 CONTROL PIN (pin4)...................................................................................................................38
2 VCR PART...................................................................................................................................................39
2.1 KEY FEATURES OF VIDEO IC AND ITS RELATIVES....................................................................39
2.2 RECORD AND PLAYBACK PROCESSING CIRCUIT .....................................................................40
2.2.1 RECORD PROCESSING...............................................................................................................40
2.2.2 PLAYBACK PROCESSING...........................................................................................................43
2.2.3 AUDIO SIGNAL PROCESSING (LA71511M) ..............................................................................46

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1 Circuit Description
1.1 Small signal part
1.1.1 Tuner and IF output Tuner:
Type TV standard PIF Channel coverage
B/G 38.9 MHz
L/L’ 38.9 MHz
DT5-BF15P
(DAEWOO) I 38.9 MHz
VHF_L : CH E2 -- CH S7
VHF_H : CH S8 -- CH S36
UHF : CH S37 -- CH E69
The RF tuner selects the picture and sound signals of the desired station by converting the RF signal
into the Intermediate Frequency (IF) of the receiver.
The common UHF/VHF input is realized by an aerial connector (75Ω) (DIN IEC jack). The IF output is
balanced (75Ω). The tuning mode is voltage synthesis.
IF output and SAW filter
The high gain tuner, balanced output can be connected directly to tile SAW filter input.
The surface Acoustic Wave filters are based on the interference of mechanical surface waves.
TV standard B/G L/L’ I
Picture carrier 38.9 MHz 38.9 MHz 38.9 MHz
Color carrier 34.47 MHz 34.47 MHz 34.47 MHz
Sound carrier 33.4 MHz 33.4 MHz 33.4 MHz
1.1.2 Vision IF
See also the related block diagram as well as the diagrams at the end of the report.
The main functions are:
* IF amplifier
* PLL-demodulator and alignment free VCO
* Video buffer
* AFC
* AGC
* Tuner AGC
* Video identification
These functions will be described next in this section.
The TDA884X includes an integrated vision-IF. This gives advantages compared to a stand alone IC
for vision-IF only. Some advantages are:
I
2C bus commands are available for many control functions and alignment. This saves a pins and
external components.
Optimal performance is achieved by means of timing/gating signals derived from the
synchronization part.
Build-in accuracy of circuits is derived by use of the available chroma crystal oscillator.

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* IF-amplifier
The IF-amplifier has symmetrical inputs and consists of three AC coupled differential gain stages with
AGC function. Due to the AC coupling, biasing is simple so that cascades can be used and no DC
feedback is necessary. The gain control range of the IF amplifier is 64dB minimal. The input sensitivity
for AGC onset is 70 mV typical. The maximal IF-gain can be reduced with 20dB by means of I²C bus
IFS.
* PLL-demodulator and alignment free VCO
The IF-signal is demodulated with the help of a PLL detector. The PLL detector is used to regenerate a
reference signal that is in phase to the IF-carrier signal. Demodulation is achieved by multiplying this
reference signal with the incoming IF-signal. This reference signal is a clean signal that does not
contain video information; this bandwidth (approx. 60kHz) is determined by the PLL loopfilter pin 5.
The demodulator can handle both negative and negative modulation, selection is done with I²C bus bit
MOD.
A low pass filter after the demodulator output reduces the higher frequency demodulation products.
The voltage controlled oscillator, VCO, is alignment free and makes the concept even more attractive.
No external coil is required any more. It saves both the coil costs and an alignment. As regards EMC
the system becomes more robust. The required IF-system frequency 38.9, 45.75MHz, including
SECAM-L’, is selected by I²C. The correct VCO frequency is determined by the calibrator system
which uses one of the actual chroma crystal as reference. Calibration occurs automatically after
power-on and every time after loss of sync lock (I2C bit SL)
The PLL catching range is plus/min 1MHz around the selected IF-frequency. Within this range the PLL
ensures automatic tracking to the incoming frequency. The PLL is basically an "FPLL", Frequency
Phase Lock Loop system. This extra frequency detector gives an output signal to the PLL loopfilter as
long as a difference in frequency is detected. This ensures fast catching.
The PLL loopfilter time constant can be made fast via Fast Filter IF-PLL, FFI. This function has been
made available to handle RF-transmitter signals with large phase modulation (for special market
areas).
* Video buffer
The video buffer is required to provide a low ohmic video output with the right amplitude and to protect
this output for the occurrence of noise peaks, refer to figure below. The video buffer also contains a
level shifter and gain stage for positive and negative modulation in order to provide a correct video
amplitude and DC level.
The video buffer bandwidth is typical 9 MHz. The video output amplitude is 2.2Vpp (sync inclusive),
independent of the supply voltage. A white spot clamp prevents the video amplitude becoming greater
than 5.3V typical. A noise clamp prevents the video output becoming less than 1.7V typical. (Top sync
is approx. 2V) For strong signal only, the noise peak is inverted to black level.
zero level white spot clamp
top white
zero levelnoise inv. clamptop sync.
1
2
3
4
5
Video out
[V]
Negative Positive
Fig 1: Video signal for negative and positive modulation
The IF part can be switched-off by means of I²C bus command VSW. The internal CVBS input than
can be used (with minimum components) as external input, for instance for satellite.

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* AGC
An AGC system controls the IF amplifier gain such that the video output amplitude is constant.
The demodulated video signal is supplied, via a low pass filter, to an AGC detector with external
decoupling capacitor. The AGC detector voltage controls directly the IF gain stages.
Negative/positive modulation:
For optimal AGC behavior the charge and discharge current of the AGC are chosen so that both, a
relative fast AGC, as well a low tilt are possible for positive and negative modulated signals with the
same AGC capacitor.
A SECAM-L speed-up circuit improves the AGC settling time after IF-signal loss.
With tilt is mend the video amplitude variation due to less "memory" function of the AGC capacitor). In
Fig 2 the tilt is given during a field period for positive modulated signals. For negative modulated
signals the tilt is line frequent. For negative modulated signals the AGC is a top sync detector.
Positive modulation:
For positive modulated signals the AGC is a top white AGC including black level clamp which making
the video amplitude independent of video contents.
A top white AGC requires a 100% white reference pulse in order to be independent of video contents.
Suitable for that purpose is the white pulse (Video Insertion Test Signal, VITS) in line 17 and 330 - see
Fig 2.
Because the time constant is large (AGC current is decreased for positive modulation) the AGC will be
independent of the video contents between the reference pulses.
The maximum tilt per field is defined by the external capacitor, the AGC steepness and the small
discharge current in this mode.
//
one field
100% white
tilt
AGC voltage
Reference
pulse Video output
signal
Fig 2: Positive modulated signal with top white reference pulse
This top white AGC however is not optimal for those signals that have neither a white reference pulse
or white video information (e.g. with some VCR signals). Due to the top level AGC principle a gray
scene becomes white and a dark scene becomes gray, see Fig 3. This behavior can be avoided by
means of the black level clamp.

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Original video signal
with/without ref. pulse Demodulated signal on video output
Not optimal behaviour Optimal behaviour
Ref
pulse
100%
Ref pulse 100%, luma 50%
Ref pulse, top white<100%
50%
100%
50%
a
100%
Top white AGC only
b
Ref
pulse
100%
Top white AGC
Black clamp AGC
50%
100%
50%
c
Fig 3: Top white and black clamp AGC
The Fig 3 “b” shows that the video amplitude is increased by the top white AGC, such that 100% white
is obtained. As a consequence the black level increases also.
The black level clamp AGC in “c” prevents this behavior and becomes automatically active if the video
black level on the video output increases.
In the external mode only the top white AGC is active. The black clamp AGC than is switched off
because the internal signal is not synchronized any more to the horizontal oscillator.
SECAM-L speed-up circuit:
In case of positive modulation and large reduction of the incoming IF-input level a speed-up circuit is
needed. This because the AGC action is slow since the AGC discharge current is small (450nA), for
minimizing the tilt.
The speed-up circuit measures the amplitude of the video output signal and will react after
approximately 60ms if the video output is continuously below 80% white level.
If the speed-up is activated the AGC capacitor will be discharged with a current of 50mA.
* Tuner AGC
The tuner AGC is provided to reduce the tuner gain and thus the tuner output voltage when receiving
strong RF signals. The tuner AGC takes over when the IF input reaches a certain input level, that can
be adjusted by I²C function AGC take over.
The tuner gain can be reduced by means of the open collector output pin 54.
* AFC
AFC output information is available for search tuning. With the alignment free concept this AFC
information is very accurate and derived via a counter. The AFC output is available by the I²C bus
outputs AFA, AFB.
The AFC window width can be increased by means of I²C bus AFW. This allows bigger frequency
steps during search tuning.
Notice: AFC information is updated once a field during the vertical retrace and only valid when the
coincidence detector is in-lock (SL=1)
* Video identification
The IF-part includes a stand-alone video identification circuit. This makes the ident function
independent of the sync part. The ident output is available by I²C bus, IFI, and can be used during
search tuning and for automatic sound mute in full scart application.
The video ident circuit measures the main frequency of the input signal, which should be
approximately 16kHz.The video ident. can be connected to the "internal" video signal or to the
selected CVBS input signal.

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IF Amplifier
VCO
PLL
FFl FastFilter IF
Tuner
take over
adjust
MOD
Gating
AGC
detector LPF
LPF
Demodulator
Calibrator
AFC
IFA, IFB, IFC
IF frequency selection
AFW
AFA
AFB
fsc
MOD
pos. / Neg. VSW
Video mute
Video
Ident
IF1
PLLloopfilter
AGCdecoupling
N.C.
IF input 1
IF input 2
Tuner AGCout
IF Video out
4
3
48
49
54
53
6
5
Fig 4 : Block diagram: Vision IF

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1.1.3 Sound
See also the related block diagram as well as the diagrams at the end of the report.
The main functions are:
* Limiter
* PLL-Demodulator
* Pre-amplifier and mute
* Audio switch
* Volume controlled amplifier
These functions will be described next.
* Limiter
The sound carrier signal is supplied to this limiter input via an external bandpass filter. This external
bandpass filter is used for selectivity, the internal filter at the pin is used for noise reduction. The limiter
consists of AC coupled amplifier stages. The minimum input amplitude for limiting is typical 1mVrms.
The input impedance is 8K5 in parallel with 5pF.
* PLL-Demodulator
Sound demodulation is achieved by a PLL FM-demodulator and does not need any external
alignment.
The PLL has been optimized for a low S/N ratio with still an acceptable power consumption. The PLL
catching range is 4.2 - 6.8MHz, which is suitable for all multistandard applications.
* Pre-amplifier and mute
The pre-amplifier output signal available at the deemphasis pin can be used for SCART application. At
this pin the deemphasis capacitor has to be connected. The output level is 500mVrms for a FM swing
of 50kHz.
A pre-amplifier with DC feedback has been provided. The DC component of the deemphasis signal is
always 3V, also during sound mute. Sound mute plop is therefore minimized.
When no video signal is identified the deemphasis output is automatically muted.
* Audio switch
An audio switch has been provided for full SCART function. The audio switch is controlled by the I2C
bus Source Select INA/INC. For positive modulation, MOD, the external sound input is automatically
selected for an external AM sound demodulator.
* Volume controlled amplifier
The volume control is active for both internal and external audio signals. The nominal gain is +9dB and
minimal -71dB, which gives a total control range of 80dB minimal.

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Limiter
Sound decoupling
AVLdecoupling
Ext. audio in
1
2
45
56
15
55
AVL
-6dB
0 / -6dB
LPF
BPF
PLLdemodulator
Loopfilter Pre-amplifier
Audio
switch
AVLVolumeFAV
Fixed audio
INA, INB
INC, MOD
XA= 0: 0dB
XA= 1: -6dB
VCO
Automatic volume level
Volume control
1 - 10MHz
15k
3V
+15dB
-71dB
500mVrms
max. 2Vrms
500mVrms @ 50kHz swep
250mVrms @ 25kHz sweep
AVLfeature not
on all models
Sound mute:
INTmode via: SL = 0, SM = 1
EXTmode via: IFl = 0, SM = 1
STB= 0 ; SM = 1
No mute ; VIM = 1
Sound IF in Deemphasis /
Audio line-out
Audio out
Fig 5: Block diagram: Sound

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1.1.4 Horizontal and vertical synchronization
See also the related block diagram as well as the diagrams at the end of the report.
The main functions are:
* Horizontal sync separator
* Horizontal oscillator and calibration system
* PHI-1 detector
* PHI-2 detector and sandcastle generation
* Horizontal output with slow start/stop facility
* Coincidence detector
* Noise detector
* Vertical sync separator
* Vertical divider system
* Horizontal sync separator
The horizontal sync separator is supplied from the CVBS/Y inputs (chosen video source). For
horizontal synchronization the sync separator slices in the middle of the sync pulse and the slicing
level is independent of the sync pulse amplitude. For the vertical synchronization the sync pulse is
sliced at a level of about 30% (closer to the black level). This ensures optimal output signals for a
stable horizontal and vertical deflection under various video input conditions.
The top sync level is clamped at the CVBS input. The black level is stored internally.
* Horizontal oscillator and calibration system
The horizontal oscillator requires no external components and is fully integrated. The adjustment for
nominal frequency is derived automatically by a calibration circuit.
The oscillator generates a sawtooth signal with double horizontal frequency. This sawtooth signal is
used to derive several other gating and timing signals. After calibration the horizontal oscillator is
controlled by the PHI-1 loop for synchronization with the incoming video input signal.
The calibrator is responsible for the automatic adjustment of the horizontal oscillator. One of the color
crystals is being used as reference. For that reason a correct crystal selection by XA,XB (Xtal
selection) is very important during power-on. Calibration occurs during the vertical retrace period and
only under following conditions:
- At power-on/ initialization
- After power dip (shutdown detection), re-initialization is required.
- After loss of synchronization (e.g. after channel switching)
* PHI-1 detector
The PHI-1 detector is a PLL circuit that synchronizes the horizontal oscillator with the incoming video
signal. The PLL compares the output of the H-sync separator with the horizontal oscillator. The PLL
output current is converted to a voltage by means of the external loop filter. This voltage controls the
horizontal oscillator. The loop filter is connected externally so the time constant can be defined
according to the customer requirements. Because the static loop gain is very high there will be no
phase shift when switching between input signals with different line.
* PHI-2 detector and sandcastle
As described, the Horizontal PLL (PHI-1 loop) synchronizes the horizontal oscillator with the incoming
video signal. The PHI-2 loop provides a stable picture position on screen.
This is necessary because due to beam current variations the storage time of the line transistor varies
and, due to that, the picture position on screen.
The PHI-2 detector compares the horizontal oscillator signal (reference) with the horizontal flyback
input pulse, pin 41. This flyback pulse is related to the horizontal deflection.
The PHI-2 circuit shifts the horizontal drive, pin 40, such that the picture position on screen is constant.
The flyback input pin 41 is combined with the sandcastle output. This combined function provides a
three level sandcastle signal and is available starting with the highest level: burstkey, line blanking (=
flyback pulse) and vertical blanking.
The phase of the video signal with respect to the deflection current can be adapted by I²C bus HS
(horizontal shift, shift picture left/right).
The PHI-2 loop filter is a first order filter. The capacitor is connected externally on pin 42.