Panasonic KX-T7453 User manual

ORDER NO. KMS0104563C1
F5
DIGITAL PROPRIETARY TELEPHONE
KX-T7453 / KX-T7453B
White Version
Black Version
(for U.S.A.)
SPECIFICATIONS

1. CAUTION
Note:
When you note the serial number, write down all of the 11 digitals.
The serial number may be found on the label affixed to the bottom of the unit.
2. FOR SERVICE TECHNICIANS
1. Note the following items when exchanging the LEDs (Ref. No. D100-
130, D201, D202) of Dial P.C. Board.
1) Do not reuse a LED which is removed from the P.C. Board.
2) Use a soldering iron (less than 15 W) for exchanging LED.
3) Do not heat the LED for more than 2 seconds.
4) Do not move the LED after soldering.
2. This unit employs the switch which is influenced by the light for the
hook switch.
When you open the cabinet to repair the unit in the bright light, the
hook switch might work improperly.
Therefore, take care not to shine the hook switch directly, or use the
jig as shown below.
3. LOCATION OF CONTROLS
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4. DISASSEMBLY INSTRUCTIONS
4.1. HOW TO REMOVE THE LOWER CABINET
(Procedure 1)
(1) Remove the 4 screws A.
(2) Remove the lower cabinet.
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4.2. HOW TO REMOVE THE HOOK BUTTON
(Procedure 1 2)
(1) Remove the hook button.
4.3. HOW TO REMOVE THE SWITCH AND MAIN BOARDS
(Procedure 1 2 3)
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(1) Remove the screws A.
(2) Pull out the switch board connector.
(3) Remove the switch board.
(4) Pull out the flat cable. (See Fig. 1)
(5) Remove the 2 screws B.
(6) Pull out the speaker and microphone connectors.
(7) Remove the main board.
4.4. HOW TO REMOVE THE LCD BOARD
(Procedure 1 4)
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(1) Pull out the flat cable. (See Fig. 1)
(2) Remove the LCD block. (See Fig. 2)
(3) Remove the 2 screws A.
(4) Remove the lower cabinet.
(5) Remove the LCD board.
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5. IC DATA
5.1. IC1
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Name Pin Dir. Pull Up Type Io Act. Block MHz Descriptions
DB3 2 bidir --- TTL 8.0mA high PT5B03 2.0 Data Bus [3]
DB2 3 bidir --- TTL 8.0mA high PT5B03 2.0 Data Bus [2]
DB1 4 bidir --- TTL 8.0mA high PT5B03 2.0 Data Bus [1]
DB0 5 bidir --- TTL 8.0mA high PT5B03 2.0 Data Bus [0]
ADR1 6 input 12-38k TTL --- high PT5D01U 2.0 Address Bus [1]
ADR0 7 input 12-38k TTL --- high PT5D01U 2.0 Address Bus [0]
CSN 8 input --- TTL --- low PT5D01 1.0 Chip Select
REN 10 input 12-38k TTL --- low PT5D01U 2.0 Read Enable Command
WEN 9 input 12-38k TTL --- low PT5D01U 2.0 Write Enable Command
RST 63 input --- CMOS
schmidt
--- high PC5D21 0.01 Asynchronous Reset In
p
INT0N 11 output --- CMOS 2.0mA low PC5O01 0.01 Interrupt Request
INT1N 12 output --- CMOS 2.0mA low PC5O01 0.01 Interrupt Request
DR0 38 input --- CMOS --- low PC5D01 0.6 Dpits Receive Data [1]
DR1 39 input --- CMOS --- low PC5D01 0.6 Dpits Receive Data [0]
DX0 40 output --- CMOS 4.0mA low PC5O02 0.6 Dpits Transmit Data [1]
DX1 41 output --- CMOS 4.0mA low PC5O02 0.6 Dpits Transmit Data [0]
CK512K 37 output --- CMOS 2.0mA high PC5O01 0.6 Dpits Bit Rate Clock
SR0 19 input 12-38k TTL --- high PT5D01U 0.1 Serial Receive Data
Stream [0]
SR1 20 input 12-38k TTL --- high PT5D01U 0.1 Serial Receive Data
Stream [1]
SX 21 output --- CMOS 4.0mA high PC5O02 0.1 Serial Transmit Data
Stream
CK2M 18 output --- CMOS 4.0mA high PC5O02 2.1 Serial Stream Clock
EP0 13 output --- CMOS 2.0mA high PC5O01 0.01 External Channel Pulse
[
EP1 14 output --- CMOS 2.0mA high PC5O01 0.01 External Channel Pulse
[
EP2 15 output --- CMOS 2.0mA high PC5O01 0.01 External Channel Pulse
[
EP3 16 output --- CMOS 2.0mA high PC5O01 0.01 External Channel Pulse
[
PI 61 input --- CMOS
schmidt
--- high PC5D21 0.01 Rotary Encoder Input
[Pos]
NI 62 input --- CMOS
schmidt
--- high PC5D21 0.01 Rotary Encoder Input
[Neg]
CLM0 43 output --- CMOS 4.0mA high PC5O02 0.01 LED Column Drive [0]
CLM1 44 output --- CMOS 4.0mA high PC5O02 0.01 LED Column Drive [1]
CLM2 45 output --- CMOS 4.0mA high PC5O02 0.01 LED Column Drive [2]
CLM3 46 output --- CMOS 4.0mA high PC5O02 0.01 LED Column Drive [3]
CLM4 47 output --- CMOS 4.0mA high PC5O02 0.01 LED Column Drive [4]
CLM5 48 output --- CMOS 4.0mA high PC5O02 0.01 LED Column Drive [5]
NROW0 50 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [0]
NROW1 51 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [1]
NROW2 52 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [2]
NROW3 53 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [3]
NROW4 54 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [4]
NROW5 55 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [5]
NROW6 56 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [6]
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NROW7 57 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [7]
NROW8 58 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [8]
NROW9 59 output --- CMOS 4.0mA low PC5O02 0.01 LED Row Drive [9]
IP0 27 input 12-38k CMOS --- high PC5D01U 0.01 Input Port [0]
IP1 28 input 12-38k CMOS --- high PC5D01U 0.01 Input Port [1]
IP2 29 input 12-38k CMOS --- high PC5D01U 0.01 Input Port [2]
IP3 30 input 12-38k CMOS --- high PC5D01U 0.01 Input Port [3]
OP0 23 output CMOS 4.0mA high PC5O02 0.01 Output Port [0]
OP1 24 output CMOS 4.0mA high PC5O02 0.01 Output Port [1]
OP2 25 output CMOS 4.0mA high PC5O02 0.01 Output Port [2]
OP3 26 output CMOS 4.0mA high PC5O02 0.01 Output Port [3]
CK2K 22 output CMOS 4.0mA high PC5O02 0.20 2kHz Clock Output (dut
y
25%)
CK16M 36 output --- CMOS 2.0mA high PC5O01 16.4 Master Clock Out
OSI 33 input --- Analog --- --- PC5X02 16.4 X'tal In (XIN)
OSO 34 output --- Analog --- --- PC5X02 16.4 X'tal Out (XOUT)
N.C. 32 not used
N.C. 42 not used
N.C. 60 not used
VDD1 1 vdd Vdd (5V)
VDD2 31 vdd Vdd (5V)
VDD3 49 vdd Vdd (5V)
VSS1 17 vss Vss (GND)
VSS2 35 vss Vss (GND)
VSS3 64 vss Vss (GND)
5.2. IC2
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Name NO. I/O Classification Function
APMP 1 Analog
input
Analog Non-inverting input terminal of microphone amplifier M1.
Connect to the microphone.
VREFDA 2--- Power.
supply, etc.
Reference voltage teminal of DAC.
Connect the capacitor of 40 F between this terminal and p
i
(AG2).
AG1 3 Ground terminal of the analog circuit.
HO+ 4Analog
output
Analog Output terminal for the handset receiver.
HO+ terminal and HO- terminal are biased to Vdd/2 voltage.
HO- terminal is the inverse porality output terminal for pin 4 (
H
+).
Connect the capacitor in series between the handset and the
s
terminals to cut the DC.
Use the nonpolar type capacitor.
HO- 5
A5V1 6 --- Power
supply, etc.
5V power supply terminal of analog circuit.
A5V2 7
SPO 8 Analog
output
Analog Output treminal for the speaker amplifier.
Connect to the external speaker amplifier input terminal.
SPO terminal is biased to Vdd/2 voltage.
Connect the capacitor of 0.1 F in series between the exter
n
speaker amplifier input terminal and this terminal.
AG2 9 --- Powers
supply, etc.
Ground terminal of the analog circuit.
P/-S 10 CMOS
input
Micro-
computer
interface
Mode selection terminal of microcomputer interface.
Inputting “0“ selects the serial mode, and “1“ selects the
parallel mode.
-RESET 11 System reset terminal.
The system is reset when “0“ is pressed.
DG1 12 --- Powers
supply, etc.
Ground terminal of the digital circuit.
OP0 13 3 states
output
Output port Outputs BIT0 signal of OPORT1 resistor.
OP1 14 Outputs BIT1 signal of OPORT1 resistor.
D5V1 15 --- Powers
supply, etc.
5V power supply terminal of digital circuit.
OP2 16 3 states
output
Output
Outputs BIT2 signal of OPORT1 resistor.
OP3 17 Outputs BIT3 signal of OPORT1 resistor.
OP4 18 Outputs BIT4 signal of OPORT1 resistor.
OP5 19 Outputs BIT5 signal of OPORT1 resistor.
OP6 20 Outputs BIT6 signal of OPORT1 resistor.
OP7 21 Outputs BIT7 signal of OPORT1 resistor.
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RXD 22 TTL
input
PCM
interface
Input terminal for PCM data.
TXD 23 output Output terminal for PCM data
-FSYNC 24 TTL
input
Input terminal of Sync. signal for PCM interface. The frequen
c
of input sync.
signal is 8 kHz.
BCLK 25 Input terminal of shift clock pulse for PCM deta. Input pulse
frequency range is 64 kHz~2.048 kHz.
PCM data (TXD termianl signal) is output st the positive edge
.
PCM data (RXD terminal signal) is sampled at the negative ed
The sameling is performed inside LSI.
MCLK 26 Output Clock Clock pulse output terminal. Output pulse frequency is
6.144MHz.
System reset (inputting “0” to -RESET terminal) doesn’t stop
this output.
CLKO 27 Clock pulse output terminal which has selective frequencies.
The following 4 frequencies can be selected by resistor setti
n
12.228, 4.096, 2.048, 1.536 (MHz).
System reset (inputting “0” to -RESET terminal) selects the
frequency of 1.536MHz and doesn’t stop this output.
DG2 28 --- Power
supply, etc.
Ground terminal of digital circuit.
OSCI 29 --- Clock Input terminal of oscillation circuit.
Connect the oscillator and resistor berween this terminal and
pin 30 (OSCO), moreover, connect the capacitor between thi
s
terminal and digital ground to make the oscillation circuit.
OSCO 30 --- Output terminal of oscillation circuit.
Connect the oscillator and resistor berween this terminal and
pin 29 (OSCI), moreover, connect the capacitor between this
terminal and digital ground to make the oscillation circuit.
D5V2 31 --- Power
supply, etc.
5V power supply terminal of digital circuit.
-INT 44 Output Micro-
computer
interface
Outputs 8 kHz clock pulse which is synchronized with -FSYN
C
TEST 45 CMOS
input
Power
supply, etc.
Test terminal
Connect to the digital ground.
A5V3 46 --- 5V power supply terminal of analog circuit.
HI 47 Analog
input
Analog Input terminal of TX handset signal.
Either this signal or the signal supplied to pin 49 (HI) is input
AD converter.
VBB 48 --- Power
supply, etc.
Reference voltage terminal of AD converter.
Connect the capacitor of 10 F between VBB terminal and
p
50 (AG3).
MI 49 Analog
input
Analog Input terminal of TX microphone signal.
Either this signal or the signal supplied to pin 47 (HI) is input
AD converter.
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AG3 50 --- Power
supply, etc.
Ground terminal of analog circuit.
A5V4 51 5V power terminal of analog circuit.
AP2HO 52 Analog
output
Analog
Output terminal of microphone amplofier H2.
Connect the capacitor of 0.1 F to this terminal to cut the D
C
AP2HI 53 Analog
input
Inverting input terminal of microphone amplofier H2.
Connect the capacitor of 0.1 F to this terminal to cut the D
C
AP1HO 54 Analog
output
Output terminal of microphone amplofier H1.
Connect the capacitor of 0.1 F to this terminal to cut the D
C
AP1HN 55 Analog
input
Inverting input terminal of microphone amplofier H1.
Connect to the handset.
AP1HP 56 Analog
input
Analog Non-inverting input terminal of microphone amplofier H1.
VREFM 57 --- Power
supply, etc.
Reference voltage terminal of microphone amplifier.
Connect the capacitor of 40 F between this terminal and p
i
56 (MICG).
AG4 58 Ground terminal of analog circuit.
APMO 59 Analog
input Analog
Output terminal of microphone amplifier.
Connect the capacitor of 0.1 F to this terminal to cut the D
C
APMN 60 Analog
input
Non-inverting input terminal of microphone amplofier M.
6. BLOCK DIAGRAM
7. CIRCUIT OPERATIONS
7.1. KEY INPUT CONTROL CIRCUIT
1) Circuit Operation
Sequential input information (negativa logic) from the DSHS proprietary telephone is executed by
dynamic scanning.
The ports RR70 to RR73, RR80 to RR83 of IC6 are brought to low status consecutively.
If a key is pressed, the key-in information input is executed by ports R91 to R93, RB1, RB11, RB21,
RB0, RD1.
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7.2. LCD CONTROL CIRCUIT
1) Circuit Operation
The LCD data is output from pins 32 to 35, 40 to 47 and 11 of IC6.
LCD contrast adjustment is performed by the circuit composed of Q28, Q29, R109, R108 and R106.
The contrast is determined only by the voltage level between V5 and VEE of IC202 and IC201.
Higher potential makes the contrast high.
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15

7.3. LED CIRCUIT
1) Circuit Operation
The LED executes dynamic lighting for the status indicators, and control is executed by the output
ports C0 to C5 (column) and R0 to R9 of IC1.
A fixed pulse (T=1.82 msec) is output continuously from the/SCK1 terminal of IC9. This pulse is
counted and the output of IC1 is shifted sequentially from C0 to C5.
R0 to R7 of IC1 also output pulses, and the lighting of the LED is controlled by the timing of the output
ports C0 to C5.
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7.4. DATA COMMUNICATION CIRCUIT
1) Function
The data communication circuit serves the following functions:
Information exchanger between the DSHS and DSHS proprietary telephone, key input information as
well as data for the LED control, LCD control, etc. This information is continuously exchanged at all
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times.
2) Circuit Operation
When the DSHS propritary telephone receives an IRQ signal from the DSHS and after sending the key
input information to the DSHS and receivung data for the LED control, etc., the DSHS proprietary
telephone will return to the DSHS an acknowledge signal.
3) Reception
The data from the DSHS is received via the H and L lines along the path shown below.
H, L Line T1 IC11 Pin 5, 10 IC1 Pin 38, 39 IC1 Pin 21 IC2 Pin 22
4) Transmission
The data to the DSHS proprietary telephone is transmitted along the following path.
IC2 Pin 23 IC1 Pin 20 IC1 Pin 40, 41 Q1, Q2 T1 H, L Line
5) IC1 (GATE ARRAY) DPITS Interface
DPITS Layer 1 interface. DR [1:0] is receiving input and DX [1:0] is transmitting output.
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Layer 1 is the transmission method of Ping-Pong type which is AMI encoded. “SYNC/MAM/C/D/B1/B2/
P” data is received in the first half at 125us/frame. After 1 bit time has passed since receiving P data,
“SYNC/MAM/C/D/B1/B2/P” is transmitted. 1 bit time is 512kHz. 7-bit time idle term comes after
receiving P data.
6) PCM interface (between IC1 and IC2)
PCM interface consists of following 4 terminals.
The first PCM data is output from TXD at the positive edge of -FSYNC. The second data and the
followings are output at the positive edge of BCLK. After all data of 8 bit are output, the last data is
kept until the positive edge of next -FSYNC. The positive edge of BCLK should be within ±100ns from
the positive edge of -FSYNC.
The PCM data input from RXD is sampled at the negative edge of BCLK inside LSI. The sampling of
the first data is performed between the positive edge of -FSYNC and the first negative edge of BCLK.
After completing the sampling of all data of 8 bit, this sampling pauses until the next positive edge of -
FSYNC.
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7.5. RESET CIRCUIT
1) Circuit Operation
This circuit is used for transmission of a reset pulse to the CPU (IC6) at the following times,
connecting the telephone line jack and circuit operation.
The timing chart is shown below.
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