Philips CBTD3306 Operational manual

1. General description
The CBTD3306 dual FET bus switch features independent line switches. Each switch is
disabled when the associated output enable (nOE) input is HIGH.
The CBTD3306 is characterized for operation from −40 °C to +85 °C.
2. Features and benefits
Designed to be used in 5 V to 3.3 V level shifting applications with internal diode
5Ωswitch connection between two ports
TTL-compatible input levels
Multiple package options
Latch-up protection exceeds 100 mA per JESD78B
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM JESD22-C101E exceeds 1000 V
3. Ordering information
4. Marking
CBTD3306
Dual bus switch with level shifting
Rev. 8 — 1 May 2012 Product data sheet
Table 1. Ordering information
Type number Package
Name Description Version
CBTD3306D SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
CBTD3306PW TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 4.4 mm SOT530-1
CBTD3306GT XSON8 plastic extremely thin small outline package; no leads; 8 terminals;
body 1 ×1.95 ×0.5 mm SOT833-1
CBTD3306GM XQFN8 plastic, extremely thin quad flat package; no leads; 8 terminals;
body 1.6 ×1.6 ×0.5 mm SOT902-2
Table 2. Marking codes
Type number Marking code
CBTD3306D CBD3306
CBTD3306PW D306
CBTD3306GT W06
CBTD3306GM W06

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 2 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 1. Logic diagram
1OE
1A 1B
2B
002aab985
2OE
2A
2
1
5
7
3
6
Fig 2. Pin configuration for SO8 (SOT96-1) Fig 3. Pin configuration for TSSOP8 (SOT530-1)
CBTD3306
1OE V
CC
1A 2OE
1B 2B
GND 2A
001aak832
1
2
3
4
6
5
8
7
CBTD3306
1OE V
CC
1A 2OE
1B 2B
GND 2A
001aak833
1
2
3
4
6
5
8
7
Fig 4. Pin configuration SOT833-1 (XSON8) Fig 5. Pin configuration SOT902-2 (XQFN8)
CBTD3306
2B
2OE
V
CC
2A
1B
1A
1OE
GND
001aal404
36
27
18
45
Transparent top view
001aal405
2B1A
2OE
V
CC
2A
1OE
GND
1B
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
CBTD3306

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 3 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
8. Limiting values
[1] Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under Section 9. is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
[2] The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
9. Recommended operating conditions
Table 3. Pin description
Symbol Pin Description
1OE, 2OE 1, 7 output enable input
1A, 2A 2, 5 data input/output (A port)
1B, 2B 3, 6 data input/output (B port)
GND 4 ground (0 V)
VCC 8 positive supply voltage
Table 4. Function selection[1]
Input Input/output
nOE nA, nB
LnA=nB
HZ
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Tamb = − 40 ° C to +85 ° C, unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7.0 V
VIinput voltage [2] −0.5 +7.0 V
ISW switch current - 128 mA
IIK input clamping current VI/O =0V −50 - mA
Tstg storage temperature −65 +150 °C
Table 6. Operating conditions
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 4.5 - 5.5 V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
Tamb ambient temperature operating in free air −40 - +85 °C

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 4 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
10. Static characteristics
[1] All typical values are at VCC =5V,T
amb =25°C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3] Measured by the voltage drop between the nA and the nB terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (nA or nB) terminals.
Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = −40 °C to +85 °CUnit
Min Typ[1] Max
VIK input clamping voltage VCC =4.5V;I
I=−18 mA - - −1.2 V
IIinput leakage current VCC =5.5V;V
I= GND or 5.5 V - - ±1μA
ICC supply current VCC =5.5V;I
SW =0mA;
VI=V
CC or GND --1.5mA
Vpass pass voltage see Figure 6 to Figure 10 ---V
ΔICC additional supply current per input pin; VCC =5.5V;
one input at 3.4 V, other inputs at
VCC or GND
[2] --2.5mA
CIinput capacitance control pin; VI= 3 V or 0 V - 3.2 - pF
Cio(off) off-state input/output
capacitance port off; VI= 3 V or 0 V; nOE =V
CC -6.5-pF
RON ON resistance VCC =4.5V;V
I=0V;I I=64mA [3] -3.65Ω
VCC =4.5V;V
I=0V;I I=30mA [3] -3.65Ω
VCC =4.5V;V
I=2.4V;I I=15mA [3] -1735Ω

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 5 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
10.1 Typical pass voltage graphs
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
Fig 6. Pass voltage versus supply voltage;
Tamb =85°C (typical) Fig 7. Pass voltage versus supply voltage; Tamb =70°C (typical)
001aak834
VCC (V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
Vpass
(V)
2.0
(4)
(3)
(1)
(2)
001aak835
VCC (V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
Vpass
(V)
2.0
(4)
(1)
(2)
(3)
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
Fig 8. Pass voltage versus supply voltage;
Tamb =25°C (typical) Fig 9. Pass voltage versus supply voltage; Tamb =0°C (typical)
001aak836
VCC (V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
Vpass
(V)
2.0
(4)
(1)
(2)
(3)
001aak837
VCC (V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
Vpass
(V)
2.0
(4)
(1)
(3)
(2)

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 6 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
(1) ISW = 100 μA
(2) ISW = 6 mA
(3) ISW =12 mA
(4) ISW = 24 mA
Fig 10. Pass voltage versus supply voltage; Tamb =−40 °C (typical)
001aak838
VCC (V)
4.4 5.65.24.8
2.8
2.4
3.2
3.6
Vpass
(V)
2.0
(1)
(3)
(2)
(4)

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 7 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
11. Dynamic characteristics
[1] The propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
12. Waveforms
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions Tamb = −40 °C to +85 °CUnit
Min Typ Max
tpd propagation delay nA, nB to nB, nA; see Figure 11 [1][2] - - 0.25 ns
VCC = 5.0 V ±0.5 V
ten enable time nOE to nA or nB; see Figure 12 [2] 1.0 - 5.4 ns
VCC = 5.0 V ±0.5 V
tdis disable time nOE to nA or nB; see Figure 12 [2] 1.0 - 4.9 ns
VCC = 5.0 V ±0.5 V
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The data input (nA, nB) to output (nB, nA) propagation delay times
001aak305
tPLH
tPHL
VM
VM
nB, nA
output
nA, nB
input
VI
GND
VOH
VOL

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 8 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
001aak298
t
PLZ
t
PHZ
outputs
disabled outputs enabled
V
Y
V
X
outputs
enabled
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
nOE input
V
I
3.5 V
V
M
V
M
V
OL
V
OH
GND
GND
t
PZL
t
PZH
V
M
V
M
Table 9. Measurement points
Supply voltage Input Output
VCC VIVMVMVXVY
VCC = 5.0 V ±0.5 V GND to 3.0 V 1.5 V 1.5 V VOL + 0.3 V VOH −0.3 V

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 9 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
13. Test information
Test data is given in Table 10.
All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz; Zo=50Ω.
The outputs are measured one at a time with one transition per measurement.
Definitions for test circuit:
RL= Load resistance.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to output impedance Zoof the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 13. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL RT
RL
RL
G
Table 10. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
VCC = 5.0 V ±0.5 V GND to 3.0 V ≤2.5 ns 50 pF 500 Ωopen 7.0 V open

CBTD3306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 8 — 1 May 2012 10 of 17
NXP Semiconductors CBTD3306
Dual bus switch with level shifting
14. Package outline
Fig 14. Package outline SOT96-1 (SO8)
UNIT A
max. A1A2A3bpcD
(1) E(2) (1)
eH
ELL pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8
0
o
o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
1.0
0.4
SOT96-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
4
5
pin 1 index
1
8
y
076E03 MS-012
0.069 0.010
0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
99-12-27
03-02-18