PLX Technology PCI 6152 Series Product guide

PCI 6152 (HB1-SE)
PCI-to-PCI Bridge
Data Book

PCI 6152 (HB1-SE)
PCI-to-PCI Bridge
Data Book
Version 2.0
May 2003
Website: http://www.plxtech.com
Technical Support: http://www.plxtech.com/support
Phone: [phone]
800 759-3735
Fax: [phone]

© 2003 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and
names are property of their respective owners.
These devices are not designed, intended, authorized, or warranted to be suitable for use in
medical, life-support applications, devices or systems or other critical applications.
PLX Part Number: PCI 6152-CC33BC; Former HiNT Part Number: HB1-SE33B
PLX Part Number: PCI 6152-CC33PC; Former HiNT Part Number: HB1-SE33P
PLX Part Number: PCI 6152-CC66BC; Former HiNT Part Number: HB1-SE66
Order Number: 6152-SIL-DB-P1-2.0
Printed in the USA, May 2003

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PCI 6152 PCI-to-PCI Bridge
The PLX PCI 6152 is a family of three very low power 32-bit PCI-to-PCI bridges: PCI 6152 33BC, PCI 6152 33PC
and PCI 6152 66PC. PCI 6152 66PC is capable of running at 66 MHz PCI Bus and PCI 6152 33BC and PCI 6152
33PC runs at 33 MHz. All parts are specially designed for applications that require high performance 32-bit PCI
bus expansion. Add-in card designers can use PCI 6152 to expand PCI connection capacity beyond the limitation
of a single PCI device. Designers can use PCI 6152 to build multi-device PCI cards such as RAID controllers and
other multimedia applications.
Part numbers and Description:
Part Number Description Package Type
PCI 6152 33BC 33 MHz, 32-bit PCI interface 160-pin Tiny BGA
PCI 6152 66PC 66 MHz, 32-bit PCI interface
(AGP 2x port compatible)
160-pin Tiny BGA
PCI 6152 33PC Intel 21152 pin compatible 33 MHz, 32-bit PCI interface 160-pin PQFP
•PCI Local Bus Specification Rev. 2.2 with VPD support
•PCI 6152 66BC is 66 MHz capable and PCI 6152 33BC and 33PC run at 33 MHz
•Synchronous primary and secondary PCI bus operation
•Compact PCI Hot Swap Friendly support with Ejector connection
•High performance, no retry penalty flow with uninterrupted 0 wait state burst up to 1K bytes
•Provides 4 Dwords buffering for posted write transactions and 4 Dwords for prefetchable read transactions
each direction
•PCI Mobile Design Guide Rev. 1.1
•Power Management D3 Cold Wakeup capable
•Concurrent primary and secondary port operation supports traffic isolation
•Provides programmable arbitration support for 4 bus masters on secondary interface
•5 Buffered secondary PCI clock outputs
•4 GPIO pins
•Enhanced address decoding
- Support 32-bit I/O address range
- Support 64-bit memory- address range
- ISA aware mode for legacy support in the first 64KB of I/O address range
- VGA addressing and VGA palette snooping support
•Supports 3.3V PCI with 5V tolerant I/O
PCI 6152
PCI-to-PCI
Bridge
Primary PCI Bus Secondary PCI Bus
GPIO Interface
Up to Four
Master PCI Devices

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History
Revision Date Description
1.1 3/27/01 Corrected register C4h, bit 4,5 description. Default should be 2 clocks delay.
1.2 4/9/01 Updated Company Address
1.3 4/24/01 Corrected description of register 28h and 2Ch register.
1.4 4/30/01 Updated Revision ID description at register 8h.
1.5 7/12/01 Enhanced EEPROM Section description.
2.0 05/28/03
This release reflects PLX part numbering.
!Changed “SRST_L to “S_RST_L”, 3 places, in Register 3Eh
!Changed Register 82h, bits 11-15 description
!Changed Dual Address Cycle (1101) values from “N” to “Y” in Table 8-1
!Globally changed LDEV, LDEV#, and DEVSEL to DEVSEL_L
!Changed Case 1 and 3 descriptions in Section 8.6
!Removed secondary clock information from bullet 2 and S_RST# bullets (4th and 6th)
from Section 13.2
!Updated Master on primary and secondary response in Section 14
!Removed synchronous design information from Section 16

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Contents
HISTORY ...................................................................................................................................................... 6
1 REGISTER INDEX............................................................................................................................... 11
2 INTRODUCTION ................................................................................................................................. 12
3 ORDERING INFORMATION ............................................................................................................... 12
4 PIN DIAGRAM..................................................................................................................................... 13
5 SIGNAL DEFINITION .......................................................................................................................... 14
5.1 PRIMARY BUS INTERFACE SIGNALS ..................................................................................................... 14
5.2 SECONDARY BUS INTERFACE SIGNALS ................................................................................................ 16
5.3 CLOCK SIGNALS ................................................................................................................................. 17
5.4 RESET SIGNALS ................................................................................................................................. 17
5.5 HOT SWAP SIGNALS ........................................................................................................................... 17
5.6 MISCELLANEOUS SIGNALS .................................................................................................................. 18
5.7 POWER SIGNALS ................................................................................................................................18
6 PIN ASSIGNMENT .............................................................................................................................. 19
6.1 PCI 6152 PINOUT TABLES.................................................................................................................. 20
6.1.1 Pin Assignment Sorted by Location .......................................................................................... 20
6.1.2 Pin Assignment Sorted by Signal Name ................................................................................... 22
7 CONFIGURATION REGISTERS......................................................................................................... 24
7.1 CONFIGURATION SPACE MAP – TRANSPARENT MODE.......................................................................... 24
7.2 CONFIGURATION REGISTER DESCRIPTION ........................................................................................... 26
8 PCI BUS OPERATION ........................................................................................................................ 45
8.1 TYPES OF TRANSACTIONS................................................................................................................... 45
8.2 ADDRESS PHASE................................................................................................................................46
8.3 DEVICE SELECT (DEVSEL_L) GENERATION ....................................................................................... 46
8.4 DATA PHASE ...................................................................................................................................... 46
8.5 WRITE TRANSACTIONS ....................................................................................................................... 47
8.6 READ TRANSACTIONS ......................................................................................................................... 47
8.7 CONFIGURATION TRANSACTIONS......................................................................................................... 48
8.7.1 Type 0 Access to PCI 6152....................................................................................................... 48
8.7.2 Type 1 to Type 0 Translation .................................................................................................... 49
8.7.3 Type 1 to Type 1 Forwarding .................................................................................................... 51
8.7.4 Special Cycles........................................................................................................................... 52
8.8 TRANSACTION TERMINATION ............................................................................................................... 53
8.8.1 Master Termination Initiated by PCI 6152................................................................................. 53
8.8.2 Master Abort Received by PCI 6152......................................................................................... 54
8.8.3 Target Termination Received by PCI 6152 ............................................................................... 54
8.8.4 Target Termination Initiated by PCI 6152 ................................................................................. 57
9 ADDRESS DECODING ....................................................................................................................... 58
9.1 ADDRESS RANGES ............................................................................................................................. 58
9.2 I/O ADDRESS DECODING .................................................................................................................... 58
9.2.1 I/O Base and Limit Address Registers ...................................................................................... 59

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9.2.2 ISA Mode................................................................................................................................... 60
9.3 MEMORY ADDRESS DECODING............................................................................................................ 60
9.3.1 Memory-Mapped I/O Base and Limit Address Registers .......................................................... 61
10 PCI BUS ARBITRATION ................................................................................................................. 62
10.1 PRIMARY PCI BUS ARBITRATION......................................................................................................... 62
10.2 SECONDARY PCI BUS ARBITRATION.................................................................................................... 62
11 TRANSACTION DELAY .................................................................................................................. 63
12 ERROR HANDLING ........................................................................................................................ 64
12.1 ADDRESS PARITY ERRORS.................................................................................................................. 64
12.2 DATA PARITY ERRORS........................................................................................................................ 65
12.2.1 Configuration Write Transactions to Configuration Space ........................................................ 65
12.2.2 Read Transactions .................................................................................................................... 65
12.3 DATA PARITY ERROR REPORTING SUMMARY ....................................................................................... 66
12.4 SYSTEM ERROR (SERR#) REPORTING ............................................................................................... 69
13 RESET.............................................................................................................................................. 70
13.1 PRIMARY INTERFACE RESET ............................................................................................................... 70
13.2 SECONDARY INTERFACE RESET .......................................................................................................... 70
14 BRIDGE BEHAVIOR ....................................................................................................................... 71
14.1 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)................................................................... 72
14.1.1 Master Abort.............................................................................................................................. 72
14.1.2 PCI Master on Primary Bus....................................................................................................... 72
14.2 CONFIGURATION TYPE #1 TO TYPE #0 CONVERSION ........................................................................... 72
14.3 CONFIGURATION TYPE #1 TO TYPE #1 BY-PASSING ............................................................................ 73
14.4 TYPE-0 CONFIGURATION CYCLE FILTER MODE .................................................................................... 73
14.5 DECODING ......................................................................................................................................... 73
14.6 SECONDARY MASTER ......................................................................................................................... 74
14.7 PCI CLOCK RUN FEATURE.................................................................................................................. 74
15 CLOCKS .......................................................................................................................................... 75
15.1 PRIMARY AND SECONDARY CLOCK INPUTS .......................................................................................... 75
15.2 SECONDARY CLOCK OUTPUTS ............................................................................................................ 75
16 66-MHZ OPERATION ...................................................................................................................... 76
17 MISCELLANEOUS OPTIONS ......................................................................................................... 77
17.1 EEPROM INTERFACE ........................................................................................................................ 77
17.1.1 Auto Mode EEPROM Access.................................................................................................... 77
17.1.2 EEPROM Mode at Reset .......................................................................................................... 77
17.1.3 EEPROM Data Structure .......................................................................................................... 78
17.1.4 EEPROM Address and Corresponding PCI 6152 Register ...................................................... 79
17.2 GENERAL PURPOSE I/O INTERFACE .................................................................................................... 80
17.3 VITAL PRODUCT DATA ........................................................................................................................ 80
18 PCI POWER MANAGEMENT.......................................................................................................... 81
19 HOT SWAP ...................................................................................................................................... 82
19.1 HOT SWAP INSERTION ........................................................................................................................ 82
19.2 HOT SWAP EXTRACTION ..................................................................................................................... 82

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20 PACKAGE SPECIFICATIONS ........................................................................................................ 83
20.1 160-PIN TINY BGA ............................................................................................................................. 83
20.2 160-PIN STANDARD PQFP.................................................................................................................. 85
21 ELECTRICAL SPECIFICATIONS.................................................................................................... 87
21.1 MAXIMUM RATINGS............................................................................................................................. 87
21.2 FUNCTIONAL OPERATING RANGE ........................................................................................................ 87
21.3 DC ELECTRICAL CHARACTERISTICS .................................................................................................... 88
21.4 PCI CLOCK SIGNAL AC PARAMETER MEASUREMENTS......................................................................... 89
21.4.1 33 MHz PCI Clock Signal AC parameters................................................................................. 89
21.4.2 66 MHz PCI Clock Signal AC parameters................................................................................. 90
21.5 PCI SIGNAL TIMING SPECIFICATION .................................................................................................... 90
21.5.1 33 MHz PCI Signal Timing ........................................................................................................ 91
21.5.2 66 MHz PCI Signal Timing ........................................................................................................ 91
APPENDIX A: PCI 6152 33PC PART DESCRIPTION............................................................................... 92
PCI 6152 33PC 160 PIN PINOUT................................................................................................................... 93
Pin Assignment Sorted by Location......................................................................................................... 93
Pin Assignment Sorted by Signal Name.................................................................................................. 95
PCI 6152 33PC VS 21152 PINOUT COMPARISON ........................................................................................... 97
APPENDIX B : SAMPLE SCHEMATICS.................................................................................................... 98
APPENDIX C: APPLICATION NOTES..................................................................................................... 104
PCI 6152 66BC APPLICATION NOTE 1: CONNECTING PCI 6152 66BC TO THE AGP INTERFACE ................... 104
INTRODUCTION ............................................................................................................................................ 104
TYPICAL APPLICATIONS ............................................................................................................................... 104
DESIGN CONSIDERATION ............................................................................................................................. 104
APPENDIX D: TIMING DIAGRAMS ......................................................................................................... 105
FIGURE 1 : PRIMARY TO SECONDARY TYPE 1 TO TYPE 0 CONFIGURATION CYCLE CONVERSION..................... 105
FIGURE 2 : PRIMARY TO SECONDARY TYPE 1 TO TYPE 1 CONFIGURATION CYCLE PASSING............................ 106
FIGURE 3 : SECONDARY TO PRIMARY MEMORY READ LINE TRANSACTION...................................................... 107
FIGURE 4 : PRIMARY TO SECONDARY MEMORY READ TRANSACTION............................................................. 108
FIGURE 5 : SECONDARY TO PRIMARY MEMORY READ TRANSACTION............................................................. 109
FIGURE 6 : PRIMARY TO SECONDARY MEMORY WRITE TRANSACTION FOLLOWED
BY SECONDARY TO PRIMARY MEMORY WRITE TRANSACTION................................................... 110
FIGURE 7 : SECONDARY TO PRIMARY MEMORY WRITE TRANSACTION............................................................ 111

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1 Register Index
Arbiter Control Register .............................................................34
Bridge Control Register .............................................................32
Cache Line Size Register ..........................................................29
Capability Identifier........................................................36, 37, 38
Chip Control Register ................................................................33
Class Code Register..................................................................29
Clkrun Register..........................................................................35
Data Register ............................................................................37
Device ID Register.....................................................................26
ECP Pointer...............................................................................31
EEPROM Address.....................................................................43
EEPROM Control ......................................................................43
EEPROM Data ..........................................................................43
GPIO Control Register...............................................................42
Header Type Register................................................................29
Hot Swap Register.....................................................................38
Hot Swap Switch .......................................................................38
I/O Base Address Upper 16 Bits Register..................................31
I/O Base Register ......................................................................29
I/O Limit Address Upper 16 Bits Register ..................................31
I/O Limit Register.......................................................................29
Internal Arbiter Control Register ................................................41
Interrupt Pin Register.................................................................32
Memory Base Register ..............................................................31
Memory Limit Register...............................................................31
Miscellaneous Control Register........................................... 40, 41
Next Item Pointer .......................................................... 36, 37, 38
PCI 6152 Test Register............................................................. 44
PMCSR Bridge Support ............................................................ 37
Power Management Capabilities............................................... 36
Power Management Control/ Status.......................................... 37
Prefetchable Memory Base Register......................................... 31
Prefetchable Memory Base Register Upper 32 Bits .................. 31
Prefetchable Memory Limit Register ......................................... 31
Prefetchable Memory Limit Register Upper 32 Bits ................... 31
Primary Bus Number Register................................................... 29
Primary Command Register ...................................................... 26
Primary Latency Timer Register................................................ 29
Primary Status Register ............................................................ 28
Revision ID Register ................................................................. 29
Secondary Bus Number Register .............................................. 29
Secondary Clock Control Register ............................................ 34
Secondary Latency Timer ......................................................... 29
Secondary Status Register........................................................ 30
Subordinate Bus Number Register............................................ 29
Subsystem ID ........................................................................... 44
Subsystem Vendor ID ............................................................... 44
Vendor ID Register.................................................................... 26
VPD Data Register.................................................................... 39
VPD Register ............................................................................ 39

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2 Introduction
This document describes the implementation and functionality of PLX’s 32-bit, 66/33 MHz PCI 6152 PCI-to-PCI
Bridge chip. The specification includes required function and limitations.
PCI 6152 has the following features:
•PCI Local Bus Specification Revision 2.2 features including VPD
•Support delayed transactions for PCI configuration, I/O and memory read commands
•Provides memory write data buffering in both directions
•Provides concurrent primary and secondary bus operation to isolate traffic
•Provides separate arbitration support for individual secondary port
- Programmable 2-level arbiter
•Enhanced address decoding
- 32-bit I/O and memory address decoding
•Supports PCI transaction forwarding for
- Type 1 to Type 0 downstream only configuration commands
- Type 1 to Type 1 configuration commands
- Type 1 configuration write to special cycle
•Three-stating of I/O during power up and power down
•Supports 3.3V, 5V tolerant signaling
3 Ordering Information
The following parts are available:
Part Number Description Package Type
PCI 6152-CC33BC 33 MHz, 32-bit PCI interface160-pin Tiny BGA
PCI 6152-CC66BC 66 MHz, 32-bit PCI interface
(AGP2x port compatible)
160-pin Tiny BGA
PCI 6152-CC33PC * 33 MHz, 32-bit PCI interface160-pin PQFP
Mechanical specifications for each package type can be found in the appendix.
* Refer to Appendix A for detailed information about this part.

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4 Pin Diagram
P_CLK
P_RST_L
P_REQ_L
P_GNT_L
P_FRAME_
P_IRDY_L
P_TRDY_L
P_DEVSEL
P_STOP_L
P_AD[31:0]
P_CBE[3:0]
P_PAR
P_PERR_L
S_FRAME_L
S_IRDY_L
S_TRDY_L
P_IDSEL
S_GNT_L[3:0]
PCI 6152
Primary
PCI
BUS
Secondary
PCI
BUS
S_DEVSEL_L
S_STOP_L
S_AD[31:0]
S_CBE[3:0]
S_PAR
S_REQ_L[3:0]
S_RST_L
S_SERR_L
P_SERR_L
S_PERR_L
ENUM_L
L_STAT
HOT
PLUG
S_CLKOUT[4:0]
S_CLKRUN
S_CLK
P_CLKRUN
EJECT Misc.
SVIO
PVIO
GPIO[3:0]
BCCP_EN
EEPDATA
EEPCLK
GOZ_L
NAND_O

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5 Signal Definition
Signal Types
PI PCI Input (5V tolerant, I/O VDD=3.3V)
PTS PCI Three-state bidirectional(5V tolerant, I/O VDD=3.3V)
PO PCI Output
PSTS PCI Sustained three-state Output. (Active LOW signal which must be driven inactive for
one cycle before being three-stated to ensure HIGH performance on a shared signal
line)
OD Output which either drives LOW (active state) or is three-stated
I CMOS Input
O CMOS Output
IO CMOS Bidirect
5.1 Primary Bus Interface Signals
Name Type Description
P_AD[31:0] PTS Primary address/data: Multiplexed address and data bus. Address is
indicated by P_FRAME_L assertion. Write data is stable and valid when
P_IRDY_L is asserted and read data is stable and valid when P_TRDY_L
is asserted. Data is transferred on rising clock edges when both
P_IRDY_L and P_TRDY_L are asserted. During bus idle, PCI 6152 drives
P_AD to a valid logic level when P_GNT_L is asserted.
P_CBE[3:0] PTS Primary command/byte enables: Multiplexed command field and byte
enable field. During address phase, the initiator drives the transaction type
on these pins. After that the initiator drives the byte enables during data
phases. During bus idle, PCI 6152 drives P_CBE[3:0] to a valid logic level
when P_GNT_L is asserted.
P_PAR PTS Primary Parity: Parity is even across P_AD[31:0], P_CBE[3:0], and
P_PAR (i.e. an even number of ‘1’s). P_PAR is an input and is valid and
stable one cycle after the address phase (indicated by assertion of
P_FRAME_L) for address parity. For write data phases, P_PAR is an
input and is valid one clock after P_IRDY_L is asserted. For read data
phase, P_PAR is an output and is valid one clock after P_TRDY_L is
asserted. Signal P_PAR is three-stated one cycle after the PAD lines are
three-stated. During bus idle, PCI 6152 drives PPAR to a valid logic level
when P_GNT_L is asserted.
P_FRAME_L PSTS Primary FRAME: Driven by the initiator of a transaction to indicate the
beginning and duration of an access. The deassertion of P_FRAME_L
indicates the final data phase requested by the initiator. Before being
three-stated, it is driven to a deasserted state for one cycle.

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P_IRDY_L PSTS Primary IRDY: Driven by the initiator of a transaction to indicate its ability
to complete the current data phase on the primary side. Once asserted in
a data phase, it is not deasserted until end of the data phase. Before
being three-stated, it is driven to a deasserted state for one cycle.
P_TRDY_L PSTS Primary TRDY: Driven by the target of a transaction to indicate its ability
to complete the current data phase on the primary side. Once asserted in
a data phase, it is not deasserted until end of the data phase. Before
being three-stated, it is driven to a deasserted state for one cycle.
P_DEVSEL_L PSTS Primary Device Select: Asserted by the target indicating that the device
is accepting the transaction. As a master, PCI 6152 waits for the assertion
of this signal within 5 cycles of P_FRAME_L assertion; otherwise,
terminate with master abort. Before being three-stated, it is driven to a
deasserted state for one cycle.
P_STOP_L PSTS Primary STOP: Asserted by the target indicating that the target is
requesting the initiator to stop the current transaction. Before being three-
stated, it is driven to a deasserted state for one cycle.
P_IDSEL PI Primary ID Select. Used as chip select line for Type 0 configuration
access to PCI 6152 configuration space.
P_PERR_L PSTS Primary Parity Error: Asserted when a data parity error is detected for
data received on the primary interface. Before being three-stated, it is
driven to a deasserted state for one cycle.
P_SERR_L OD Primary System Error: Can be driven LOW by any device to indicate a
system error condition, PCI 6152 drives this pin on
•Address parity error
•Posted write data parity error on target bus
•Secondary bus S_SERR_L asserted
•Master abort during posted write transaction
•Target abort during posted write transaction
•Posted write transaction discarded
•Delayed write request discarded
•Delayed read request discarded
•Delayed transaction master timeout
This signal is pulled up through an external resistor.
P_REQ_L PTS Primary Request: This is asserted by PCI 6152 to indicate that it wants
to start a transaction on the primary bus. PCI 6152 deasserts this pin for
at least 2 PCI clock cycles before asserting it again.
P_GNT_L PI Primary Grant: When asserted, PCI 6152 can access the primary bus.
During idle and P_GNT_L asserted, PCI 6152 will drive P_AD, P_CBE
and P_PAR to valid logic level.

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5.2 Secondary Bus Interface Signals
Name Type Description
S_AD[31:0] PTS Secondary Address/Data: Multiplexed address and data bus. Address is
indicated by S_FRAME_L assertion. Write data is stable and valid when
S_IRDY_L is asserted and read data is stable and valid when S_TRDY_L
is asserted. Data is transferred on rising clock edges when both
S_IRDY_L and S_TRDY_L are asserted. During bus idle, PCI 6152 drives
S_AD to a valid logic level when the S_GNT_L is asserted
S_CBE[3:0] PTS Secondary Command/Byte Enables: Multiplexed command field and
byte enable field. During the address phase, the initiator drives the
transaction type on these pins. After that the initiator drives the byte
enables during data phases. During bus idle, PCI 6152 drives S_CBE[3:0]
to a valid logic level when the internal grant is asserted.
S_PAR PTS Secondary Parity: Parity is even across S_AD[31:0], S_CBE[3:0], and
S_PAR (i.e. an even number of ‘1’s). S_PAR is an input and is valid and
stable one cycle after the address phase (indicated by assertion of
S_FRAME_L) for address parity. For write data phases, S_PAR is an
input and is valid one clock after S_IRDY_L is asserted. For read data
phase, S_PAR is an output and is valid one clock after S_TRDY_L is
asserted. Signal S_PAR is three-stated one cycle after the S_AD lines are
three-stated. During bus idle, PCI 6152 drives S_PAR to a valid logic level
when the internal grant is asserted.
S_FRAME_L PSTS Secondary FRAME: Driven by the initiator of a transaction to indicate the
beginning and duration of an access. The deassertion of S_FRAME_L
indicates the final data phase requested by the initiator. Before being
three-stated, it is driven to a deasserted state for one cycle
S_IRDY_L PSTS Secondary IRDY: Driven by the initiator of a transaction to indicate its
ability to complete the current data phase on the primary side. Once
asserted in a data phase, it is not deasserted until end of the data phase.
Before being three-stated, it is driven to a deasserted state for one cycle.
S_TRDY_L PSTS Secondary TRDY: Driven by the target of a transaction to indicate its
ability to complete the current data phase on the primary side. Once
asserted in a data phase, it is not deasserted until end of the data phase.
Before being three-stated, it is driven to a deasserted state for one cycle.
S_DEVSEL_L PSTS Secondary Device Select: Asserted by the target indicating that the
device is accepting the transaction. As a master, PCI 6152 waits for the
assertion of this signal within 5 cycles of S_FRAME_L assertion;
otherwise, terminate with master abort. Before being three-stated, it is
driven to a deasserted state for one cycle.
S_STOP_L PSTS Secondary STOP: Asserted by the target indicating that the target is
requesting the initiator to stop the current transaction. Before being three-
stated, it is driven to a deasserted state for one cycle.
S_PERR_L PSTS Secondary Parity Error: Asserted when a data parity error is detected
for data received on the primary interface. Before being three-stated, it is
driven to a deasserted state for one cycle.
S_SERR_L PI Secondary System Error: Can be driven LOW by any device to indicate
a system error condition.

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S_REQ_L[3:0] PI Secondary Requests: This is asserted by external device to indicate that
it wants to start a transaction on the Secondary bus. They are external
pulled up through resistors to VDD.
S_GNT_L[3:0] PO Secondary Grant: PCI 6152 asserts this pin to access the secondary
bus. PCI 6152 deasserts this pin for at least 2 PCI clock cycles before
asserting it again. During idle and S_GNT_L asserted, PCI 6152 will drive
S_AD, S_CBE and S_PAR to valid logic levels.
5.3 Clock Signals
Name Type Description
P_CLK I Primary CLK input: Provides timing for all transaction on primary
interface.
S_CLK I Secondary CLK input: Provides timing for all transaction on secondary
interface.
S_CLKOUT[4:0] O Secondary CLK output: Provides secondary clocks phase synchronous
with the P_CLK.
5.4 Reset Signals
Name Type Description
P_RST_L I Primary Reset: When P_RST_L is active, outputs and should be
asynchronously three-stated and P_SERR_L and P_GNT_L floated.
S_RST_L PO Secondary Reset: Asserted when any of the following conditions is met:
1. Signal P_RST_L is asserted.
2. The secondary reset bit in the bridge control register in configuration
space is set.
When asserted, all control signals are three-stated and zeros are driven
on S_AD, S_CBE and S_PAR.
5.5 Hot Swap Signals
Name Type Description
ENUM_L O Hot Swap Interrupt: An open drain bussed signal to signal a change in
status for the chip. Leave floating if not used.
EJECT I Hot Swap Eject: Indicates the status of software connection process. If
pin is used to detect the insertion of Hot Swap devices. Pin should be tied
to ground if not used.
L_STAT IO Hot Swap LED: Indicates the status of software connection process.
Signal should be pulled down to ground if not used.

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5.6 Miscellaneous Signals
Name Type Description
P_CLKRUN_L I/OD Primary CLKRUN: Used by the central resource to stop the PCI clock or
to slow it down. If not used, this pin should be connected to ground to
signify that PCLK is always running.
S_CLKRUN_L I/O Secondary CLKRUN: Drive high to stop or slow down secondary PCI
clock, driven by secondary PCI device to keep clock running. If secondary
PCI devices do not support CLKRUN#, this pin needs to be pulled low by
a 300ohm resistor.
BPCC_EN I Bus/power clock control management pin. When signal is tied high
and the PCI 6152 is placed in the D3hot power state, the PCI 6152 places
the secondary bus in the B2 power state. The PCI 6152 disables the
secondary clocks and drives them to 0. When tied low, placing the PCI
6152 in the D3hot power state has no effect on the secondary bus clocks.
GPIO[3:0] PTS General Purpose Input Output pins. These 4 general purpose signals
are programmable as either input-only or bi-directional signals by writing
the GPIO output enable control register
EEPCLK O EEPROM Clock. This pin is the clock signal to the EEPROM interface
used during autoload and for VPD functions.
EEPDATA I/O EEPROM Serial Data. This pin is serial data interface to the EEPROM.
PVIO I Primary Interface I/O Voltage This signal must be tied to either 3.3V or
5V, depending on the signaling voltage of the primary interface.
SVIO I Secondary Interface I/O Voltage This signal must be tied to either 3.3V
or 5V, depending on the signaling voltage of the secondray interface.
GOZ_L I Diagnostic three-state control. This signal, when asserted, three-states
all bidirectional and three-statable output pins. This pin must be pulled
high or connected to VDD for normal operation.
NAND_O O Nand tree diagnostic output. This signal is dedicated to the diagnostic
Nand tree. The GOZ_L signal should be asserted when the Nand tree
mechanism is used.
5.7 Power Signals
Name Type Description
VDD +3.3V
VSS Ground

PCI 6152 Data Book v2.0


2003 PLX Technology, Inc. All rights reserved. 19
6 Pin Assignment
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VSS
VSS
SPAR
VDD
10 11 12 13 14987654321
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDDVSS
VSS
SDEVSEL_L
SFRAME_L
SAD22
VSS
SAD19
SAD16
SREQ0_L
GPIO0
SAD29
SAD24
SSERR_L
SAD21
SAD31
SAD28
SIRDY_L
SAD26
SSTOP_L
SCBE3_L
VSS
SAD18
SCBE2_L
SAD30
SAD23
EEPD
SAD25
SPERR_L
STRDY_L
SREQ1_L
SAD17
SAD27
SAD20
VSS
VDD
VDD
VDD VDD VDDVSS
VDD
VDD
VSS
VSS
VSS
VDDVSS
VSS
SGNT0_L
SGNT1_L
SGNT2_L
PAD27
GPIO2PAD31SRST_L
PGNT_LSVIOSGNT3_L PAD24
PAD29
SCLK0
SCLK1SCLK
PAD28
SCLK2
RST_L
GPIO1
SCLK3
PAD30
PCLK
PAD25
SCLK4 PAD26
GOZ_L PVIO
NAND_O
PREQ_L
PAD9
PAD10
GPIO3
PAD21
PAD12
PAD19
PCBE1_L
PDEVSEL_L
PFRAME_L
PAD20
PAD15
PAD18
PAD22
PTRDY_L
PSERR_L
PAD17
PAD13
PAD11
PSTOP_L
PIRDY_L
PPERR_L EEPCLK
PAD14
CBE2_LPAD16
PPAR
PAD23
PAD8
SCBE1_L SAD15
SCLKRUN_L
SAD14
SAD13
ENUM_L
SAD10
SAD12
SAD11
SCBE0_L
SAD8
SAD9
SAD6
SAD5
SAD7
SAD1
SAD0
PAD1
SAD2
SAD4
L_STATSAD3 PAD7PAD4
PAD0
PAD6
PAD5PAD2
BPCCE
SREQ2_L
VSS
SREQ3_L
VDD
VSS
VSS
PIDSEL
CBE3_L
VSS
CBE0_L
EJECT
PCLKRUN_LPAD3
PCI 6152 Top View

PCI 6152 Data Book v2.0


2003 PLX Technology, Inc. All rights reserved. 20
6.1 PCI 6152 Pinout Tables
6.1.1 Pin Assignment Sorted by Location
Location Pin Name Type
A01 BPCCE I
A02 S_CBE_L[1] TS
A03 S_AD[15] TS
A04 S_AD[13] TS
A05 S_AD[10] TS
A06 S_CBE_L[0] TS
A07 S_AD[05] TS
A08 S_AD[04] TS
A09 S_AD[01] TS
A10 P_AD[01] TS
A11 P_AD[03] TS
A12 P_AD[06] TS
A13 P_CBE_L[0] TS
A14 P_CLKRUN_L TS
B01 S_PAR TS
B02 VSS P
B03 S_CLKRUN_L TS
B04 ENUM_L TS
B05 S_AD[11] TS
B06 S_AD[08] TS
B07 S_AD[06] TS
B08 S_AD[03] TS
B09 S_AD[00] TS
B10 L_STAT TS
B11 P_AD[04] TS
B12 P_AD[07] TS
B13 VSS P
B14 P_AD[08] TS
C01 S_PERR_L TS
C02 S_SERR_L I
C03 VSS P
C04 S_AD[14] TS
C05 S_AD[12] TS
C06 S_AD[09] TS
C07 S_AD[07] TS
C08 S_AD[02] TS
C09 P_AD[00] TS
C10 P_AD[02] TS
C11 P_AD[05] TS
C12 VSS P
C13 P_AD[09] TS
C14 EJECT I
D01 S_TRDY_L STS
D02 S_DEVSEL_L STS
D03 S_STOP_L STS
D04 VSS P
D05 VSS P
D06 VDD P
D07 VDD P
D08 VDD P
D09 VDD P
D10 VSS P
D11 VSS P
D12 P_AD[10] TS
D13 P_AD[11] TS
D14 P_AD[12] TS
E01 EEPD I/O
E02 S_FRAME_L STS
E03 S_IRDY_L STS
E04 VSS P
E11 VSS P
E12 P_AD[13] TS
E13 P_AD[14] TS
E14 P_AD[15] TS
F01 S_AD[17] TS
F02 S_AD[16] TS
F03 S_CBE_L[2] TS
F04 VDD P
F11 VDD P
F12 P_CBE_L[1] TS
F13 P_PAR TS
F14 P_SERR_L OD
G01 S_AD[20] TS
G02 S_AD[19] TS
G03 S_AD[18] TS
G04 VDD P
G11 VDD P
G12 P_PERR_L STS
G13 EEPCLK O
G14 P_STOP_L STS
H01 S_AD[21] TS
H02 S_AD[22] TS
H03 S_AD[23] TS
H04 VDD P
H11 VDD P
H12 P_IRDY_L STS
H13 P_TRDY_L STS
H14 P_DEVSEL_L STS
J01 S_CBE_L[3] TS
J02 S_AD[24] TS
J03 S_AD[25] TS
J04 VDD P
J11 VDD P