PLX Technology PCI 6152 Series Product guide

PCI 6152 (HB1-SE)
PCI-to-PCI Bridge
Data Book

PCI 6152 (HB1-SE)
PCI-to-PCI Bridge
Data Book
Version 2.0
May 2003
Website: http://www.plxtech.com
Technical Support: http://www.plxtech.com/support
Phone: [phone]
800 759-3735
Fax: [phone]

© 2003 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and
names are property of their respective owners.
These devices are not designed, intended, authorized, or warranted to be suitable for use in
medical, life-support applications, devices or systems or other critical applications.
PLX Part Number: PCI 6152-CC33BC; Former HiNT Part Number: HB1-SE33B
PLX Part Number: PCI 6152-CC33PC; Former HiNT Part Number: HB1-SE33P
PLX Part Number: PCI 6152-CC66BC; Former HiNT Part Number: HB1-SE66
Order Number: 6152-SIL-DB-P1-2.0
Printed in the USA, May 2003

PCI 6152 Data Book v2.0
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2003 PLX Technology, Inc. All rights reserved. 5
PCI 6152 PCI-to-PCI Bridge
The PLX PCI 6152 is a family of three very low power 32-bit PCI-to-PCI bridges: PCI 6152 33BC, PCI 6152 33PC
and PCI 6152 66PC. PCI 6152 66PC is capable of running at 66 MHz PCI Bus and PCI 6152 33BC and PCI 6152
33PC runs at 33 MHz. All parts are specially designed for applications that require high performance 32-bit PCI
bus expansion. Add-in card designers can use PCI 6152 to expand PCI connection capacity beyond the limitation
of a single PCI device. Designers can use PCI 6152 to build multi-device PCI cards such as RAID controllers and
other multimedia applications.
Part numbers and Description:
Part Number Description Package Type
PCI 6152 33BC 33 MHz, 32-bit PCI interface 160-pin Tiny BGA
PCI 6152 66PC 66 MHz, 32-bit PCI interface
(AGP 2x port compatible)
160-pin Tiny BGA
PCI 6152 33PC Intel 21152 pin compatible 33 MHz, 32-bit PCI interface 160-pin PQFP
•PCI Local Bus Specification Rev. 2.2 with VPD support
•PCI 6152 66BC is 66 MHz capable and PCI 6152 33BC and 33PC run at 33 MHz
•Synchronous primary and secondary PCI bus operation
•Compact PCI Hot Swap Friendly support with Ejector connection
•High performance, no retry penalty flow with uninterrupted 0 wait state burst up to 1K bytes
•Provides 4 Dwords buffering for posted write transactions and 4 Dwords for prefetchable read transactions
each direction
•PCI Mobile Design Guide Rev. 1.1
•Power Management D3 Cold Wakeup capable
•Concurrent primary and secondary port operation supports traffic isolation
•Provides programmable arbitration support for 4 bus masters on secondary interface
•5 Buffered secondary PCI clock outputs
•4 GPIO pins
•Enhanced address decoding
- Support 32-bit I/O address range
- Support 64-bit memory- address range
- ISA aware mode for legacy support in the first 64KB of I/O address range
- VGA addressing and VGA palette snooping support
•Supports 3.3V PCI with 5V tolerant I/O
PCI 6152
PCI-to-PCI
Bridge
Primary PCI Bus Secondary PCI Bus
GPIO Interface
Up to Four
Master PCI Devices

PCI 6152 Data Book v2.0
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History
Revision Date Description
1.1 3/27/01 Corrected register C4h, bit 4,5 description. Default should be 2 clocks delay.
1.2 4/9/01 Updated Company Address
1.3 4/24/01 Corrected description of register 28h and 2Ch register.
1.4 4/30/01 Updated Revision ID description at register 8h.
1.5 7/12/01 Enhanced EEPROM Section description.
2.0 05/28/03
This release reflects PLX part numbering.
!Changed “SRST_L to “S_RST_L”, 3 places, in Register 3Eh
!Changed Register 82h, bits 11-15 description
!Changed Dual Address Cycle (1101) values from “N” to “Y” in Table 8-1
!Globally changed LDEV, LDEV#, and DEVSEL to DEVSEL_L
!Changed Case 1 and 3 descriptions in Section 8.6
!Removed secondary clock information from bullet 2 and S_RST# bullets (4th and 6th)
from Section 13.2
!Updated Master on primary and secondary response in Section 14
!Removed synchronous design information from Section 16

PCI 6152 Data Book v2.0
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Contents
HISTORY ...................................................................................................................................................... 6
1 REGISTER INDEX............................................................................................................................... 11
2 INTRODUCTION ................................................................................................................................. 12
3 ORDERING INFORMATION ............................................................................................................... 12
4 PIN DIAGRAM..................................................................................................................................... 13
5 SIGNAL DEFINITION .......................................................................................................................... 14
5.1 PRIMARY BUS INTERFACE SIGNALS ..................................................................................................... 14
5.2 SECONDARY BUS INTERFACE SIGNALS ................................................................................................ 16
5.3 CLOCK SIGNALS ................................................................................................................................. 17
5.4 RESET SIGNALS ................................................................................................................................. 17
5.5 HOT SWAP SIGNALS ........................................................................................................................... 17
5.6 MISCELLANEOUS SIGNALS .................................................................................................................. 18
5.7 POWER SIGNALS ................................................................................................................................18
6 PIN ASSIGNMENT .............................................................................................................................. 19
6.1 PCI 6152 PINOUT TABLES.................................................................................................................. 20
6.1.1 Pin Assignment Sorted by Location .......................................................................................... 20
6.1.2 Pin Assignment Sorted by Signal Name ................................................................................... 22
7 CONFIGURATION REGISTERS......................................................................................................... 24
7.1 CONFIGURATION SPACE MAP – TRANSPARENT MODE.......................................................................... 24
7.2 CONFIGURATION REGISTER DESCRIPTION ........................................................................................... 26
8 PCI BUS OPERATION ........................................................................................................................ 45
8.1 TYPES OF TRANSACTIONS................................................................................................................... 45
8.2 ADDRESS PHASE................................................................................................................................46
8.3 DEVICE SELECT (DEVSEL_L) GENERATION ....................................................................................... 46
8.4 DATA PHASE ...................................................................................................................................... 46
8.5 WRITE TRANSACTIONS ....................................................................................................................... 47
8.6 READ TRANSACTIONS ......................................................................................................................... 47
8.7 CONFIGURATION TRANSACTIONS......................................................................................................... 48
8.7.1 Type 0 Access to PCI 6152....................................................................................................... 48
8.7.2 Type 1 to Type 0 Translation .................................................................................................... 49
8.7.3 Type 1 to Type 1 Forwarding .................................................................................................... 51
8.7.4 Special Cycles........................................................................................................................... 52
8.8 TRANSACTION TERMINATION ............................................................................................................... 53
8.8.1 Master Termination Initiated by PCI 6152................................................................................. 53
8.8.2 Master Abort Received by PCI 6152......................................................................................... 54
8.8.3 Target Termination Received by PCI 6152 ............................................................................... 54
8.8.4 Target Termination Initiated by PCI 6152 ................................................................................. 57
9 ADDRESS DECODING ....................................................................................................................... 58
9.1 ADDRESS RANGES ............................................................................................................................. 58
9.2 I/O ADDRESS DECODING .................................................................................................................... 58
9.2.1 I/O Base and Limit Address Registers ...................................................................................... 59

PCI 6152 Data Book v2.0
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9.2.2 ISA Mode................................................................................................................................... 60
9.3 MEMORY ADDRESS DECODING............................................................................................................ 60
9.3.1 Memory-Mapped I/O Base and Limit Address Registers .......................................................... 61
10 PCI BUS ARBITRATION ................................................................................................................. 62
10.1 PRIMARY PCI BUS ARBITRATION......................................................................................................... 62
10.2 SECONDARY PCI BUS ARBITRATION.................................................................................................... 62
11 TRANSACTION DELAY .................................................................................................................. 63
12 ERROR HANDLING ........................................................................................................................ 64
12.1 ADDRESS PARITY ERRORS.................................................................................................................. 64
12.2 DATA PARITY ERRORS........................................................................................................................ 65
12.2.1 Configuration Write Transactions to Configuration Space ........................................................ 65
12.2.2 Read Transactions .................................................................................................................... 65
12.3 DATA PARITY ERROR REPORTING SUMMARY ....................................................................................... 66
12.4 SYSTEM ERROR (SERR#) REPORTING ............................................................................................... 69
13 RESET.............................................................................................................................................. 70
13.1 PRIMARY INTERFACE RESET ............................................................................................................... 70
13.2 SECONDARY INTERFACE RESET .......................................................................................................... 70
14 BRIDGE BEHAVIOR ....................................................................................................................... 71
14.1 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)................................................................... 72
14.1.1 Master Abort.............................................................................................................................. 72
14.1.2 PCI Master on Primary Bus....................................................................................................... 72
14.2 CONFIGURATION TYPE #1 TO TYPE #0 CONVERSION ........................................................................... 72
14.3 CONFIGURATION TYPE #1 TO TYPE #1 BY-PASSING ............................................................................ 73
14.4 TYPE-0 CONFIGURATION CYCLE FILTER MODE .................................................................................... 73
14.5 DECODING ......................................................................................................................................... 73
14.6 SECONDARY MASTER ......................................................................................................................... 74
14.7 PCI CLOCK RUN FEATURE.................................................................................................................. 74
15 CLOCKS .......................................................................................................................................... 75
15.1 PRIMARY AND SECONDARY CLOCK INPUTS .......................................................................................... 75
15.2 SECONDARY CLOCK OUTPUTS ............................................................................................................ 75
16 66-MHZ OPERATION ...................................................................................................................... 76
17 MISCELLANEOUS OPTIONS ......................................................................................................... 77
17.1 EEPROM INTERFACE ........................................................................................................................ 77
17.1.1 Auto Mode EEPROM Access.................................................................................................... 77
17.1.2 EEPROM Mode at Reset .......................................................................................................... 77
17.1.3 EEPROM Data Structure .......................................................................................................... 78
17.1.4 EEPROM Address and Corresponding PCI 6152 Register ...................................................... 79
17.2 GENERAL PURPOSE I/O INTERFACE .................................................................................................... 80
17.3 VITAL PRODUCT DATA ........................................................................................................................ 80
18 PCI POWER MANAGEMENT.......................................................................................................... 81
19 HOT SWAP ...................................................................................................................................... 82
19.1 HOT SWAP INSERTION ........................................................................................................................ 82
19.2 HOT SWAP EXTRACTION ..................................................................................................................... 82

PCI 6152 Data Book v2.0
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20 PACKAGE SPECIFICATIONS ........................................................................................................ 83
20.1 160-PIN TINY BGA ............................................................................................................................. 83
20.2 160-PIN STANDARD PQFP.................................................................................................................. 85
21 ELECTRICAL SPECIFICATIONS.................................................................................................... 87
21.1 MAXIMUM RATINGS............................................................................................................................. 87
21.2 FUNCTIONAL OPERATING RANGE ........................................................................................................ 87
21.3 DC ELECTRICAL CHARACTERISTICS .................................................................................................... 88
21.4 PCI CLOCK SIGNAL AC PARAMETER MEASUREMENTS......................................................................... 89
21.4.1 33 MHz PCI Clock Signal AC parameters................................................................................. 89
21.4.2 66 MHz PCI Clock Signal AC parameters................................................................................. 90
21.5 PCI SIGNAL TIMING SPECIFICATION .................................................................................................... 90
21.5.1 33 MHz PCI Signal Timing ........................................................................................................ 91
21.5.2 66 MHz PCI Signal Timing ........................................................................................................ 91
APPENDIX A: PCI 6152 33PC PART DESCRIPTION............................................................................... 92
PCI 6152 33PC 160 PIN PINOUT................................................................................................................... 93
Pin Assignment Sorted by Location......................................................................................................... 93
Pin Assignment Sorted by Signal Name.................................................................................................. 95
PCI 6152 33PC VS 21152 PINOUT COMPARISON ........................................................................................... 97
APPENDIX B : SAMPLE SCHEMATICS.................................................................................................... 98
APPENDIX C: APPLICATION NOTES..................................................................................................... 104
PCI 6152 66BC APPLICATION NOTE 1: CONNECTING PCI 6152 66BC TO THE AGP INTERFACE ................... 104
INTRODUCTION ............................................................................................................................................ 104
TYPICAL APPLICATIONS ............................................................................................................................... 104
DESIGN CONSIDERATION ............................................................................................................................. 104
APPENDIX D: TIMING DIAGRAMS ......................................................................................................... 105
FIGURE 1 : PRIMARY TO SECONDARY TYPE 1 TO TYPE 0 CONFIGURATION CYCLE CONVERSION..................... 105
FIGURE 2 : PRIMARY TO SECONDARY TYPE 1 TO TYPE 1 CONFIGURATION CYCLE PASSING............................ 106
FIGURE 3 : SECONDARY TO PRIMARY MEMORY READ LINE TRANSACTION...................................................... 107
FIGURE 4 : PRIMARY TO SECONDARY MEMORY READ TRANSACTION............................................................. 108
FIGURE 5 : SECONDARY TO PRIMARY MEMORY READ TRANSACTION............................................................. 109
FIGURE 6 : PRIMARY TO SECONDARY MEMORY WRITE TRANSACTION FOLLOWED
BY SECONDARY TO PRIMARY MEMORY WRITE TRANSACTION................................................... 110
FIGURE 7 : SECONDARY TO PRIMARY MEMORY WRITE TRANSACTION............................................................ 111

PCI 6152 Data Book v2.0
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