PLX PEX 8648-AA Quick user guide

PEX 8648-AA RDK
Hardware Reference Manual
Version 1.2
December 2010
Website: www.plxtech.com
Technical Support: www.plxtech.com/support
Copyright © 2010 by PLX Technology, Inc. All Rights Reserved – Version 1.2
December 6, 2010

© 2010 PLX Technology, Inc. All Rights Reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of
PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: 8648-AA RDK-HRM-1.2

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved ii
Contents
Preface ......................................................................................................................................................................iv
Notice .....................................................................................................................................................................iv
About This Manual .................................................................................................................................................iv
Revision History......................................................................................................................................................iv
1General Information .............................................................................................................................................1
1.1PEX 8648 Switch Features............................................................................................................................2
1.2PEX 8648 RDK Base Board Features...........................................................................................................2
2System Architecture.............................................................................................................................................3
3Hardware Architecture .........................................................................................................................................5
3.1PCI Express Port Configuration.....................................................................................................................5
3.2Non-Transparent Operation.........................................................................................................................12
3.3PCI Express Hot-Plug Circuitry ...................................................................................................................12
3.4Reference Clock Circuitry............................................................................................................................14
3.5Port Configuration and Status LED Indicators.............................................................................................16
3.5.1PORT STATUS LED Indicators............................................................................................................17
3.5.2UP PORT LED Indicators......................................................................................................................17
3.5.3NT PORT LED Indicators......................................................................................................................17
3.6Hardware Strapping Balls............................................................................................................................18
3.7Power Circuitry ............................................................................................................................................20
3.8Reset Circuitry.............................................................................................................................................21
3.9Serial EEPROM Interface (U2)....................................................................................................................21
3.10JTAG Interface (JP7)...................................................................................................................................22
3.11I2C Interface (JP8 and JP9).........................................................................................................................22
3.12Device-Specific Sideband Signals...............................................................................................................23
3.12.1FATAL_ERR# (TPV22, DS1)................................................................................................................23
3.12.2PEX_INTA# (TPV21, DS2) ...................................................................................................................23
3.12.3PEX_NT_RESET# (TPV49)..................................................................................................................23
4Base Board Mechanicals/Component Placement .............................................................................................24
4.1Monitoring Point, LED Indicator, and Control Summary .............................................................................25
4.1.1Monitoring Points ..................................................................................................................................25
4.1.2LED Indicators.......................................................................................................................................26
4.1.3Controls.................................................................................................................................................27
4.2Board Layout Information............................................................................................................................28
4.2.1Trace Routing Design Rules.................................................................................................................28
4.2.2Power De-Coupling...............................................................................................................................28
4.2.3PCB Layer Stackup...............................................................................................................................30
5References.........................................................................................................................................................31
6Bill of Materials & Schematics............................................................................................................................32

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved iii
Figures
Figure 1. PEX 8648 RDK Base Board Component Layout....................................................................................... 1
Figure 2. PEX 8648 RDK Being Used in a PC.......................................................................................................... 3
Figure 3. PEX 8648 RDK Base Board Component Layout....................................................................................... 4
Figure 4. Station 0, x4 UP and x4x4x4 DOWN ......................................................................................................... 7
Figure 5. Station 0, x16 UP ....................................................................................................................................... 7
Figure 6. Station 0, x8 UP and x8 DOWN (Factory Default)..................................................................................... 8
Figure 7. Station 0, x8 UP and x4x4 DOWN ............................................................................................................. 8
Figure 8. Station 0, x8 UP and x8 NT........................................................................................................................ 9
Figure 9. Station 0, x4 UP, x4 NT, and x4x4 DOWN................................................................................................. 9
Figure 10. Station 1, x4x4x4x4 DOWN.................................................................................................................... 10
Figure 11. Station 1, x16 DOWN............................................................................................................................. 10
Figure 12. Station 1, x8x8 DOWN (Factory Default)............................................................................................... 11
Figure 13. Station 1, x8x4x4 DOWN ....................................................................................................................... 11
Figure 14. PEX 8648 RDK Base Board PCI Express Hot-Plug Circuitry................................................................ 13
Figure 15. PEX 8648 RDK Base Board Reference Clock Circuitry......................................................................... 15
Figure 16. PEX 8648 RDK Base Board Port Configuration and Status LED Indicators ......................................... 16
Figure 17. PEX 8648 RDK Base Board Hardware Strapping DIP Switches – SW1, SW11,
SW4, SW5, SW9, SW6, SW2, and SW10, Default Settings..................................................................... 18
Figure 18. PEX 8648 RDK Base Board Power Circuitry......................................................................................... 20
Figure 19. JTAG Header (Top View)....................................................................................................................... 22
Figure 20. I2C Headers (Top View) ......................................................................................................................... 22
Figure 21. TPV21, TPV22, DS1, and DS2 Placement on PEX 8648 RDK Base Board......................................... 23
Figure 22. PEX 8648 RDK Base Board Mechanical Outline................................................................................... 24
Figure 23. PEX 8648 RDK Base Board Dimensions............................................................................................... 24
Figure 24. De-Coupling Capacitor Footprints.......................................................................................................... 28
Figure 25. PEX 8648 RDK Base Board Power Ball and Perimeter De-Coupling Capacitor Footprints
(Reverse Screen)...................................................................................................................................... 29
Figure 26. PEX 8648 RDK Base Board External PCB Layer Stackup Report........................................................ 30
Tables
Table 1. PEX 8648 RDK Base Board Port Configurations........................................................................................ 6
Table 2. PEX 8648 Switch Port Status LED On/Off Patterns, by State .................................................................. 17
Table 3. PEX 8648 RDK Base Board Hardware Strapping DIP Switches – SW1, SW11,
SW4, SW5, SW9, SW6, SW2, and SW10 ................................................................................................ 19
Table 4. PEX 8648 RDK Base Board Monitoring Points......................................................................................... 25
Table 5. PEX 8648 RDK Base Board LED Indicators............................................................................................. 26
Table 6. PEX 8648 RDK Base Board Controls ....................................................................................................... 27

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved iv
Preface
Notice
This manual contains PLX Confidential and Proprietary information. The contents of this manual may not be
copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.
PLX provides the information and data included in this manual for your benefit, but it is not possible to entirely
verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured
products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this
information. The information in this manual is subject to change without notice. Although every effort has been
made to ensure the accuracy of this manual, PLX shall not be liable for any errors, or incidental or consequential
damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes
no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which
may arise through the use of the PEX 8648 RDK, or for any damage or loss caused by deletion of data as a result
of malfunction or repair.
About This Manual
This Hardware Reference Manual describes the PLX PEX 8648 Rapid Development Kit (PEX 8648 RDK), from a
hardware perspective. It contains a description of all major functional circuit blocks on the PEX 8648 RDK base
board, and serves as a reference for creating software for this product. This manual also includes a complete Bill
of Materials and Schematics.
Revision History
Date Version Comments
March 2008 1.0 Initial release. Supports Board Revision 100, which includes
the PEX 8648 switch, Silicon Revision AA.
November 2008 1.1 Minor update.
December 2010 1.2 Updated the schematic and BOM to reflect the new 360K ohm R170
resistor.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 1
1 General Information
The PLX PEX 8648 RDK is a Rapid Development Kit based upon PLX Technology’s ExpressLane™ PEX 8648, a
48-Lane, 12-Port, 3-Station PCI Express Gen 2 switch. The PEX 8648 RDK provides a complete hardware and
software development platform to facilitate getting designs up and running quickly, lowering risk and reducing
time-to-market. The PEX 8648 RDK consists of a base board containing three PEX 8648 hardware modules, an
adapter board that plugs into the Host system, four mini-SAS cables and a SATA cable (used to connect the
adapter board to the base board), and a Software Development Kit (SDK). The SDK is downloadable from the
PLX web site, at www.plxtech.com/products/sdk.
This manual primarily focuses on the PEX 8648 RDK base board, and its use with other parts provided as part of
the RDK. Figure 1 provides a component-side view of the PEX 8648 RDK base board.
RefClk
1:12
Fanout
Configuration Module
SATA
37.34 cm (14.7 inches)
U11
P2 Configuration Module
P3
PEX8648
27 x 27
16
31
015
32
47
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN OPEN OPEN
Configuration Module
P1
Figure 1. PEX 8648 RDK Base Board Component Layout
Note: In Figure 1 and other figures in this manual that represent the base board, the Port-related LEDs indicate a
sample Port configuration. The figures do not show which LEDs are turned ON/OFF to match the indicated Port
width and Port Numbers.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 2
1.1 PEX 8648 Switch Features
48-Lane, 12-Port, 3-Station PCI Express Gen 2 switch
Standard 676-ball Flip Chip Plastic BGA (FCBGA) package (27 x 27 mm2) with Heat Spreader
480 GT/s aggregate bandwidth (5.0 GT/s/Lane x 48 SerDes Lanes x 2 (full duplex))
Non-blocking Crossbar Switch interface supports TLP bandwidth capacity of each x16 Link
Out-of-band communication/initialization interfaces (serial EEPROM and I2C)
2,048-byte Maximum Payload Size
Performance tuning
Choice of width (number of Lanes) per unique Link/Port – x4, x8, or x16
Allows any Port to be designated as the upstream Port (Port 0 is recommended)
Configuration with Strapping balls, serial EEPROM, or I2C
Lane reversal
Polarity reversal
Quality of Service (QoS) with one Virtual Channel (VC0) and eight Traffic Classes (TC[7:0])
Non-Transparent Bridging (NTB)
Read Pacing (intelligent bandwidth allocation)
Dual Cast
INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) ball
support
Compliant to the following specifications:
PCI Local Bus Specification, Revision 3.0
PCI Bus Power Management Interface Specification, Revision 1.2
PCI to PCI Bridge Architecture Specification, Revision 1.2
PCI Express Base Specification, Revision 2.0
PCI Express Card Electromechanical Specification, Revision 2.0
The I2C-Bus Specification, Version 2.1
1.2 PEX 8648 RDK Base Board Features
PLX PEX 8648 PCI Express Gen 2 switch in a 676-ball FCBGA package.
11 downstream PCI Express slot connectors. Hardware configuration is determined
by plug-in Configuration modules.
DIP switches, for hardware configuration of the PEX 8648 switch.
Transparent or Non-Transparent (NT) switch support.
Two Hot-Plug-controllable slots – one through a Parallel Hot-Plug Controller interface, and one through
the Serial Hot-Plug Controller interface.
Socketable serial EEPROM.
I
2C interface, to read and write registers.
Manual pushbutton PERST#.
LED indicators for visual inspection of Port configuration and status.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 3
2 System Architecture
The PEX 8648 RDK is a PLX Rapid Development Kit primarily intended for use by PLX customers for silicon
evaluation and design reference for PEX 8648 switches in the 27 x 27 mm2package. The PEX 8648 RDK
consists of three main hardware components:
Base board, which is meant to lay on a benchtop and houses the PEX 8648 switch
PCI Express slot-to-cable adapter board, which is meant to plug into a PC platform for the upstream Port
connection
Cable assembly, which connects the base board to the adapter board
Figure 2 provides a diagram of the PEX 8648 RDK, being used in a PC. Figure 3 represents the placement of
major component blocks on the PEX 8648 RDK base board.
The PEX 8648 RDK base board is similar to a motherboard in form factor. The base board is meant to lay on a
benchtop, and provides 11 PCI Express slots for add-in boards. Board power is supplied by an external ATX
supply (P5). The PEX 8648 RDK base board supports up to 12 Ports (one upstream and 11 downstream). By
default, the upstream Port is Port 0 and the NT Port is Port 1. All available Port width combinations are possible
with the PEX 8648 RDK, by means of Configuration modules that enable versatile routing of the Lanes from the
PEX 8648 switch to the PCI Express connectors. Controls are provided, to support Hot-Plug capability for Port 5
(Parallel Hot-Plug) and Port 8 (Serial Hot-Plug). On-board LED indicators display various configuration and status
information. The power distribution system for the PEX 8648 RDK is such that accurate current draw
measurements can be made, as well as supplying various PEX 8648 RDK base board supply voltages from an
external source, for the purposes of voltage margining.
SAS
SAS
SAS
SAS
SATA
PERST# REFCLK
Lanes 0-3
Lanes 4-7
Lanes 8-11
Lanes 12-15
Host
Motherboard
Adapter
RDK Base Board
RefClk
1:12
Fanout
Configuration Module
SATA
MICTOR
MICTOR
37.34 cm (14.7 inches)
37.34 cm (14.7 inches)
U11
CABLE SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SLOT 9 SLOT 10 SLOT 11
PORT
WIDTH
PORT
NUMBER
UP PORT
NT PORT
PORT STATUS
J1
J2
J3
J9
J10
J11
J6
J7
J8
J4
J5
IP1
IP2
IP3
IP4
P4
P5
P6
P7
P8
P9
P10
P11
J12 J13
J14
JP11
JP13
JP12
P2 Configuration Module
P3
SLOT8-HP SLOT5-HP
RESET
PERST
1.0VDC
2.5VDC
PEX8648
27 X 27
16
31
015
32
47
SAS
Lanes 4-7
SAS
Lanes 8-11
SAS
Lanes 12-15
SAS
Lanes 0-3
OPEN
OPEN OPEN
OPEN
OPEN
OPEN OPEN
OPEN
Configuration Module
P1
Figure 2. PEX 8648 RDK Being Used in a PC

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 4
Figure 3. PEX 8648 RDK Base Board Component Layout

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 5
3 Hardware Architecture
3.1 PCI Express Port Configuration
The PEX 8648 is a 48-Lane, 12-Port, 3-Station non-blocking PCI Express Gen 2 switch that supports Transparent
and NT modes of operation. The footprint for the PEX 8648 switch is laid out so that a heat sink can be attached
to the switch, or a high-speed BGA test socket can be loaded onto the PEX 8648 RDK base board.
The PEX 8648 RDK base board fixes the upstream Port at Port 0 and the NT Port at Port 1, by default. The
upstream Port connects to the Host through four mini-SAS cables that carry four Lanes each, and a serial ATA
cable that provides RefClk and PERST#. This is a significantly less-expensive and less-bulky solution than using
a PCI Express cable. On the Host side, the mini-SAS cables pass through the PC’s bulkhead and attach to the
PEX 8648 RDK adapter board, which plugs into one of the PC’s PCI Express slots, allowing the computer lid to
be closed.
The PEX 8648 RDK adapter board has a x16 male edge connector, to support Port 0 as a x16 Port. If the adapter
board is to be plugged into a smaller slot, a small Catalyst-style adapter must be used, which raises the adapter
board by 18 mm (0.7 inches). This makes the upper-most mini-SAS connector inaccessible, which is acceptable,
because this connector carries Lanes 12 through 15, which would not be used. Also, there is sufficient clearance
for the computer lid to close. Each Station has four possible Port configurations – x4x4x4x4, x16, x8x8, and
x8x4x4. The lowest four Lanes of Station 0 (Lanes 0 through 3) route directly to the lowest four Lanes of the SAS
connectors, the lowest four Lanes of Station 1 (Lanes 16 through 19) route directly to the lowest four Lanes of
Slot 4, and the lowest four Lanes of Station 2 (Lanes 32 through 35) route directly to the lowest four Lanes of
Slot 8. The remaining 12 Lanes of each Station route to a Configuration module. These modules map the Lanes
to the remaining mini-SAS and/or PCI Express connectors, as needed, to obtain the desired Port configuration.
Table 1 describes how to set up the various Port configuration options for each Station.
Note: The possibilities for Station 0 are more complex, because it houses the upstream Port and NT Port.
The Configuration modules consist of a 10 x 40 ball board-to-board, high-speed connector, with one-half of the
connectors mounted on the PEX 8648 RDK base board, and its mate mounted on a small 2-layer PCB that
performs the re-mapping. There are no other components. There are four different Configuration modules, one for
each possible Station configuration. Each module’s functionality is clearly labeled, and a 3-pin interface on each
module communicates its function to the CPLD glue logic.
The PCI Express Lanes for Station 1 and Station 2, from the PEX 8648 switch to the Configuration modules, have
soft touch midbus probe headers, for monitoring PCI Express traffic. Refer to the Agilent Soft Touch Midbus
Probe User’s Guide, for further details regarding the headers.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 6
Table 1. PEX 8648 RDK Base Board Port Configurations
Station 0
Port Configuration
Configuration
Module Installed
(P1)
SW2[2 – 1]
Setting Connectors Used SW1[6] Setting Refer to
x4 UP
x4x4x4 DOWN x4x4x4x4 LL (IP1), J1, J2, J3 H Figure 4
x16 UP x16 LH (IP1, IP2, IP3, IP4) H Figure 5
x8 UP
x8 DOWN
(Factory Default) x8x8 HL (IP1, IP2), J2 H Figure 6
x8 UP
x4x4 DOWN x8x4x4 HH (IP1, IP2), J2, J3 H Figure 7
x8 UP
x8 NT x16 HL (IP1, IP2), IP3, IP4 L Figure 8
x4 UP
x4 NT
x4x4 DOWN x8x4x4 LL (IP1), IP2, J2, J3 L Figure 9
Station 1
Port Configuration
Configuration
Module Installed
(P2)
SW2[4 – 3]
Setting Connectors Used – Refer to
x4x4x4x4 DOWN x4x4x4x4 LL J4, J5, J6, J7 Figure 10
x16 DOWN x16 LH J4 Figure 11
x8x8 DOWN
(Factory Default) x8x8 HL J4, J6 Figure 12
x8x4x4 DOWN x8x4x4 HH J4, J6, J7 Figure 13
Station 2
Port Configuration
Configuration
Module Installed
(P3)
SW2[6 – 5]
Setting Connectors Used – –
x4x4x4x4 DOWN x4x4x4x4 LL J8, J9, J10, J11
x16 DOWN x16 LH J8
x8x8 DOWN x8x8 HL J8, J10
x8x4x4 DOWN
(Factory Default) x8x4x4 HH J8, J10, J11
Note: In Table 1, parenthesis around the IP components are used to indicate the connectors that comprise the
upstream Port.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 7
Figure 4 through Figure 13 illustrate the hardwire routing arrangement for each configuration. The routing for
Station 2 is the same as for Station 1, except that it uses J8 through J11 and Lanes 32 through 47 of the
PEX 8648 switch.
PEX8648
27 x 27
16
31
015
32
47
Configuration Module
x4x4x4x4
Figure 4. Station 0, x4 UP and x4x4x4 DOWN
PEX8648
27 x 27
16
31
015
32
47
Configuration Module
x16
Figure 5. Station 0, x16 UP

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 8
PEX8648
27 x 27
16
31
015
32
47
Configuration Module
x8x8
Figure 6. Station 0, x8 UP and x8 DOWN (Factory Default)
PEX8648
27 x 27
16
31
015
32
47
Configuration Module
x8x4x4
Figure 7. Station 0, x8 UP and x4x4 DOWN

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 9
SAS
SAS
SAS
SAS Lanes 0-3
Lanes 4-7
Lanes 8-11
Lanes 12-15
Host
Motherboard
Adapter
PEX8648
27 x 27
16
31
015
32
47
IP1
IP2
IP3
IP4
P1
Lanes 0-3
Lanes4-7
Lanes 8-11
Lanes 12-15
Configuration Module
x16
J1
J3
J2 SAS
SAS
SAS
SAS Lanes 0-3
Lanes 4-7
Lanes 8-11
Lanes 12-15
NT
Motherboard
Adapter
Note: Station 0 must be configured
as x8x8, but the Configuration
Module used must be x16.
SAS
Lanes 4-7
SAS
Lanes 8-11
SAS
Lanes 12-15
SAS
Lanes 0-3
Figure 8. Station 0, x8 UP and x8 NT
SAS
SAS
SAS
SAS Lanes 0-3
Lanes 4-7
Lanes 8-11
Lanes 12-15
Host
Motherboard
Adapter
IP1
IP2
IP3
IP4
P1
Lanes 0-3
Lanes4-7
Lanes 8-11
Lanes 12-15
J1
J3
J2 SAS
SAS
SAS
SAS Lanes 0-3
Lanes 4-7
Lanes 8-11
Lanes 12-15
NT
Motherboard
Adapter
Note: Station 0 must be configured
as x4x4x4x4, but the Configuration
Module used must be x8x4x4.
SAS
Lanes 4-7
SAS
Lanes 8-11
SAS
Lanes 12-15
SAS
Lanes 0-3
Figure 9. Station 0, x4 UP, x4 NT, and x4x4 DOWN

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 10
PEX8648
27 x 27
16
31
015
32
47
P2
J7
J6
J5
J4
Configuration Module
x4x4x4x4
Figure 10. Station 1, x4x4x4x4 DOWN
PEX8648
27 x 27
16
31
015
32
47
P2
J7
J6
J5
J4
Configuration Module
x16
Figure 11. Station 1, x16 DOWN

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 11
PEX8648
27 x 27
16
31
015
32
47
P2
J7
J6
J5
J4
Configuration Module
x8x8
Figure 12. Station 1, x8x8 DOWN (Factory Default)
PEX8648
27 x 27
16
31
015
32
47
P2
J7
J6
J5
J4
Configuration Module
x8x4x4
Figure 13. Station 1, x8x4x4 DOWN

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 12
3.2 Non-Transparent Operation
Only the Station 0 Ports – Ports 0, 1, 2, and 3 – support NT mode. By default, the NT Port is assigned to Port 1,
by way of DIP switch SW1. To use the NT function, however, DIP switch SW1 must be used to Set the PEX 8648
switch’s Strapping balls so that the switch is in NT mode. Mini-SAS connectors are used to connect to the Host on
the NT Port, by way of cables.
For further details regarding the various hardware configurations for NT mode, refer to Section 3.1, “PCI Express
Port Configuration.”
For further details regarding DIP switch SW1, refer to Table 3, “PEX 8648 RDK Base Board Hardware Strapping
DIP Switches – SW1, SW11, SW4, SW5, SW9, SW6, SW2, and SW10.”
For details regarding the PEX_NT_RESET# sideband signal, refer to Section 3.12.3, “PEX_NT_RESET#
(TPV49).”
3.3 PCI Express Hot-Plug Circuitry
The PEX 8648 switch supports Hot-Plug on three downstream Ports, by way of dedicated 10-signal Parallel Hot-
Plug interfaces. In addition, a serial I2C interface, in conjunction with an external I/O Expander IC, can be used to
support Hot-Plug on any Port. The PEX 8648 RDK base board has external Hot-Plug circuitry that supports
Parallel Hot-Plug to Slot 5, and Serial Hot-Plug to Slot 8.
The PEX 8648 RDK base board supports Parallel Hot-Plug, only on Port 5 of Station 1, routed to Slot 5, and only
when Station 1 is configured as x4x4x4x4. To support Parallel Hot-Plug, Slot 5 has a dual-voltage Hot-Plug
Controller chip associated with it (U15), which controls power to this slot. If Port 5 is the upstream Port, the
Strapping signals that Set the upstream Port are used to bypass the Hot-Plug circuitry for Slot 5.
Note: Other Port configurations that include Port 5 – x8x8 or x8x4x4 – do not support Hot-Plug. In this case,
Port 5 routes to Slot 6, which does not include Hot-Plug circuitry.
The PEX 8648 RDK base board supports Serial Hot-Plug on Port 8 of Station 2 (U18). A serial I2C interface, with
an external I/O Expander IC (U17), supports Serial Hot-Plug functionality on this slot. Because Port 8 is the
primary slot on Station 2, Port configuration of Station 2 does not matter. Port 8 is always Hot-Plug-capable.
Figure 14 illustrates the PEX 8648 RDK base board PCI Express Hot-Plug circuitry.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 13
SLOT8-HP SLOT5-HP
RefClk
1:12
Fanout
Configuration Module
Bracket
SATA
MICTOR MICTOR
U11
CABLE SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 SLOT 9 SLOT 10 SLOT 11
PORT
WIDTH
PORT
NUMBER
UP PORT
NT PORT
PORT STATUS
J9
J10 J11
J6 J7 J8 J4 J5
IP1 IP2 IP3 IP4
P4
P5
P6
P7 P8
P9
P10 P11
J12 J13
J14
JP11
JP13
JP12
P2 Configuration Module
P3
SLOT8-HP SLOT5-HP
RESET
PERST
ATN LED
PWR LED
ATN BUTTON
PORT 5 –
PARALLEL HOT PLUG PORT 8 – SERIAL HOT PLUG
SAS
Lanes 4-7
SAS
Lanes 8-11
SAS
Lanes 12-15
SAS
Lanes 0-3
PEX8648
27 x 27
16
31
015
32
47
J1 J2 J3
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN OPEN OPEN
Configuration Module
P1
Figure 14. PEX 8648 RDK Base Board PCI Express Hot-Plug Circuitry

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 14
3.4 Reference Clock Circuitry
The differential PCI Express RefClk is brought onto the PEX 8648 RDK base board from the Host PC, by way of
the PEX 8648 RDK adapter board and a Serial ATA cable connection. It is used to drive a dual-level set of 1:4
Fan-Out buffers (U3, U4, U5, and U7) to provide a 1:12 Clock Fan-Out buffer. One of these clocks connects to the
PEX 8648 switch and is always enabled. The other 11 clocks connect to the 11 PCI Express slot connectors.
Except for Slot 5 and Slot 8, these RefClks are always enabled. Slot 5 is the downstream connection selected to
demonstrate Hot-Plug capability using the Parallel Hot-Plug interface. Therefore, by default, Slot 5 is enabled by
the PEX 8648 switch’s Parallel Hot-Plug Controller for Port 5. Slot 8 is the downstream connection selected to
demonstrate Hot-Plug capability using the Serial Hot-Plug Controller and an external I/O Expander IC. Figure 15
illustrates the PEX 8648 RDK base board’s Reference Clock circuitry.

PEX 8648-AA RDK Hardware Reference Manual, Version 1.2
Copyright © 2010 by PLX Technology, Inc. All rights reserved 15
PEX8648
27 x 27
16
31
015
32
47
Figure 15. PEX 8648 RDK Base Board Reference Clock Circuitry