Texas Instruments SimpleLink MSP432E4 Product manual

MSP432E4 SimpleLink™ Microcontrollers
Technical Reference Manual
Literature Number: SLAU723A
October 2017–Revised October 2018

2SLAU723A–October 2017–Revised October 2018
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Copyright © 2017–2018, Texas Instruments Incorporated
Contents
Contents
Preface....................................................................................................................................... 77
1 Cortex®-M4F Processor....................................................................................................... 79
1.1 Introduction.................................................................................................................. 80
1.2 Block Diagram .............................................................................................................. 81
1.3 Overview..................................................................................................................... 82
1.3.1 System-Level Interface ........................................................................................... 82
1.3.2 Integrated Configurable Debug.................................................................................. 82
1.3.3 Trace Port Interface Unit (TPIU) ................................................................................ 82
1.3.4 Cortex-M4F System Component Details....................................................................... 83
1.4 Programming Model ....................................................................................................... 83
1.4.1 Processor Mode and Privilege Levels for Software Execution.............................................. 83
1.4.2 Stacks............................................................................................................... 84
1.4.3 Exceptions and Interrupts........................................................................................ 97
1.4.4 Data Types......................................................................................................... 97
1.5 Memory Model.............................................................................................................. 97
1.5.1 Memory Regions, Types, and Attributes...................................................................... 100
1.5.2 Memory System Ordering of Memory Accesses ............................................................ 100
1.5.3 Behavior of Memory Accesses................................................................................. 100
1.5.4 Software Ordering of Memory Accesses ..................................................................... 101
1.5.5 Bit-Banding ....................................................................................................... 102
1.5.6 Data Storage ..................................................................................................... 104
1.5.7 Synchronization Primitives...................................................................................... 104
1.6 Exception Model .......................................................................................................... 105
1.6.1 Exception States................................................................................................. 106
1.6.2 Exception Types ................................................................................................. 106
1.6.3 Exception Handlers.............................................................................................. 108
1.6.4 Vector Table...................................................................................................... 108
1.6.5 Exception Priorities .............................................................................................. 109
1.6.6 Interrupt Priority Grouping ...................................................................................... 110
1.6.7 Exception Entry and Return .................................................................................... 110
1.7 Fault Handling............................................................................................................. 113
1.7.1 Fault Types ....................................................................................................... 113
1.7.2 Fault Escalation and Hard Faults.............................................................................. 113
1.7.3 Fault Status Registers and Fault Address Registers........................................................ 114
1.7.4 Lockup............................................................................................................. 114
1.8 Power Management...................................................................................................... 114
1.8.1 Entering Sleep Modes........................................................................................... 115
1.8.2 Wake Up From Sleep Mode.................................................................................... 115
1.9 Instruction Set Summary................................................................................................. 115
2 Cortex-M4 Peripherals....................................................................................................... 121
2.1 Introduction ................................................................................................................ 122
2.2 Functional Description.................................................................................................... 122
2.2.1 System Timer (SysTick)......................................................................................... 122
2.2.2 Nested Vectored Interrupt Controller (NVIC)................................................................. 123
2.2.3 System Control Block (SCB) ................................................................................... 124

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2.2.4 Memory Protection Unit (MPU) ................................................................................ 124
2.2.5 Floating-Point Unit (FPU)....................................................................................... 128
2.3 SysTick Registers......................................................................................................... 133
2.3.1 STCTRL Register (Offset = 0x10) [reset = 0x0] ............................................................. 134
2.3.2 STRELOAD Register (Offset = 0x14) [reset = 0x0] ......................................................... 135
2.3.3 STCURRENT Register (Offset = 0x18) [reset = 0x0]....................................................... 136
2.4 NVIC Registers............................................................................................................ 137
2.4.1 EN0 to EN3 Registers........................................................................................... 139
2.4.2 DIS0 to DIS3 Registers ......................................................................................... 140
2.4.3 PEND0 to PEND 3 Registers .................................................................................. 141
2.4.4 UNPEND0 to UNPEND3 Registers ........................................................................... 142
2.4.5 ACTIVE0 to ACTIVE3 Registers............................................................................... 143
2.4.6 PRI0 to PRI28 Registers........................................................................................ 144
2.4.7 SWTRIG Register (Offset = 0xF00) [reset = 0x0] ........................................................... 146
2.5 SCB Registers............................................................................................................. 147
2.5.1 ACTLR Register (Offset = 0x8) [reset = 0x0] ................................................................ 148
2.5.2 CPUID Register (Offset = 0xD00) [reset = 0x410FC241] .................................................. 149
2.5.3 INTCTRL Register (Offset = 0xD04) [reset = 0x0] .......................................................... 150
2.5.4 VTABLE Register (Offset = 0xD08) [reset = 0x0] ........................................................... 152
2.5.5 APINT Register (Offset = 0xD0C) [reset = 0xFA050000] .................................................. 153
2.5.6 SYSCTRL Register (Offset = 0xD10) [reset = 0x0] ......................................................... 155
2.5.7 CFGCTRL Register (Offset = 0xD14) [reset = 0x200]...................................................... 156
2.5.8 SYSPRI1 Register (Offset = 0xD18) [reset = 0x0] .......................................................... 157
2.5.9 SYSPRI2 Register (Offset = 0xD1C) [reset = 0x0].......................................................... 158
2.5.10 SYSPRI3 Register (Offset = 0xD20) [reset = 0x0] ......................................................... 159
2.5.11 SYSHNDCTRL Register (Offset = 0xD24) [reset = 0x0] .................................................. 160
2.5.12 FAULTSTAT Register (Offset = 0xD28) [reset = 0x0] ..................................................... 162
2.5.13 HFAULTSTAT Register (Offset = 0xD2C) [reset = 0x0]................................................... 165
2.5.14 MMADDR Register (Offset = 0xD34) [reset = X] ........................................................... 166
2.5.15 FAULTADDR Register (Offset = 0xD38) [reset = X]....................................................... 167
2.6 MPU Registers............................................................................................................ 168
2.6.1 MPUTYPE Register (Offset = 0xD90) [reset = 0x800]...................................................... 169
2.6.2 MPUCTRL Register (Offset = 0xD94) [reset = 0x0]......................................................... 170
2.6.3 MPUNUMBER Register (Offset = 0xD98) [reset = 0x0].................................................... 172
2.6.4 MPUBASEn Registers .......................................................................................... 173
2.6.5 MPUATTRn Registers........................................................................................... 175
2.7 FPU Registers............................................................................................................. 177
2.7.1 CPAC Register (Offset = 0xD88) [reset = 0x0] .............................................................. 178
2.7.2 FPCC Register (Offset = 0xF34) [reset = 0xC0000000].................................................... 179
2.7.3 FPCA Register (Offset = 0xF38) [reset = X] ................................................................. 181
2.7.4 FPDSC Register (Offset = 0xF3C) [reset = X]............................................................... 182
3 JTAG Interface ................................................................................................................. 183
3.1 Introduction ................................................................................................................ 184
3.2 Block Diagram............................................................................................................. 184
3.3 Functional Description.................................................................................................... 185
3.3.1 JTAG Interface Pins............................................................................................. 185
3.3.2 JTAG TAP Controller............................................................................................ 187
3.3.3 Shift Registers.................................................................................................... 187
3.3.4 Operational Considerations..................................................................................... 187
3.4 Initialization and Configuration.......................................................................................... 190
3.5 Register Descriptions..................................................................................................... 190
3.5.1 Instruction Register (IR)......................................................................................... 190
3.5.2 Data Registers ................................................................................................... 192

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4 System Control................................................................................................................. 194
4.1 Functional Description.................................................................................................... 195
4.1.1 Device Identification............................................................................................. 195
4.1.2 Reset Control..................................................................................................... 195
4.1.3 Nonmaskable Interrupt.......................................................................................... 201
4.1.4 Power Control .................................................................................................... 202
4.1.5 Clock Control..................................................................................................... 203
4.1.6 System Control................................................................................................... 210
4.2 System Control Registers................................................................................................ 217
4.2.1 DID0 Register (Offset = 0x0) [reset = X]...................................................................... 222
4.2.2 DID1 Register (Offset = 0x4) [reset = X]...................................................................... 224
4.2.3 PTBOCTL Register (Offset = 0x38) [reset = 0x3] ........................................................... 226
4.2.4 RIS Register (Offset = 0x50) [reset = 0x0] ................................................................... 227
4.2.5 IMC Register (Offset = 0x54) [reset = 0x0]................................................................... 229
4.2.6 MISC Register (Offset = 0x58) [reset = 0x0]................................................................. 230
4.2.7 RESC Register (Offset = 0x5C) [reset = X] .................................................................. 232
4.2.8 PWRTC Register (Offset = 0x60) [reset = 0x0].............................................................. 234
4.2.9 NMIC Register (Offset = 0x64) [reset = 0x0]................................................................. 235
4.2.10 MOSCCTL Register (Offset = 0x7C) [reset = 0xC]......................................................... 237
4.2.11 RSCLKCFG Register (Offset = 0xB0) [reset = 0x0]........................................................ 239
4.2.12 MEMTIM0 Register (Offset = 0xC0) [reset = 0x00200030] ............................................... 241
4.2.13 ALTCLKCFG Register (Offset = 0x138) [reset = 0x0] ..................................................... 244
4.2.14 DSCLKCFG Register (Offset = 0x144) [reset = 0x0] ...................................................... 245
4.2.15 DIVSCLK Register (Offset = 0x148) [reset = 0x0].......................................................... 247
4.2.16 SYSPROP Register (Offset = 0x14C) [reset = 0x00031F31]............................................. 248
4.2.17 PIOSCCAL Register (Offset = 0x150) [reset = 0x0] ....................................................... 250
4.2.18 PIOSCSTAT Register (Offset = 0x154) [reset = 0x00400040] ........................................... 251
4.2.19 PLLFREQ0 Register (Offset = 0x160) [reset = 0x0] ....................................................... 252
4.2.20 PLLFREQ1 Register (Offset = 0x164) [reset = 0x0] ....................................................... 253
4.2.21 PLLSTAT Register (Offset = 0x168) [reset = 0x0] ......................................................... 254
4.2.22 SLPPWRCFG Register (Offset = 0x188) [reset = 0x0].................................................... 255
4.2.23 DSLPPWRCFG Register (Offset = 0x18C) [reset = 0x0].................................................. 256
4.2.24 NVMSTAT Register (Offset = 0x1A0) [reset = 0x1]........................................................ 258
4.2.25 LDOSPCTL Register (Offset = 0x1B4) [reset = 0x18] ..................................................... 259
4.2.26 LDOSPCAL Register (Offset = 0x1B8) [reset = 0x1818].................................................. 260
4.2.27 LDODPCTL Register (Offset = 0x1BC) [reset = 0x12]..................................................... 261
4.2.28 LDODPCAL Register (Offset = 0x1C0) [reset = 0x1212].................................................. 262
4.2.29 SDPMST Register (Offset = 0x1CC) [reset = 0x0]......................................................... 263
4.2.30 RESBEHAVCTL Register (Offset = 0x1D8) [reset = 0x00FFFFFF]...................................... 265
4.2.31 HSSR Register (Offset = 0x1F4) [reset = 0x0] ............................................................. 266
4.2.32 USBPDS Register (Offset = 0x280) [reset = 0x3F] ........................................................ 267
4.2.33 USBMPC Register (Offset = 0x284) [reset = 0x3].......................................................... 268
4.2.34 EMACPDS Register (Offset = 0x288) [reset = 0x3F] ...................................................... 269
4.2.35 EMACMPC Register (Offset = 0x28C) [reset = 0x3]....................................................... 270
4.2.36 LCDPDS Register (Offset = 0x290) [reset = 0x3F]......................................................... 271
4.2.37 LCDMPC Register (Offset = 0x294) [reset = 0x3].......................................................... 272
4.2.38 CAN0PDS Register (Offset = 0x298) [reset = 0x3F]....................................................... 273
4.2.39 CAN0MPC Register (Offset = 0x29C) [reset = 0x3]........................................................ 274
4.2.40 CAN1PDS Register (Offset = 0x2A0) [reset = 0x3F] ...................................................... 275
4.2.41 CAN1MPC Register (Offset = 0x2A4) [reset = 0x3]........................................................ 276
4.2.42 PPWD Register (Offset = 0x300) [reset = 0x3]............................................................. 277
4.2.43 PPTIMER Register (Offset = 0x304) [reset = 0xFF] ....................................................... 278
4.2.44 PPGPIO Register (Offset = 0x308) [reset = 0x3FFFF] .................................................... 279

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4.2.45 PPDMA Register (Offset = 0x30C) [reset = 0x1] ........................................................... 281
4.2.46 PPEPI Register (Offset = 0x310) [reset = 0x1] ............................................................. 282
4.2.47 PPHIB Register (Offset = 0x314) [reset = 0x01]............................................................ 283
4.2.48 PPUART Register (Offset = 0x318) [reset = 0xFF] ........................................................ 284
4.2.49 PPSSI Register (Offset = 0x31C) [reset = 0xF]............................................................. 285
4.2.50 PPI2C Register (Offset = 0x320) [reset = 0x3FF].......................................................... 286
4.2.51 PPUSB Register (Offset = 0x328) [reset = 0x1]............................................................ 287
4.2.52 PPEPHY Register (Offset = 0x330) [reset = 0x1] .......................................................... 288
4.2.53 PPCAN Register (Offset = 0x334) [reset = 0x3]............................................................ 289
4.2.54 PPADC Register (Offset = 0x338) [reset = 0x3]............................................................ 290
4.2.55 PPACMP Register (Offset = 0x33C) [reset = 0x1] ......................................................... 291
4.2.56 PPPWM Register (Offset = 0x340) [reset = 0x1]........................................................... 292
4.2.57 PPQEI Register (Offset = 0x344) [reset = 0x1]............................................................. 293
4.2.58 PPEEPROM Register (Offset = 0x358) [reset = 0x01] .................................................... 294
4.2.59 PPCCM Register (Offset = 0x374) [reset = 0x01].......................................................... 295
4.2.60 PPLCD Register (Offset = 0x390) [reset = 0x01]........................................................... 296
4.2.61 PPOWIRE Register (Offset = 0x398) [reset = 0x01]....................................................... 297
4.2.62 PPEMAC Register (Offset = 0x39C) [reset = 0x01]........................................................ 298
4.2.63 PPPRB Register (Offset = 0x3A0) [reset = 0x00] .......................................................... 299
4.2.64 SRWD Register (Offset = 0x500) [reset = 0x00] ........................................................... 300
4.2.65 SRTIMER Register (Offset = 0x504) [reset = 0x00]........................................................ 301
4.2.66 SRGPIO Register (Offset = 0x508) [reset = 0x00] ......................................................... 302
4.2.67 SRDMA Register (Offset = 0x50C) [reset = 0x00] ......................................................... 304
4.2.68 SREPI Register (Offset = 0x510) [reset = 0x00]............................................................ 305
4.2.69 SRHIB Register (Offset = 0x514) [reset = 0x00] ........................................................... 306
4.2.70 SRUART Register (Offset = 0x518) [reset = 0x00]......................................................... 307
4.2.71 SRSSI Register (Offset = 0x51C) [reset = 0x0]............................................................. 309
4.2.72 SRI2C Register (Offset = 0x520) [reset = 0x0] ............................................................. 310
4.2.73 SRUSB Register (Offset = 0x528) [reset = 0x0]............................................................ 312
4.2.74 SREPHY Register (Offset = 0x530) [reset = 0x0].......................................................... 313
4.2.75 SRCAN Register (Offset = 0x534) [reset = 0x0]............................................................ 314
4.2.76 SRADC Register (Offset = 0x538) [reset = 0x0]............................................................ 315
4.2.77 SRACMP Register (Offset = 0x53C) [reset = 0x0] ......................................................... 316
4.2.78 SRPWM Register (Offset = 0x540) [reset = 0x0]........................................................... 317
4.2.79 SRQEI Register (Offset = 0x544) [reset = 0x0]............................................................. 318
4.2.80 SREEPROM Register (Offset = 0x558) [reset = 0x0]...................................................... 319
4.2.81 SRCCM Register (Offset = 0x574) [reset = 0x0] ........................................................... 320
4.2.82 SRLCD Register (Offset = 0x590) [reset = 0x0]............................................................ 321
4.2.83 SROWIRE Register (Offset = 0x598) [reset = 0x0] ........................................................ 322
4.2.84 SREMAC Register (Offset = 0x59C) [reset = 0x0] ......................................................... 323
4.2.85 RCGCWD Register (Offset = 0x600) [reset = 0x0]......................................................... 324
4.2.86 RCGCTIMER Register (Offset = 0x604) [reset = 0x00] ................................................... 325
4.2.87 RCGCGPIO Register (Offset = 0x608) [reset = 0x00]..................................................... 326
4.2.88 RCGCDMA Register (Offset = 0x60C) [reset = 0x0]....................................................... 328
4.2.89 RCGCEPI Register (Offset = 0x610) [reset = 0x0]......................................................... 329
4.2.90 RCGCHIB Register (Offset = 0x614) [reset = 0x1]......................................................... 330
4.2.91 RCGCUART Register (Offset = 0x618) [reset = 0x00] .................................................... 331
4.2.92 RCGCSSI Register (Offset = 0x61C) [reset = 0x0] ........................................................ 332
4.2.93 RCGCI2C Register (Offset = 0x620) [reset = 0x00]........................................................ 333
4.2.94 RCGCUSB Register (Offset = 0x628) [reset = 0x0]........................................................ 335
4.2.95 RCGCEPHY Register (Offset = 0x630) [reset = 0x0]...................................................... 336
4.2.96 RCGCCAN Register (Offset = 0x634) [reset = 0x0]........................................................ 337
4.2.97 RCGCADC Register (Offset = 0x638) [reset = 0x0]........................................................ 338

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4.2.98 RCGCACMP Register (Offset = 0x63C) [reset = 0x0]..................................................... 339
4.2.99 RCGCPWM Register (Offset = 0x640) [reset = 0x0]....................................................... 340
4.2.100 RCGCQEI Register (Offset = 0x644) [reset = 0x0]....................................................... 341
4.2.101 RCGCEEPROM Register (Offset = 0x658) [reset = 0x0]................................................ 342
4.2.102 RCGCCCM Register (Offset = 0x674) [reset = 0x0]...................................................... 343
4.2.103 RCGCLCD Register (Offset = 0x690) [reset = 0x0] ...................................................... 344
4.2.104 RCGCOWIRE Register (Offset = 0x698) [reset = 0x0]................................................... 345
4.2.105 RCGCEMAC Register (Offset = 0x69C) [reset = 0x0] ................................................... 346
4.2.106 SCGCWD Register (Offset = 0x700) [reset = 0x0] ....................................................... 347
4.2.107 SCGCTIMER Register (Offset = 0x704) [reset = 0x00].................................................. 348
4.2.108 SCGCGPIO Register (Offset = 0x708) [reset = 0x00].................................................... 350
4.2.109 SCGCDMA Register (Offset = 0x70C) [reset = 0x0] ..................................................... 352
4.2.110 SCGCEPI Register (Offset = 0x710) [reset = 0x0] ....................................................... 353
4.2.111 SCGCHIB Register (Offset = 0x714) [reset = 0x1] ....................................................... 354
4.2.112 SCGCUART Register (Offset = 0x718) [reset = 0x00]................................................... 355
4.2.113 SCGCSSI Register (Offset = 0x71C) [reset = 0x0]....................................................... 356
4.2.114 SCGCI2C Register (Offset = 0x720) [reset = 0x00] ...................................................... 357
4.2.115 SCGCUSB Register (Offset = 0x728) [reset = 0x0] ...................................................... 359
4.2.116 SCGCEPHY Register (Offset = 0x730) [reset = 0x0]..................................................... 360
4.2.117 SCGCCAN Register (Offset = 0x734) [reset = 0x0] ...................................................... 361
4.2.118 SCGCADC Register (Offset = 0x738) [reset = 0x0] ...................................................... 362
4.2.119 SCGCACMP Register (Offset = 0x73C) [reset = 0x0].................................................... 363
4.2.120 SCGCPWM Register (Offset = 0x740) [reset = 0x0] ..................................................... 364
4.2.121 SCGCQEI Register (Offset = 0x744) [reset = 0x0] ....................................................... 365
4.2.122 SCGCEEPROM Register (Offset = 0x758) [reset = 0x0] ................................................ 366
4.2.123 SCGCCCM Register (Offset = 0x774) [reset = 0x0]...................................................... 367
4.2.124 SCGCLCD Register (Offset = 0x790) [reset = 0x0] ...................................................... 368
4.2.125 SCGCOWIRE Register (Offset = 0x798) [reset = 0x0]................................................... 369
4.2.126 SCGCEMAC Register (Offset = 0x79C) [reset = 0x0].................................................... 370
4.2.127 DCGCWD Register (Offset = 0x800) [reset = 0x0] ....................................................... 371
4.2.128 DCGCTIMER Register (Offset = 0x804) [reset = 0x00].................................................. 372
4.2.129 DCGCGPIO Register (Offset = 0x808) [reset = 0x00] ................................................... 374
4.2.130 DCGCDMA Register (Offset = 0x80C) [reset = 0x0] ..................................................... 376
4.2.131 DCGCEPI Register (Offset = 0x810) [reset = 0x0] ....................................................... 377
4.2.132 DCGCHIB Register (Offset = 0x814) [reset = 0x1] ....................................................... 378
4.2.133 DCGCUART Register (Offset = 0x818) [reset = 0x00]................................................... 379
4.2.134 DCGCSSI Register (Offset = 0x81C) [reset = 0x0]....................................................... 381
4.2.135 DCGCI2C Register (Offset = 0x820) [reset = 0x00]...................................................... 382
4.2.136 DCGCUSB Register (Offset = 0x828) [reset = 0x0] ...................................................... 384
4.2.137 DCGCEPHY Register (Offset = 0x830) [reset = 0x0] .................................................... 385
4.2.138 DCGCCAN Register (Offset = 0x834) [reset = 0x0]...................................................... 386
4.2.139 DCGCADC Register (Offset = 0x838) [reset = 0x0]...................................................... 387
4.2.140 DCGCACMP Register (Offset = 0x83C) [reset = 0x0] ................................................... 388
4.2.141 DCGCPWM Register (Offset = 0x840) [reset = 0x0] ..................................................... 389
4.2.142 DCGCQEI Register (Offset = 0x844) [reset = 0x0]....................................................... 390
4.2.143 DCGCEEPROM Register (Offset = 0x858) [reset = 0x0]................................................ 391
4.2.144 DCGCCCM Register (Offset = 0x874) [reset = 0x0]...................................................... 392
4.2.145 DCGCLCD Register (Offset = 0x890) [reset = 0x0] ...................................................... 393
4.2.146 DCGCOWIRE Register (Offset = 0x898) [reset = 0x0]................................................... 394
4.2.147 DCGCEMAC Register (Offset = 0x89C) [reset = 0x0] ................................................... 395
4.2.148 PCWD Register (Offset = 0x900) [reset = 0x3] ........................................................... 396
4.2.149 PCTIMER Register (Offset = 0x904) [reset = 0xFF]...................................................... 398
4.2.150 PCGPIO Register (Offset = 0x908) [reset = 0x3FFFF]................................................... 401

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4.2.151 PCDMA Register (Offset = 0x90C) [reset = 0x1] ......................................................... 405
4.2.152 PCEPI Register (Offset = 0x910) [reset = 0x1]............................................................ 407
4.2.153 PCHIB Register (Offset = 0x914) [reset = 0x1] ........................................................... 409
4.2.154 PCUART Register (Offset = 0x918) [reset = 0xFF]....................................................... 411
4.2.155 PCSSI Register (Offset = 0x91C) [reset = 0xF]........................................................... 414
4.2.156 PCI2C Register (Offset = 0x920) [reset = 0x3FF] ........................................................ 416
4.2.157 PCUSB Register (Offset = 0x928) [reset = 0x1] .......................................................... 419
4.2.158 PCEPHY Register (Offset = 0x930) [reset = 0x0]......................................................... 420
4.2.159 PCCAN Register (Offset = 0x934) [reset = 0x3] .......................................................... 422
4.2.160 PCADC Register (Offset = 0x938) [reset = 0x3] .......................................................... 424
4.2.161 PCACMP Register (Offset = 0x93C) [reset = 0x1]........................................................ 426
4.2.162 PCPWM Register (Offset = 0x940) [reset = 0x1] ......................................................... 428
4.2.163 PCQEI Register (Offset = 0x944) [reset = 0x1] ........................................................... 430
4.2.164 PCEEPROM Register (Offset = 0x958) [reset = 0x1] .................................................... 432
4.2.165 PCCCM Register (Offset = 0x974) [reset = 0x1].......................................................... 434
4.2.166 PCLCD Register (Offset = 0x990) [reset = 0x1] .......................................................... 436
4.2.167 PCOWIRE Register (Offset = 0x998) [reset = 0x1]....................................................... 437
4.2.168 PCEMAC Register (Offset = 0x99C) [reset = 0x1]........................................................ 439
4.2.169 PRWD Register (Offset = 0xA00) [reset = 0x0] ........................................................... 440
4.2.170 PRTIMER Register (Offset = 0xA04) [reset = 0x00]...................................................... 441
4.2.171 PRGPIO Register (Offset = 0xA08) [reset = 0x00] ....................................................... 443
4.2.172 PRDMA Register (Offset = 0xA0C) [reset = 0x0] ......................................................... 445
4.2.173 PREPI Register (Offset = 0xA10) [reset = 0x0] ........................................................... 446
4.2.174 PRHIB Register (Offset = 0xA14) [reset = 0x1]........................................................... 447
4.2.175 PRUART Register (Offset = 0xA18) [reset = 0x00]....................................................... 448
4.2.176 PRSSI Register (Offset = 0xA1C) [reset = 0x0]........................................................... 450
4.2.177 PRI2C Register (Offset = 0xA20) [reset = 0x00].......................................................... 451
4.2.178 PRUSB Register (Offset = 0xA28) [reset = 0x0].......................................................... 453
4.2.179 PREPHY Register (Offset = 0xA30) [reset = 0x0] ........................................................ 454
4.2.180 PRCAN Register (Offset = 0xA34) [reset = 0x0].......................................................... 455
4.2.181 PRADC Register (Offset = 0xA38) [reset = 0x0].......................................................... 456
4.2.182 PRACMP Register (Offset = 0xA3C) [reset = 0x0] ....................................................... 457
4.2.183 PRPWM Register (Offset = 0xA40) [reset = 0x0]......................................................... 458
4.2.184 PRQEI Register (Offset = 0xA44) [reset = 0x0]........................................................... 459
4.2.185 PREEPROM Register (Offset = 0xA58) [reset = 0x0].................................................... 460
4.2.186 PRCCM Register (Offset = 0xA74) [reset = 0x0] ......................................................... 461
4.2.187 PRLCD Register (Offset = 0xA90) [reset = 0x0] .......................................................... 462
4.2.188 PROWIRE Register (Offset = 0xA98) [reset = 0x0] ...................................................... 463
4.2.189 PREMAC Register (Offset = 0xA9C) [reset = 0x0] ....................................................... 464
4.2.190 UNIQUEID0 to UNIQUEID3 Register (Offset = 0xF20 to 0xF2C) [reset = X]......................... 465
4.3 Cryptographic System Control (CCM) Registers ..................................................................... 466
4.3.1 CCMCGREQ Register (Offset = 0x204) [reset = 0x0] ...................................................... 467
5 Processor Support and Exception Module........................................................................... 468
5.1 Functional Description.................................................................................................... 469
5.2 System Exception Registers ............................................................................................ 470
5.2.1 SYSEXCRIS Register (Offset = 0x0) [reset = 0x0].......................................................... 471
5.2.2 SYSEXCIM Register (Offset = 0x4) [reset = 0x0] ........................................................... 472
5.2.3 SYSEXCMIS Register (Offset = 0x8) [reset = 0x0] ......................................................... 473
5.2.4 SYSEXCIC Register (Offset = 0xC) [reset = 0x0] ........................................................... 474
6 Hibernation Module........................................................................................................... 475
6.1 Introduction ................................................................................................................ 476
6.2 Block Diagram............................................................................................................. 477
6.3 Functional Description.................................................................................................... 477

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6.3.1 Register Access Timing......................................................................................... 478
6.3.2 Hibernation Clock Source....................................................................................... 478
6.3.3 System Implementation......................................................................................... 480
6.3.4 Battery Management ............................................................................................ 481
6.3.5 Real-Time Clock ................................................................................................. 482
6.3.6 Tamper............................................................................................................ 484
6.3.7 Battery-Backed Memory ........................................................................................ 488
6.3.8 Power Control Using HIB ...................................................................................... 488
6.3.9 Power Control Using VDD3ON Mode......................................................................... 488
6.3.10 Initiating Hibernate.............................................................................................. 488
6.3.11 Waking from Hibernate ........................................................................................ 488
6.3.12 Arbitrary Power Removal...................................................................................... 489
6.3.13 Interrupts and Status........................................................................................... 490
6.4 Initialization and Configuration.......................................................................................... 490
6.4.1 Initialization ....................................................................................................... 490
6.4.2 RTC Match Functionality (No Hibernation)................................................................... 491
6.4.3 RTC Match and Wake From Hibernation..................................................................... 491
6.4.4 External Wake From Hibernation.............................................................................. 491
6.4.5 RTC or External Wake From Hibernation .................................................................... 492
6.4.6 Tamper Initialization............................................................................................. 492
6.5 HIB Registers.............................................................................................................. 493
6.5.1 HIBRTCC Register (Offset = 0x0) [reset = 0x0] ............................................................. 495
6.5.2 HIBRTCM0 Register (Offset = 0x4) [reset = 0xFFFFFFFF]................................................ 496
6.5.3 HIBRTCLD Register (Offset = 0xC) [reset = 0x0] ........................................................... 497
6.5.4 HIBCTL Register (Offset = 0x10) [reset = 0x80002000].................................................... 498
6.5.5 HIBIM Register (Offset = 0x14) [reset = 0x0] ................................................................ 502
6.5.6 HIBRIS Register (Offset = 0x18) [reset = 0x0]............................................................... 504
6.5.7 HIBMIS Register (Offset = 0x1C) [reset = 0x0].............................................................. 506
6.5.8 HIBIC Register (Offset = 0x20) [reset = 0x0]................................................................. 508
6.5.9 HIBRTCT Register (Offset = 0x24) [reset = 0x7FFF] ....................................................... 510
6.5.10 HIBRTCSS Register (Offset = 0x28) [reset = 0x0]......................................................... 511
6.5.11 HIBIO Register (Offset = 0x2C) [reset = 0x80000000] .................................................... 512
6.5.12 HIBDATA Register (Offset = 0x030 to 0x06F) [reset = X]................................................. 513
6.5.13 HIBCALCTL Register (Offset = 0x300) [reset = 0x0] ...................................................... 514
6.5.14 HIBCAL0 Register (Offset = 0x310) [reset = 0x0].......................................................... 515
6.5.15 HIBCAL1 Register (Offset = 0x314) [reset = 0x0].......................................................... 516
6.5.16 HIBCALLD0 Register (Offset = 0x320) [reset = 0x0] ...................................................... 517
6.5.17 HIBCALLD1 Register (Offset = 0x324) [reset = 0x0] ...................................................... 518
6.5.18 HIBCALM0 Register (Offset = 0x330) [reset = 0x0]........................................................ 519
6.5.19 HIBCALM1 Register (Offset = 0x334) [reset = 0x0]........................................................ 520
6.5.20 HIBLOCK Register (Offset = 0x360) [reset = 0x0] ......................................................... 521
6.5.21 HIBTPCTL Register (Offset = 0x400) [reset = 0x0] ........................................................ 522
6.5.22 HIBTPSTAT Register (Offset = 0x404) [reset = 0x0] ...................................................... 524
6.5.23 HIBTPIO Register (Offset = 0x410) [reset = 0x0] .......................................................... 525
6.5.24 HIBTPLOG0, HIBTPLOG2, HIBTPLOG4, HIBTPLOG6 Registers (Offset = 0x4E0 to 0x4F8)
[reset = 0x0] ...................................................................................................... 527
6.5.25 HIBTPLOG1, HIBTPLOG3, HIBTPLOG5, HIBTPLOG7 Registers (Offset = 0x4E4 to 0x4FC)
[reset = 0x0] ...................................................................................................... 528
6.5.26 HIBPP Register (Offset = 0xFC0) [reset = 0x2] ............................................................ 529
6.5.27 HIBCC Register (Offset = 0xFC8) [reset = 0x0] ............................................................ 530
7 Internal Memory................................................................................................................ 531
7.1 Block Diagram............................................................................................................. 532
7.2 Functional Description.................................................................................................... 532
7.2.1 SRAM ............................................................................................................. 533

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7.2.2 ROM............................................................................................................... 533
7.2.3 Flash Memory .................................................................................................... 535
7.2.4 EEPROM.......................................................................................................... 544
7.2.5 Bus Matrix Memory Accesses.................................................................................. 549
7.3 Flash Registers ........................................................................................................... 550
7.3.1 FMA Register (Offset = 0x0) [reset = 0x0].................................................................... 551
7.3.2 FMD Register (Offset = 0x4) [reset = 0x0] ................................................................... 552
7.3.3 FMC Register (Offset = 0x8) [reset = 0x0] ................................................................... 553
7.3.4 FCRIS Register (Offset = 0xC) [reset = 0x0]................................................................. 555
7.3.5 FCIM Register (Offset = 0x10) [reset = 0x0] ................................................................. 557
7.3.6 FCMISC Register (Offset = 0x14) [reset = 0x0] ............................................................. 559
7.3.7 FMC2 Register (Offset = 0x20) [reset = 0x0] ................................................................ 561
7.3.8 FWBVAL Register (Offset = 0x30) [reset = 0x0]............................................................. 562
7.3.9 FLPEKEY Register (Offset = 0x3C) [reset = 0xFFFF]...................................................... 563
7.3.10 FWB0 to FWB31 Registers (Offset = 0x100 to 0x17C) [reset = 0x0].................................... 564
7.3.11 FLASHPP Register (Offset = 0xFC0) [reset = 0x701401FF] ............................................. 565
7.3.12 SSIZE Register (Offset = 0xFC4) [reset = 0x3FF] ......................................................... 566
7.3.13 FLASHCONF Register (Offset = 0xFC8) [reset = 0x0] .................................................... 567
7.3.14 ROMSWMAP Register (Offset = 0xFCC) [reset = 0x0].................................................... 568
7.3.15 FLASHDMASZ Register (Offset = 0xFD0) [reset = 0x0] .................................................. 569
7.3.16 FLASHDMAST Register (Offset = 0xFD4) [reset = 0x0] .................................................. 570
7.4 EEPROM Registers ...................................................................................................... 571
7.4.1 EESIZE Register (Offset = 0x0) [reset = 0x00600600] ..................................................... 572
7.4.2 EEBLOCK Register (Offset = 0x4) [reset = 0x0] ............................................................ 573
7.4.3 EEOFFSET Register (Offset = 0x8) [reset = 0x0]........................................................... 574
7.4.4 EERDWR Register (Offset = 0x10) [reset = X] .............................................................. 575
7.4.5 EERDWRINC Register (Offset = 0x14) [reset = X].......................................................... 576
7.4.6 EEDONE Register (Offset = 0x18) [reset = 0x0] ............................................................ 577
7.4.7 EESUPP Register (Offset = 0x1C) [reset = X]............................................................... 579
7.4.8 EEUNLOCK Register (Offset = 0x20) [reset = X] ........................................................... 580
7.4.9 EEPROT Register (Offset = 0x30) [reset = 0x0]............................................................. 581
7.4.10 EEPASS0 to EEPASS2 Registers (Offset = 0x34 to 0x3C) [reset = X] ................................. 582
7.4.11 EEINT Register (Offset = 0x40) [reset = 0x0]............................................................... 583
7.4.12 EEHIDE0 Register (Offset = 0x50) [reset = 0x0]........................................................... 584
7.4.13 EEHIDE1 Register (Offset = 0x54) [reset = 0x0]........................................................... 585
7.4.14 EEHIDE2 Register (Offset = 0x58) [reset = 0x0]........................................................... 586
7.4.15 EEDBGME Register (Offset = 0x80) [reset = 0x0] ......................................................... 587
7.4.16 EEPROMPP Register (Offset = 0xFC0) [reset = 0x1FF].................................................. 588
7.5 System Control Memory Registers..................................................................................... 589
7.5.1 RVP Register (Offset = 0xD4) [reset = 0x0101FFF0]....................................................... 590
7.5.2 BOOTCFG Register (Offset = 0x1D0) [reset = 0xFFFFFFFE]............................................. 591
7.5.3 USER_REG0 to USER_REG3 Registers (Offset = 0x1E0 to 0x1EC) [reset = 0xFFFFFFFF] ........ 594
7.5.4 FMPRE0 to FMPRE15 Registers (Offset = 0x200 to 0x23C) [reset = 0xFFFFFFFF] .................. 595
7.5.5 FMPPE0 to FMPPE15 Registers (Offset = 0x400 to 0x43C) [reset = 0xFFFFFFFF]................... 597
8 Micro Direct Memory Access (µDMA) .................................................................................. 599
8.1 Introduction ................................................................................................................ 600
8.2 Block Diagram............................................................................................................. 600
8.3 Functional Description.................................................................................................... 601
8.3.1 Priority............................................................................................................. 602
8.3.2 Arbitration Size................................................................................................... 602
8.3.3 Request Types................................................................................................... 602
8.3.4 Channel Configuration .......................................................................................... 603
8.3.5 Transfer Modes .................................................................................................. 604

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8.3.6 Transfer Size and Increment................................................................................... 612
8.3.7 Peripheral Interface.............................................................................................. 612
8.3.8 Software Request................................................................................................ 613
8.3.9 Interrupts and Errors ............................................................................................ 613
8.4 Initialization and Configuration.......................................................................................... 613
8.4.1 Module Initialization.............................................................................................. 613
8.4.2 Configuring a Memory-to-Memory Transfer.................................................................. 614
8.4.3 Configuring a Peripheral for Simple Transmit................................................................ 615
8.4.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 616
8.4.5 Configuring Channel Assignments ............................................................................ 618
8.5 µDMA Channel Control Structure Registers .......................................................................... 620
8.5.1 DMASRCENDP Register (Offset = 0x0) [reset = X]......................................................... 621
8.5.2 DMADSTENDP Register (Offset = 0x4) [reset = X]......................................................... 622
8.5.3 DMACHCTL Register (Offset = 0x8) [reset = X]............................................................. 623
8.6 µDMA Registers........................................................................................................... 626
8.6.1 DMASTAT Register (Offset = 0x0) [reset = 0x001F0000].................................................. 628
8.6.2 DMACFG Register (Offset = 0x4) [reset = X]................................................................ 629
8.6.3 DMACTLBASE Register (Offset = 0x8) [reset = 0x0]....................................................... 630
8.6.4 DMAALTBASE Register (Offset = 0xC) [reset = 0x200].................................................... 631
8.6.5 DMAWAITSTAT Register (Offset = 0x10) [reset = 0x03C3CF00]......................................... 632
8.6.6 DMASWREQ Register (Offset = 0x14) [reset = X].......................................................... 633
8.6.7 DMAUSEBURSTSET Register (Offset = 0x18) [reset = 0x0].............................................. 634
8.6.8 DMAUSEBURSTCLR Register (Offset = 0x1C) [reset = X]................................................ 635
8.6.9 DMAREQMASKSET Register (Offset = 0x20) [reset = 0x0]............................................... 636
8.6.10 DMAREQMASKCLR Register (Offset = 0x24) [reset = X] ................................................ 637
8.6.11 DMAENASET Register (Offset = 0x28) [reset = 0x0]...................................................... 638
8.6.12 DMAENACLR Register (Offset = 0x2C) [reset = X]........................................................ 639
8.6.13 DMAALTSET Register (Offset = 0x30) [reset = 0x0] ...................................................... 640
8.6.14 DMAALTCLR Register (Offset = 0x34) [reset = X]......................................................... 641
8.6.15 DMAPRIOSET Register (Offset = 0x38) [reset = 0x0]..................................................... 642
8.6.16 DMAPRIOCLR Register (Offset = 0x3C) [reset = X]....................................................... 643
8.6.17 DMAERRCLR Register (Offset = 0x4C) [reset = 0x0] ..................................................... 644
8.6.18 DMACHMAP0 Register (Offset = 0x510) [reset = 0x0].................................................... 645
8.6.19 DMACHMAP1 Register (Offset = 0x514) [reset = 0x0].................................................... 646
8.6.20 DMACHMAP2 Register (Offset = 0x518) [reset = 0x0].................................................... 647
8.6.21 DMACHMAP3 Register (Offset = 0x51C) [reset = 0x0] ................................................... 648
8.6.22 DMAPeriphID4 Register (Offset = 0xFD0) [reset = 0x4]................................................... 649
8.6.23 DMAPeriphID0 Register (Offset = 0xFE0) [reset = 0x30] ................................................. 650
8.6.24 DMAPeriphID1 Register (Offset = 0xFE4) [reset = 0xB2]................................................. 651
8.6.25 DMAPeriphID2 Register (Offset = 0xFE8) [reset = 0xB] .................................................. 652
8.6.26 DMAPeriphID3 Register (Offset = 0xFEC) [reset = 0x0] .................................................. 653
8.6.27 DMAPCellID0 Register (Offset = 0xFF0) [reset = 0xD].................................................... 654
8.6.28 DMAPCellID1 Register (Offset = 0xFF4) [reset = 0xF0]................................................... 655
8.6.29 DMAPCellID2 Register (Offset = 0xFF8) [reset = 0x5] .................................................... 656
8.6.30 DMAPCellID3 Register (Offset = 0xFFC) [reset = 0xB1].................................................. 657
9 Advance Encryption Standard Accelerator (AES) ................................................................. 658
9.1 AES Overview............................................................................................................. 659
9.2 AES Functional Description ............................................................................................. 659
9.2.1 AES Block Diagram ............................................................................................. 659
9.2.2 AES Algorithm.................................................................................................... 662
9.2.3 AES Operating Modes .......................................................................................... 663
9.2.4 AES Software Reset............................................................................................. 671
9.2.5 Power Management............................................................................................. 671

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9.2.6 Hardware Requests ............................................................................................. 671
9.3 AES Performance Information .......................................................................................... 672
9.4 AES Module Programming Guide ...................................................................................... 674
9.4.1 AES Low - Level Programming Models....................................................................... 674
9.5 AES Registers............................................................................................................. 679
9.5.1 AES_KEYn_n Register (Offset = 0x000 to 0x03C) [reset = 0x0].......................................... 681
9.5.2 AES_IV_IN_0 to AES_IV_IN_3 Registers (Offset = 0x40 to 0x4C) [reset = 0x0]....................... 682
9.5.3 AES_CTRL Register (Offset = 0x50) [reset = 0x80000000] ............................................... 683
9.5.4 AES_C_LENGTH_0 to AES_C_LENGTH_1 Registers (Offset = 0x54 to 0x58) [reset = 0x0] ........ 686
9.5.5 AES_AUTH_LENGTH Register (Offset = 0x5C) [reset = 0x0]............................................. 687
9.5.6 AES_DATA_IN_0 to AES_DATA_IN_3 Registers (Offset = 0x60 to 0x6C) [reset = 0x0].............. 688
9.5.7 AES_TAG_OUT_0 to AES_TAG_OUT_3 Registers (Offset = 0x70 to 0x7C) [reset = 0x0]........... 689
9.5.8 AES_REVISION Register (Offset = 0x80) [reset = 0x41] .................................................. 690
9.5.9 AES_SYSCONFIG Register (Offset = 0x84) [reset = 0x1]................................................. 691
9.5.10 AES_SYSSTATUS Register (Offset = 0x88) [reset = 0x1]................................................ 693
9.5.11 AES_IRQSTATUS Register (Offset = 0x8C) [reset = 0x0]................................................ 694
9.5.12 AES_IRQENABLE Register (Offset = 0x90) [reset = 0x0] ................................................ 695
9.5.13 AES_DIRTYBITS Register (Offset = 0x94) [reset = 0x0].................................................. 696
9.6 AES µDMA Registers .................................................................................................... 697
9.6.1 AES_DMAIM Register (Offset = 0x20) [reset = 0x0]........................................................ 698
9.6.2 AES_DMARIS Register (Offset = 0x24) [reset = 0x0] ...................................................... 699
9.6.3 AES_DMAMIS Register (Offset = 0x28) [reset = 0x0]...................................................... 700
9.6.4 AES_DMAIC Register (Offset = 0x2C) [reset = 0x0]........................................................ 701
10 Analog-to-Digital Converter (ADC) ...................................................................................... 702
10.1 Introduction ................................................................................................................ 703
10.2 Block Diagram............................................................................................................. 703
10.3 Functional Description.................................................................................................... 704
10.3.1 Sample Sequencers............................................................................................ 704
10.3.2 Module Control.................................................................................................. 705
10.3.3 Hardware Sample Averaging Circuit ......................................................................... 709
10.3.4 Analog-to-Digital Converter.................................................................................... 710
10.3.5 Differential Sampling ........................................................................................... 712
10.3.6 Internal Temperature Sensor.................................................................................. 713
10.3.7 Digital Comparator Unit........................................................................................ 714
10.4 Initialization and Configuration.......................................................................................... 717
10.4.1 Module Initialization ............................................................................................ 717
10.4.2 Sample Sequencer Configuration ............................................................................ 717
10.5 ADC Registers ............................................................................................................ 719
10.5.1 ADCACTSS Register (Offset = 0x0) [reset = 0x0] ......................................................... 721
10.5.2 ADCRIS Register (Offset = 0x4) [reset = 0x0].............................................................. 723
10.5.3 ADCIM Register (Offset = 0x8) [reset = 0x0] ............................................................... 725
10.5.4 ADCISC Register (Offset = 0xC) [reset = 0x0].............................................................. 727
10.5.5 ADCOSTAT Register (Offset = 0x10) [reset = 0x0]........................................................ 730
10.5.6 ADCEMUX Register (Offset = 0x14) [reset = 0x0] ......................................................... 731
10.5.7 ADCUSTAT Register (Offset = 0x18) [reset = 0x0] ........................................................ 734
10.5.8 ADCTSSEL Register (Offset = 0x1C) [reset = 0x0]........................................................ 735
10.5.9 ADCSSPRI Register (Offset = 0x20) [reset = 0x3210] .................................................... 737
10.5.10 ADCSPC Register (Offset = 0x24) [reset = 0x0].......................................................... 738
10.5.11 ADCPSSI Register (Offset = 0x28) [reset = X]............................................................ 740
10.5.12 ADCSAC Register (Offset = 0x30) [reset = 0x0].......................................................... 742
10.5.13 ADCDCISC Register (Offset = 0x34) [reset = 0x0]....................................................... 743
10.5.14 ADCCTL Register (Offset = 0x38) [reset = 0x0] .......................................................... 745
10.5.15 ADCSSMUX0 Register (Offset = 0x40) [reset = 0x0] .................................................... 746

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10.5.16 ADCSSCTL0 Register (Offset = 0x44) [reset = 0x0] ..................................................... 748
10.5.17 ADCSSFIFO0 to ADCSSFIFO3 Registers [reset = X] ................................................... 752
10.5.18 ADCSSFSTAT0 to ADCSSFSTAT3 Registers [reset = 0x00000100].................................. 753
10.5.19 ADCSSOP0 Register (Offset = 0x50) [reset = 0x0] ...................................................... 754
10.5.20 ADCSSDC0 Register (Offset = 0x54) [reset = 0x0] ...................................................... 755
10.5.21 ADCSSEMUX0 Register (Offset = 0x58) [reset = 0x0]................................................... 756
10.5.22 ADCSSTSH0 Register (Offset = 0x5C) [reset = 0x0]..................................................... 758
10.5.23 ADCSSMUX1 and ADCSSMUX2 Registers [reset = 0x0]............................................... 760
10.5.24 ADCSSCTL1 and ADCSSCTL2 Registers [reset = 0x0]................................................. 761
10.5.25 ADCSSOP1 and ADCSSOP2 Registers [reset = 0x0] ................................................... 764
10.5.26 ADCSSDC1 and ADCSSDC2 Registers [reset = 0x0] ................................................... 765
10.5.27 ADCSSEMUX1 and ADCSSEMUX2 Registers [reset = 0x0] ........................................... 766
10.5.28 ADCSSTSH1 and ADCSSTSH2 Registers [reset = 0x0] ................................................ 768
10.5.29 ADCSSMUX3 Register (Offset = 0xA0) [reset = 0x0].................................................... 769
10.5.30 ADCSSCTL3 Register (Offset = 0xA4) [reset = 0x0]..................................................... 770
10.5.31 ADCSSOP3 Register (Offset = 0xB0) [reset = 0x0] ...................................................... 771
10.5.32 ADCSSDC3 Register (Offset = 0xB4) [reset = 0x0] ...................................................... 772
10.5.33 ADCSSEMUX3 Register (Offset = 0xB8) [reset = 0x0] .................................................. 773
10.5.34 ADCSSTSH3 Register (Offset = 0xBC) [reset = 0x0] .................................................... 774
10.5.35 ADCDCRIC Register (Offset = 0xD00) [reset = 0x0]..................................................... 775
10.5.36 ADCDCCTL0 to ADCDCCTL7 Registers [reset = 0x0] .................................................. 779
10.5.37 ADCDCCMP0 to ADCDCCMP7 Registers [reset = 0x0]................................................. 781
10.5.38 ADCPP Register (Offset = 0xFC0) [reset = 0x01B02187]............................................... 782
10.5.39 ADCPC Register (Offset = 0xFC4) [reset = 0x7].......................................................... 784
10.5.40 ADCCC Register (Offset = 0xFC8) [reset = 0x1] ......................................................... 785
11 Controller Area Network (CAN) Module ............................................................................... 786
11.1 Introduction ................................................................................................................ 787
11.2 Block Diagram............................................................................................................. 787
11.3 Functional Description.................................................................................................... 788
11.3.1 Initialization ...................................................................................................... 789
11.3.2 Operation ........................................................................................................ 789
11.3.3 Transmitting Message Objects................................................................................ 790
11.3.4 Configuring a Transmit Message Object .................................................................... 790
11.3.5 Updating a Transmit Message Object ....................................................................... 791
11.3.6 Accepting Received Message Objects....................................................................... 792
11.3.7 Receiving a Data Frame....................................................................................... 792
11.3.8 Receiving a Remote Frame ................................................................................... 792
11.3.9 Receive and Transmit Priority................................................................................. 793
11.3.10 Configuring a Receive Message Object.................................................................... 793
11.3.11 Handling of Received Message Objects ................................................................... 794
11.3.12 Handling of Interrupts......................................................................................... 795
11.3.13 Test Mode...................................................................................................... 796
11.3.14 Bit Timing Configuration Error Considerations ............................................................ 797
11.3.15 Bit Time and Bit Rate......................................................................................... 797
11.3.16 Calculating the Bit Timing Parameters ..................................................................... 799
11.4 CAN Registers ............................................................................................................ 803
11.4.1 CANCTL Register (Offset = 0x0) [reset = 0x1] ............................................................. 805
11.4.2 CANSTS Register (Offset = 0x4) [reset = 0x0] ............................................................. 807
11.4.3 CANERR Register (Offset = 0x8) [reset = 0x0]............................................................. 809
11.4.4 CANBIT Register (Offset = 0xC) [reset = 0x2301] ......................................................... 810
11.4.5 CANINT Register (Offset = 0x10) [reset = 0x0]............................................................. 811
11.4.6 CANTST Register (Offset = 0x14) [reset = X] .............................................................. 812
11.4.7 CANBRPE Register (Offset = 0x18) [reset = X] ............................................................ 813

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11.4.8 CANIFnCRQ Register (Offset = 0x20) [reset = 0x1]....................................................... 814
11.4.9 CANIFnCMSK Register [reset = 0x0] ........................................................................ 815
11.4.10 CANIFnMSK1 Register [reset = 0xFFFF].................................................................. 817
11.4.11 CANIFnMSK2 Register [reset = 0xE0FF].................................................................. 818
11.4.12 CANIFnARB1 Register [reset = 0x0] ....................................................................... 819
11.4.13 CANIFnARB2 Register [reset = 0x0] ....................................................................... 820
11.4.14 CANIFnMCTL Register [reset = 0x0]....................................................................... 821
11.4.15 CANIFnDnn Register [reset = 0x0] ......................................................................... 823
11.4.16 CANTXRQn Register [reset = 0x0] ......................................................................... 824
11.4.17 CANNWDAn Register [reset = 0x0]......................................................................... 825
11.4.18 CANMSGnINT Register [reset = 0x0] ...................................................................... 826
11.4.19 CANMSGnVAL Register [reset = 0x0]...................................................................... 827
12 Analog Comparators ........................................................................................................ 828
12.1 Introduction ................................................................................................................ 829
12.2 Block Diagram............................................................................................................. 830
12.3 Functional Description.................................................................................................... 830
12.3.1 Internal Reference Programming............................................................................. 831
12.4 Initialization and Configuration.......................................................................................... 833
12.5 Comparator Registers.................................................................................................... 834
12.5.1 ACMIS Register (Offset = 0x0) [reset = 0x0]................................................................ 835
12.5.2 ACRIS Register (Offset = 0x4) [reset = 0x0]................................................................ 836
12.5.3 ACINTEN Register (Offset = 0x8) [reset = 0x0] ............................................................ 837
12.5.4 ACREFCTL Register (Offset = 0x10) [reset = 0x0] ........................................................ 838
12.5.5 ACSTATn Register [reset = 0x0] ............................................................................. 839
12.5.6 ACCTLn Register [reset = 0x0] ............................................................................... 840
12.5.7 ACMPPP Register (Offset = 0xFC0) [reset = 0x70007] ................................................... 841
13 Cyclical Redundancy Check (CRC) ..................................................................................... 842
13.1 Introduction ................................................................................................................ 843
13.2 Functional Description.................................................................................................... 843
13.2.1 CRC Support.................................................................................................... 843
13.3 Initialization and Configuration.......................................................................................... 844
13.3.1 CRC Initialization and Configuration ......................................................................... 844
13.4 CRC Registers ............................................................................................................ 846
13.4.1 CRCCTRL Register (Offset = 400h) [reset = 0h]........................................................... 847
13.4.2 CRCSEED Register (Offset = 410h) [reset = 0h]........................................................... 849
13.4.3 CRCDIN Register (Offset = 414h) [reset = 0h] ............................................................. 850
13.4.4 CRCRSLTPP Register (Offset = 418h) [reset = 0h]........................................................ 851
14 Data Encryption Standard Accelerator (DES) ....................................................................... 852
14.1 Introduction ................................................................................................................ 853
14.2 DES Functional Description ............................................................................................. 853
14.3 DES Block Diagram ...................................................................................................... 854
14.3.1 µDMA Control ................................................................................................... 854
14.3.2 Interrupt Control................................................................................................. 854
14.3.3 Register Interface............................................................................................... 855
14.3.4 DES Engine ..................................................................................................... 855
14.4 Software Reset............................................................................................................ 856
14.5 DES Supported Modes of Operation................................................................................... 856
14.5.1 ECB Feedback Mode .......................................................................................... 856
14.6 DES Module Programming Guide – Low Level Programming Models ............................................ 858
14.6.1 Surrounding Modules Global Initialization................................................................... 858
14.6.2 Operational Modes Configuration ............................................................................ 859
14.6.3 DES Events Servicing.......................................................................................... 861
14.7 DES Registers............................................................................................................. 863

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14.7.1 DES_KEYn_n Registers (Offset = 0x00 to 0x14) [reset = 0x0]........................................... 864
14.7.2 DES_IV_L Register (Offset = 0x18) [reset = 0x0].......................................................... 865
14.7.3 DES_IV_H Register (Offset = 0x1C) [reset = 0x0] ......................................................... 866
14.7.4 DES_CTRL Register (Offset = 0x20) [reset = 0x80000000].............................................. 867
14.7.5 DES_LENGTH Register (Offset = 0x24) [reset = 0x0]..................................................... 868
14.7.6 DES_DATA_L Register (Offset = 0x28) [reset = 0x0] ..................................................... 869
14.7.7 DES_DATA_H Register (Offset = 0x2C) [reset = 0x0]..................................................... 870
14.7.8 DES_REVISION Register (Offset = 0x30) [reset = 0x21] ................................................. 871
14.7.9 DES_SYSCONFIG Register (Offset = 0x34) [reset = 0x1]................................................ 872
14.7.10 DES_SYSSTATUS Register (Offset = 0x38) [reset = 0x1].............................................. 873
14.7.11 DES_IRQSTATUS Register (Offset = 0x3C) [reset = 0x0] .............................................. 874
14.7.12 DES_IRQENABLE Register (Offset = 0x40) [reset = 0x0]............................................... 875
14.7.13 DES_DIRTYBITS Register (Offset = 0x44) [reset = 0x0]................................................ 876
14.8 DES µDMA Registers .................................................................................................... 877
14.8.1 DES_DMAIM Register (Offset = 0x30) [reset = 0x0]....................................................... 878
14.8.2 DES_DMARIS Register (Offset = 0x34) [reset = 0x0] ..................................................... 879
14.8.3 DES_DMAMIS Register (Offset = 0x38) [reset = 0x0]..................................................... 880
14.8.4 DES_DMAIC Register (Offset = 0x3C) [reset = 0x0] ...................................................... 881
15 Ethernet Controller ........................................................................................................... 882
15.1 Introduction ................................................................................................................ 883
15.2 Block Diagram............................................................................................................. 884
15.3 Functional Description.................................................................................................... 884
15.3.1 Ethernet Clock Control......................................................................................... 884
15.3.2 MII and RMII Signals........................................................................................... 887
15.3.3 DMA Controller.................................................................................................. 888
15.3.4 TX/RX Controller................................................................................................ 909
15.3.5 MAC Operation.................................................................................................. 913
15.3.6 IEEE 1588 and Advanced Timestamp Function............................................................ 915
15.3.7 Frame Filtering.................................................................................................. 922
15.3.8 Source Address, VLAN, and CRC Insertion, Replacement or Deletion ................................. 924
15.3.9 Checksum Offload Engine..................................................................................... 925
15.3.10 MAC Management Counters ................................................................................ 926
15.3.11 Power Management Module................................................................................. 926
15.3.12 Serial Management Interface................................................................................ 929
15.3.13 Reduced Media Independent Interface (RMII) ............................................................ 929
15.3.14 Interrupt Configuration........................................................................................ 929
15.4 Ethernet PHY.............................................................................................................. 929
15.4.1 Integrated PHY Block Diagram ............................................................................... 930
15.4.2 Functional Description ......................................................................................... 930
15.4.3 Interface Configuration......................................................................................... 935
15.5 Initialization and Configuration.......................................................................................... 935
15.5.1 Ethernet PHY Initialization..................................................................................... 936
15.6 EMAC Registers .......................................................................................................... 939
15.6.1 EMACCFG Register (Offset = 0x0) [reset = 0x8000] ...................................................... 942
15.6.2 EMACFRAMEFLTR Register (Offset = 0x4) [reset = 0x0] ................................................ 946
15.6.3 EMACHASHTBLH Register (Offset = 0x8) [reset = 0x0].................................................. 949
15.6.4 EMACHASHTBLL Register (Offset = 0xC) [reset = 0x0].................................................. 950
15.6.5 EMACMIIADDR Register (Offset = 0x10) [reset = 0x0] ................................................... 951
15.6.6 EMACMIIDATA Register (Offset = 0x14) [reset = 0x0].................................................... 953
15.6.7 EMACFLOWCTL Register (Offset = 0x18) [reset = 0x0].................................................. 954
15.6.8 EMACVLANTG Register (Offset = 0x1C) [reset = 0x0].................................................... 956
15.6.9 EMACSTATUS Register (Offset = 0x24) [reset = 0x0] .................................................... 958
15.6.10 EMACRWUFF Register (Offset = 0x28) [reset = 0x0].................................................... 960

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15.6.11 EMACPMTCTLSTAT Register (Offset = 0x2C) [reset = 0x0] ........................................... 961
15.6.12 EMACLPICTLSTAT Register (Offset = 0x30) [reset = 0x0] ............................................. 963
15.6.13 EMACLPITIMERCTRL Register (Offset = 0x34) [reset = 0x0].......................................... 965
15.6.14 EMACRIS Register (Offset = 0x38) [reset = 0x0]......................................................... 966
15.6.15 EMACIM Register (Offset = 0x3C) [reset = 0x0].......................................................... 968
15.6.16 EMACADDR0H Register (Offset = 0x40) [reset = 0x8000FFFF] ....................................... 969
15.6.17 EMACADDR0L Register (Offset = 0x44) [reset = 0xFFFFFFFF]....................................... 970
15.6.18 EMACADDR1H Register (Offset = 0x48) [reset = 0xFFFF] ............................................. 971
15.6.19 EMACADDR1L Register (Offset = 0x4C) [reset = 0xFFFFFFFF]....................................... 972
15.6.20 EMACADDR2H Register (Offset = 0x50) [reset = 0xFFFF] ............................................. 973
15.6.21 EMACADDR2L Register (Offset = 0x54) [reset = 0xFFFFFFFF]....................................... 974
15.6.22 EMACADDR3H Register (Offset = 0x58) [reset = 0xFFFF] ............................................. 975
15.6.23 EMACADDR3L Register (Offset = 0x5C) [reset = 0xFFFFFFFF]....................................... 976
15.6.24 EMACWDOGTO Register (Offset = 0xDC) [reset = 0x0]................................................ 977
15.6.25 EMACMMCCTRL Register (Offset = 0x100) [reset = 0x0] .............................................. 978
15.6.26 EMACMMCRXRIS Register (Offset = 0x104) [reset = 0x0] ............................................. 980
15.6.27 EMACMMCTXRIS Register (Offset = 0x108) [reset = 0x0] ............................................. 982
15.6.28 EMACMMCRXIM Register (Offset = 0x10C) [reset = 0x0] .............................................. 984
15.6.29 EMACMMCTXIM Register (Offset = 0x110) [reset = 0x0]............................................... 985
15.6.30 EMACTXCNTGB Register (Offset = 0x118) [reset = 0x0]............................................... 986
15.6.31 EMACTXCNTSCOL Register (Offset = 0x14C) [reset = 0x0]........................................... 987
15.6.32 EMACTXCNTMCOL Register (Offset = 0x150) [reset = 0x0]........................................... 988
15.6.33 EMACTXOCTCNTG Register (Offset = 0x164) [reset = 0x0]........................................... 989
15.6.34 EMACRXCNTGB Register (Offset = 0x180) [reset = 0x0]............................................... 990
15.6.35 EMACRXCNTCRCERR Register (Offset = 0x194) [reset = 0x0]....................................... 991
15.6.36 EMACRXCNTALGNERR Register (Offset = 0x198) [reset = 0x0]...................................... 992
15.6.37 EMACRXCNTGUNI Register (Offset = 0x1C4) [reset = 0x0] ........................................... 993
15.6.38 EMACVLNINCREP Register (Offset = 0x584) [reset = 0x0] ............................................ 994
15.6.39 EMACVLANHASH Register (Offset = 0x588) [reset = 0x0] ............................................. 995
15.6.40 EMACTIMSTCTRL Register (Offset = 0x700) [reset = 0x2000] ........................................ 996
15.6.41 EMACSUBSECINC Register (Offset = 0x704) [reset = 0x0] ............................................ 999
15.6.42 EMACTIMSEC Register (Offset = 0x708) [reset = 0x0] ................................................ 1000
15.6.43 EMACTIMNANO Register (Offset = 0x70C) [reset = 0x0] ............................................. 1001
15.6.44 EMACTIMSECU Register (Offset = 0x710) [reset = 0x0] .............................................. 1002
15.6.45 EMACTIMNANOU Register (Offset = 0x714) [reset = 0x0]............................................ 1003
15.6.46 EMACTIMADD Register (Offset = 0x718) [reset = 0x0]................................................ 1004
15.6.47 EMACTARGSEC Register (Offset = 0x71C) [reset = 0x0]............................................. 1005
15.6.48 EMACTARGNANO Register (Offset = 0x720) [reset = 0x0]........................................... 1006
15.6.49 EMACHWORDSEC Register (Offset = 0x724) [reset = 0x0] .......................................... 1007
15.6.50 EMACTIMSTAT Register (Offset = 0x728) [reset = 0x0]............................................... 1008
15.6.51 EMACPPSCTRL Register (Offset = 0x72C) [reset = 0x0] ............................................. 1009
15.6.52 EMACPPS0INTVL Register (Offset = 0x760) [reset = 0x0]............................................ 1012
15.6.53 EMACPPS0WIDTH Register (Offset = 0x764) [reset = 0x0]........................................... 1013
15.6.54 EMACDMABUSMOD Register (Offset = 0xC00) [reset = 0x00020101].............................. 1014
15.6.55 EMACTXPOLLD Register (Offset = 0xC04) [reset = 0x0].............................................. 1017
15.6.56 EMACRXPOLLD Register (Offset = 0xC08) [reset = 0x0] ............................................. 1018
15.6.57 EMACRXDLADDR Register (Offset = 0xC0C) [reset = 0x0]........................................... 1019
15.6.58 EMACTXDLADDR Register (Offset = 0xC10) [reset = 0x0] ........................................... 1020
15.6.59 EMACDMARIS Register (Offset = 0xC14) [reset = 0x0] ............................................... 1021
15.6.60 EMACDMAOPMODE Register (Offset = 0xC18) [reset = 0x0]........................................ 1025
15.6.61 EMACDMAIM Register (Offset = 0xC1C) [reset = 0x0] ................................................ 1029
15.6.62 EMACMFBOC Register (Offset = 0xC20) [reset = 0x0] ................................................ 1031
15.6.63 EMACRXINTWDT Register (Offset = 0xC24) [reset = 0x0]............................................ 1032

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15.6.64 EMACHOSTXDESC Register (Offset = 0xC48) [reset = 0x0] ......................................... 1033
15.6.65 EMACHOSRXDESC Register (Offset = 0xC4C) [reset = 0x0] ........................................ 1034
15.6.66 EMACHOSTXBA Register (Offset = 0xC50) [reset = 0x0]............................................. 1035
15.6.67 EMACHOSRXBA Register (Offset = 0xC54) [reset = 0x0]............................................. 1036
15.6.68 EMACPP Register (Offset = 0xFC0) [reset = 0x103] ................................................... 1037
15.6.69 EMACPC Register (Offset = 0xFC4) [reset = 0x0080040E] ........................................... 1038
15.6.70 EMACCC Register (Offset = 0xFC8) [reset = 0x0]...................................................... 1041
15.6.71 EPHYRIS Register (Offset = 0xFD0) [reset = 0x0]...................................................... 1042
15.6.72 EPHYIM Register (Offset = 0xFD4) [reset = 0x0] ....................................................... 1043
15.6.73 EPHYMISC Register (Offset = 0xFD8) [reset = 0x0] ................................................... 1044
15.7 MII Management (EPHY) Registers .................................................................................. 1045
15.7.1 EPHYBMCR Register (Address = 0x0) [reset = 0x3100] ................................................ 1047
15.7.2 EPHYBMSR Register (Address = 0x1) [reset = 0x7849] ................................................ 1049
15.7.3 EPHYID1 Register (Address = 0x2) [reset = 0x2000].................................................... 1051
15.7.4 EPHYID2 Register (Address = 0x3) [reset = 0xA221].................................................... 1052
15.7.5 EPHYANA Register (Address = 0x4) [reset = 0x01E1] .................................................. 1053
15.7.6 EPHYANLPA Register (Address = 0x5) [reset = 0x0].................................................... 1055
15.7.7 EPHYANER Register (Address = 0x6) [reset = 0x4] ..................................................... 1056
15.7.8 EPHYANNPTR Register (Address = 0x7) [reset = 0x2001]............................................. 1057
15.7.9 EPHYANLNPTR Register (Address = 0x8) [reset = 0x0]................................................ 1058
15.7.10 EPHYCFG1 Register (Address = 0x9) [reset = 0x0].................................................... 1059
15.7.11 EPHYCFG2 Register (Address = 0xA) [reset = 0x4].................................................... 1061
15.7.12 EPHYCFG3 Register (Address = 0xB) [reset = 0x0].................................................... 1062
15.7.13 EPHYREGCTL Register (Address = 0xD) [reset = 0x0]................................................ 1063
15.7.14 EPHYADDAR Register (Address = 0xE) [reset = 0x0] ................................................. 1064
15.7.15 EPHYSTS Register (Address = 0x10) [reset = 0x2] .................................................... 1065
15.7.16 EPHYSCR Register (Address = 0x11) [reset = 0x103]................................................. 1067
15.7.17 EPHYMISR1 Register (Address = 0x12) [reset = 0x0] ................................................. 1069
15.7.18 EPHYMISR2 Register (Address = 0x13) [reset = 0x0] ................................................. 1071
15.7.19 EPHYFCSCR Register (Address = 0x14) [reset = 0x0] ................................................ 1073
15.7.20 EPHYRXERCNT Register (Address = 0x15) [reset = 0x0]............................................. 1074
15.7.21 EPHYBISTCR Register (Address = 0x16) [reset = 0x100]............................................. 1075
15.7.22 EPHYLEDCR Register (Address = 0x18) [reset = 0x400] ............................................. 1077
15.7.23 EPHYCTL Register (Address = 0x19) [reset = 0x8000]................................................ 1078
15.7.24 EPHY10BTSC Register (Address = 0x1A) [reset = 0x0] ............................................... 1079
15.7.25 EPHYBICSR1 Register (Address = 0x1B) [reset = 0x7D].............................................. 1080
15.7.26 EPHYBICSR2 Register (Address = 0x1C) [reset = 0x5EE]............................................ 1081
15.7.27 EPHYCDCR Register (Address = 0x1E) [reset = 0x102]............................................... 1082
15.7.28 EPHYRCR Register (Address = 0x1F) [reset = 0x0].................................................... 1083
15.7.29 EPHYLEDCFG Register (Address = 0x25) [reset = 0x510]............................................ 1084
16 External Peripheral Interface (EPI)..................................................................................... 1086
16.1 Introduction............................................................................................................... 1087
16.2 EPI Block Diagram...................................................................................................... 1088
16.3 Functional Description.................................................................................................. 1088
16.3.1 Master Access to EPI......................................................................................... 1089
16.3.2 Nonblocking Reads ........................................................................................... 1089
16.3.3 DMA Operation................................................................................................ 1090
16.4 Initialization and Configuration......................................................................................... 1090
16.4.1 EPI Interface Options......................................................................................... 1091
16.4.2 SDRAM Mode ................................................................................................. 1091
16.4.3 Host Bus Mode ................................................................................................ 1095
16.4.4 General-Purpose Mode....................................................................................... 1115
16.5 EPI Registers ............................................................................................................ 1122

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16.5.1 EPICFG Register (Offset = 0x0) [reset = 0x0]............................................................. 1124
16.5.2 EPIBAUD Register (Offset = 0x4) [reset = 0x0]........................................................... 1125
16.5.3 EPIBAUD2 Register (Offset = 0x8) [reset = 0x0] ......................................................... 1126
16.5.4 EPISDRAMCFG Register (Offset = 0x10) [reset = 0x82EE0000] ...................................... 1127
16.5.5 EPIHB8CFG Register (Offset = 0x10) [reset = 0x0008FF00]........................................... 1129
16.5.6 EPIHB16CFG Register (Offset = 0x10) [reset = 0x0008FF00].......................................... 1132
16.5.7 EPIGPCFG Register (Offset = 0x10) [reset = 0x0] ....................................................... 1136
16.5.8 EPIHB8CFG2 Register (Offset = 0x14) [reset = 0x00080000].......................................... 1138
16.5.9 EPIHB16CFG2 Register (Offset = 0x14) [reset = 0x00080000] ........................................ 1142
16.5.10 EPIADDRMAP Register (Offset = 0x1C) [reset = 0x0] ................................................. 1147
16.5.11 EPIRSIZE0 and EPIRSIZE1 Registers [reset = 0x3] ................................................... 1149
16.5.12 EPIRADDR0 and EPIRADDR1 Registers [reset = 0x0] ................................................ 1150
16.5.13 EPIRPSTD0 and EPIRPSTD1 Registers [reset = 0x0]................................................. 1151
16.5.14 EPISTAT Register (Offset = 0x60) [reset = 0x0] ........................................................ 1152
16.5.15 EPIRFIFOCNT Register (Offset = 0x6C) [reset = X].................................................... 1154
16.5.16 EPIREADFIFO0 to EPIREADFIFO7 Registers (Offset = 0x70 to 0x8C) [reset = X]................ 1155
16.5.17 EPIFIFOLVL Register (Offset = 0x200) [reset = 0x33] ................................................. 1156
16.5.18 EPIWFIFOCNT Register (Offset = 0x204) [reset = 0x4]................................................ 1158
16.5.19 EPIDMATXCNT Register (Offset = 0x208) [reset = 0x0]............................................... 1159
16.5.20 EPIIM Register (Offset = 0x210) [reset = 0x0]........................................................... 1160
16.5.21 EPIRIS Register (Offset = 0x214) [reset = 0x4] ......................................................... 1161
16.5.22 EPIMIS Register (Offset = 0x218) [reset = 0x0]......................................................... 1163
16.5.23 EPIEISC Register (Offset = 0x21C) [reset = 0x0]....................................................... 1165
16.5.24 EPIHB8CFG3 Register (Offset = 0x308) [reset = 0x00080000]....................................... 1166
16.5.25 EPIHB16CFG3 Register (Offset = 0x308) [reset = 0x00080000] ..................................... 1168
16.5.26 EPIHB8CFG4 Register (Offset = 0x30C) [reset = 0x00080000] ...................................... 1170
16.5.27 EPIHB16CFG4 Register (Offset = 0x30C) [reset = 0x00080000]..................................... 1172
16.5.28 EPIHB8TIME Register (Offset = 0x310) [reset = 0x00022000]........................................ 1174
16.5.29 EPIHB16TIME Register (Offset = 0x310) [reset = 0x00022000] ...................................... 1176
16.5.30 EPIHB8TIME2 Register (Offset = 0x314) [reset = 0xA000]............................................ 1178
16.5.31 EPIHB16TIME2 Register (Offset = 0x314) [reset = 0x00022000]..................................... 1180
16.5.32 EPIHB8TIME3 Register (Offset = 0x318) [reset = 0xA000]............................................ 1182
16.5.33 EPIHB16TIME3 Register (Offset = 0x318) [reset = 0x00022000]..................................... 1184
16.5.34 EPIHB8TIME4 Register (Offset = 0x31C) [reset = 0xA000] ........................................... 1186
16.5.35 EPIHB16TIME4 Register (Offset = 0x31C) [reset = 0x00022000] .................................... 1188
16.5.36 EPIHBPSRAM Register (Offset = 0x360) [reset = 0x0] ................................................ 1190
17 General-Purpose Input/Outputs (GPIOs) ............................................................................ 1191
17.1 Introduction............................................................................................................... 1192
17.2 Pad Capabilities ......................................................................................................... 1192
17.3 Functional Description.................................................................................................. 1193
17.3.1 Data Control ................................................................................................... 1194
17.3.2 Interrupt Control ............................................................................................... 1195
17.3.3 Mode Control .................................................................................................. 1197
17.3.4 Commit Control................................................................................................ 1197
17.3.5 Pad Control .................................................................................................... 1197
17.3.6 Identification.................................................................................................... 1198
17.4 Initialization and Configuration......................................................................................... 1198
17.5 GPIO Registers.......................................................................................................... 1201
17.5.1 GPIODATA Register (Offset = 0x0) [reset = 0x0]......................................................... 1204
17.5.2 GPIODIR Register (Offset = 0x400) [reset = 0x0] ........................................................ 1205
17.5.3 GPIOIS Register (Offset = 0x404) [reset = 0x0] .......................................................... 1206
17.5.4 GPIOIBE Register (Offset = 0x408) [reset = 0x0]......................................................... 1207
17.5.5 GPIOIEV Register (Offset = 0x40C) [reset = 0x0]........................................................ 1208

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17.5.6 GPIOIM Register (Offset = 0x410) [reset = 0x0].......................................................... 1209
17.5.7 GPIORIS Register (Offset = 0x414) [reset = 0x0] ........................................................ 1210
17.5.8 GPIOMIS Register (Offset = 0x418) [reset = 0x0]........................................................ 1211
17.5.9 GPIOICR Register (Offset = 0x41C) [reset = 0x0]........................................................ 1212
17.5.10 GPIOAFSEL Register (Offset = 0x420) [reset = X] ..................................................... 1213
17.5.11 GPIODR2R Register (Offset = 0x500) [reset = 0xFF] .................................................. 1215
17.5.12 GPIODR4R Register (Offset = 0x504) [reset = 0x0].................................................... 1216
17.5.13 GPIODR8R Register (Offset = 0x508) [reset = 0x0].................................................... 1217
17.5.14 GPIOODR Register (Offset = 0x50C) [reset = 0x0]..................................................... 1218
17.5.15 GPIOPUR Register (Offset = 0x510) [reset = X] ........................................................ 1219
17.5.16 GPIOPDR Register (Offset = 0x514) [reset = 0x0]...................................................... 1221
17.5.17 GPIOSLR Register (Offset = 0x518) [reset = 0x0] ...................................................... 1223
17.5.18 GPIODEN Register (Offset = 0x51C) [reset = X]........................................................ 1224
17.5.19 GPIOLOCK Register (Offset = 0x520) [reset = 0x1].................................................... 1226
17.5.20 GPIOCR Register (Offset = 0x524) [reset = X].......................................................... 1227
17.5.21 GPIOAMSEL Register (Offset = 0x528) [reset = 0x0] .................................................. 1228
17.5.22 GPIOPCTL Register (Offset = 0x52C) [reset = X]....................................................... 1229
17.5.23 GPIOADCCTL Register (Offset = 0x530) [reset = 0x0]................................................. 1231
17.5.24 GPIODMACTL Register (Offset = 0x534) [reset = 0x0] ................................................ 1232
17.5.25 GPIOSI Register (Offset = 0x538) [reset = 0x0]......................................................... 1233
17.5.26 GPIODR12R Register (Offset = 0x53C) [reset = 0x0] .................................................. 1234
17.5.27 GPIOWAKEPEN Register (Offset = 0x540) [reset = 0x0].............................................. 1235
17.5.28 GPIOWAKELVL Register (Offset = 0x544) [reset = 0x0]............................................... 1236
17.5.29 GPIOWAKESTAT Register (Offset = 0x548) [reset = 0x0]............................................. 1237
17.5.30 GPIOPP Register (Offset = 0xFC0) [reset = 0x1] ....................................................... 1238
17.5.31 GPIOPC Register (Offset = 0xFC4) [reset = 0x0]....................................................... 1239
17.5.32 GPIOPeriphID4 Register (Offset = 0xFD0) [reset = 0x0]............................................... 1241
17.5.33 GPIOPeriphID5 Register (Offset = 0xFD4) [reset = 0x0]............................................... 1242
17.5.34 GPIOPeriphID6 Register (Offset = 0xFD8) [reset = 0x0]............................................... 1243
17.5.35 GPIOPeriphID7 Register (Offset = 0xFDC) [reset = 0x0] .............................................. 1244
17.5.36 GPIOPeriphID0 Register (Offset = 0xFE0) [reset = 0x61] ............................................. 1245
17.5.37 GPIOPeriphID1 Register (Offset = 0xFE4) [reset = 0x0]............................................... 1246
17.5.38 GPIOPeriphID2 Register (Offset = 0xFE8) [reset = 0x18] ............................................. 1247
17.5.39 GPIOPeriphID3 Register (Offset = 0xFEC) [reset = 0x1]............................................... 1248
17.5.40 GPIOPCellID0 Register (Offset = 0xFF0) [reset = 0xD]................................................ 1249
17.5.41 GPIOPCellID1 Register (Offset = 0xFF4) [reset = 0xF0]............................................... 1250
17.5.42 GPIOPCellID2 Register (Offset = 0xFF8) [reset = 0x5] ................................................ 1251
17.5.43 GPIOPCellID3 Register (Offset = 0xFFC) [reset = 0xB1] .............................................. 1252
18 General-Purpose Timers .................................................................................................. 1253
18.1 Introduction............................................................................................................... 1254
18.2 Block Diagram ........................................................................................................... 1254
18.3 Functional Description.................................................................................................. 1256
18.3.1 GPTM Reset Conditions ..................................................................................... 1256
18.3.2 Timer Clock Source........................................................................................... 1257
18.3.3 Timer Modes................................................................................................... 1257
18.3.4 Wait-for-Trigger Mode ........................................................................................ 1265
18.3.5 Synchronizing GP Timer Blocks............................................................................. 1266
18.3.6 DMA Operation................................................................................................ 1267
18.3.7 ADC Operation ................................................................................................ 1267
18.3.8 Accessing Concatenated 16- or 32-Bit GPTM Register Values......................................... 1267
18.4 Initialization and Configuration......................................................................................... 1268
18.4.1 One-Shot and Periodic Timer Mode........................................................................ 1268
18.4.2 Real-Time Clock (RTC) Mode............................................................................... 1268

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Contents
18.4.3 Input Edge-Count Mode...................................................................................... 1269
18.4.4 Input Edge Time Mode ....................................................................................... 1269
18.4.5 PWM Mode..................................................................................................... 1269
18.5 GPTM Registers......................................................................................................... 1271
18.5.1 GPTMCFG Register (Offset = 0x0) [reset = X]............................................................ 1273
18.5.2 GPTMTAMR Register (Offset = 0x4) [reset = 0x0] ....................................................... 1274
18.5.3 GPTMTBMR Register (Offset = 0x8) [reset = 0x0] ....................................................... 1277
18.5.4 GPTMCTL Register (Offset = 0xC) [reset = 0x0] ......................................................... 1280
18.5.5 GPTMSYNC Register (Offset = 0x10) [reset = 0x0]...................................................... 1282
18.5.6 GPTMIMR Register (Offset = 0x18) [reset = 0x0] ........................................................ 1284
18.5.7 GPTMRIS Register (Offset = 0x1C) [reset = 0x0] ........................................................ 1286
18.5.8 GPTMMIS Register (Offset = 0x20) [reset = X] ........................................................... 1288
18.5.9 GPTMICR Register (Offset = 0x24) [reset = X] ........................................................... 1290
18.5.10 GPTMTAILR Register (Offset = 0x28) [reset = 0xFFFFFFFF]......................................... 1292
18.5.11 GPTMTBILR Register (Offset = 0x2C) [reset = 0xFFFF]............................................... 1293
18.5.12 GPTMTAMATCHR Register (Offset = 0x30) [reset = 0xFFFFFFFF] ................................. 1294
18.5.13 GPTMTBMATCHR Register (Offset = 0x34) [reset = 0xFFFF]........................................ 1295
18.5.14 GPTMTAPR Register (Offset = 0x38) [reset = 0x0]..................................................... 1296
18.5.15 GPTMTBPR Register (Offset = 0x3C) [reset = 0x0] .................................................... 1297
18.5.16 GPTMTAPMR Register (Offset = 0x40) [reset = 0x0] .................................................. 1298
18.5.17 GPTMTBPMR Register (Offset = 0x44) [reset = 0x0] .................................................. 1299
18.5.18 GPTMTAR Register (Offset = 0x48) [reset = 0xFFFFFFFF]........................................... 1300
18.5.19 GPTMTBR Register (Offset = 0x4C) [reset = 0xFFFF]................................................. 1301
18.5.20 GPTMTAV Register (Offset = 0x50) [reset = 0xFFFFFFFF]........................................... 1302
18.5.21 GPTMTBV Register (Offset = 0x54) [reset = 0xFFFF].................................................. 1303
18.5.22 GPTMRTCPD Register (Offset = 0x58) [reset = 0x7FFF].............................................. 1304
18.5.23 GPTMTAPS Register (Offset = 0x5C) [reset = 0x0] .................................................... 1305
18.5.24 GPTMTBPS Register (Offset = 0x60) [reset = 0x0]..................................................... 1306
18.5.25 GPTMDMAEV Register (Offset = 0x6C) [reset = 0x0].................................................. 1307
18.5.26 GPTMADCEV Register (Offset = 0x70) [reset = 0x0]................................................... 1309
18.5.27 GPTMPP Register (Offset = 0xFC0) [reset = 0x70]..................................................... 1311
18.5.28 GPTMCC Register (Offset = 0xFC8) [reset = 0x0]...................................................... 1312
19 Inter-Integrated Circuit (I2C) Interface ................................................................................ 1313
19.1 Introduction............................................................................................................... 1314
19.2 Block Diagram ........................................................................................................... 1315
19.3 Functional Description.................................................................................................. 1315
19.3.1 I2C Bus Functional Overview ................................................................................ 1316
19.3.2 Available Speed Modes ...................................................................................... 1320
19.3.3 Interrupts ....................................................................................................... 1323
19.3.4 Loopback Operation .......................................................................................... 1323
19.3.5 FIFO and µDMA Operation .................................................................................. 1324
19.3.6 Command Sequence Flow Charts.......................................................................... 1326
19.4 Initialization and Configuration......................................................................................... 1333
19.4.1 Configure the I2C Module to Transmit a Single Byte as a Master ...................................... 1333
19.4.2 Configure the I2C Master to High Speed Mode ........................................................... 1334
19.5 I2C Registers ............................................................................................................ 1335
19.5.1 I2CMSA Register (Offset = 0x0) [reset = 0x0]............................................................. 1336
19.5.2 I2CMCS Register (Offset = 0x4) [reset = 0x20]........................................................... 1337
19.5.3 I2CMDR Register (Offset = 0x8) [reset = 0x0] ............................................................ 1343
19.5.4 I2CMTPR Register (Offset = 0xC) [reset = 0x1] .......................................................... 1344
19.5.5 I2CMIMR Register (Offset = 0x10) [reset = 0x0].......................................................... 1345
19.5.6 I2CMRIS Register (Offset = 0x14) [reset = 0x0] .......................................................... 1347
19.5.7 I2CMMIS Register (Offset = 0x18) [reset = 0x0].......................................................... 1349

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19.5.8 I2CMICR Register (Offset = 0x1C) [reset = 0x0].......................................................... 1351
19.5.9 I2CMCR Register (Offset = 0x20) [reset = 0x0]........................................................... 1353
19.5.10 I2CMCLKOCNT Register (Offset = 0x24) [reset = 0x0] ................................................ 1354
19.5.11 I2CMBMON Register (Offset = 0x2C) [reset = 0x3]..................................................... 1355
19.5.12 I2CMBLEN Register (Offset = 0x30) [reset = 0x0] ...................................................... 1356
19.5.13 I2CMBCNT Register (Offset = 0x34) [reset = 0x0]...................................................... 1357
19.5.14 I2CSOAR Register (Offset = 0x800) [reset = 0x0] ...................................................... 1358
19.5.15 I2CSCSR Register (Offset = 0x804) [reset = 0x0] ...................................................... 1359
19.5.16 I2CSDR Register (Offset = 0x808) [reset = 0x0] ........................................................ 1361
19.5.17 I2CSIMR Register (Offset = 0x80C) [reset = 0x0]....................................................... 1362
19.5.18 I2CSRIS Register (Offset = 0x810) [reset = 0x0]........................................................ 1364
19.5.19 I2CSMIS Register (Offset = 0x814) [reset = 0x0] ....................................................... 1366
19.5.20 I2CSICR Register (Offset = 0x818) [reset = 0x0] ....................................................... 1368
19.5.21 I2CSOAR2 Register (Offset = 0x81C) [reset = 0x0] .................................................... 1369
19.5.22 I2CSACKCTL Register (Offset = 0x820) [reset = 0x0].................................................. 1370
19.5.23 I2CFIFODATA Register (Offset = 0xF00) [reset = 0x0] ................................................ 1371
19.5.24 I2CFIFOCTL Register (Offset = 0xF04) [reset = 0x00040004]........................................ 1372
19.5.25 I2CFIFOSTATUS Register (Offset = 0xF08) [reset = 0x00010005]................................... 1374
19.5.26 I2CPP Register (Offset = 0xFC0) [reset = 0x1].......................................................... 1375
19.5.27 I2CPC Register (Offset = 0xFC4) [reset = 0x1].......................................................... 1376
20 LCD Controller................................................................................................................ 1377
20.1 Introduction............................................................................................................... 1378
20.2 Block Diagram ........................................................................................................... 1378
20.3 Functional Description.................................................................................................. 1379
20.3.1 Clocking ........................................................................................................ 1379
20.3.2 LCD DMA Engine ............................................................................................. 1380
20.3.3 LIDD Bus Operation .......................................................................................... 1382
20.3.4 Raster Control ................................................................................................. 1383
20.3.5 LCD Frame Buffer............................................................................................. 1385
20.3.6 Palette RAM ................................................................................................... 1386
20.3.7 Palette .......................................................................................................... 1391
20.3.8 Grayscaler and Serializer – Passive (STN) Mode ........................................................ 1391
20.3.9 Grayscaler and Serializer – Active (TFT) Mode........................................................... 1391
20.3.10 Color and Grayscale Intensities and Modulation Rates ................................................ 1391
20.3.11 Summary of Color Depth ................................................................................... 1391
20.3.12 Output Format................................................................................................ 1392
20.3.13 Subpicture Feature .......................................................................................... 1393
20.4 Interrupts ................................................................................................................. 1394
20.5 Bus Transaction Modes ................................................................................................ 1395
20.6 Initialization and Configuration......................................................................................... 1395
20.7 LCD Registers ........................................................................................................... 1397
20.7.1 LCDPID Register (Offset = 0x0) [reset = X] ............................................................... 1398
20.7.2 LCDCTL Register (Offset = 0x4) [reset = 0x0] ............................................................ 1399
20.7.3 LCDLIDDCTL Register (Offset = 0xC) [reset = 0x0]...................................................... 1401
20.7.4 LIDDCS0CFG Register (Offset = 0x10) [reset = 0x00440044].......................................... 1403
20.7.5 LIDDCS0ADDR Register (Offset = 0x14) [reset = 0x0] .................................................. 1404
20.7.6 LIDDCS0DATA Register (Offset = 0x18) [reset = 0x0]................................................... 1405
20.7.7 LIDDCS1CFG Register (Offset = 0x1C) [reset = 0x00440044] ......................................... 1406
20.7.8 LIDDCS1ADDR Register (Offset = 0x20) [reset = 0x0] .................................................. 1407
20.7.9 LIDDCS1DATA Register (Offset = 0x24) [reset = 0x0]................................................... 1408
20.7.10 LCDRASTRCTL Register (Offset = 0x28) [reset = 0x0]................................................ 1409
20.7.11 LCDRASTRTIM0 Register (Offset = 0x2C) [reset = 0x0]............................................... 1412
20.7.12 LCDRASTRTIM1 Register (Offset = 0x30) [reset = 0x0]............................................... 1413