Quantum Q250 Product manual

Q200 Series™
Intelligent Disk Drives
Technical Reference Manual
For Q250, Q280
Disk Drives

Q200 SERIES
tm
INTELLIGENT DISK DRIVES
Q250jQ280
DISK DRIVES
Technical Reference Manual
Publication No. 81-45528
REV A

PREFACE
This manual contains technical reference information describing
the Q250 and Q280 rigid disk drives. Information is intended for
technicians and engineers evaluating or maintaining the drives, or
integrating them into systems.
Quantum reserves the right to make changes and/or improvements to its
products without incurring any obligation to incorporate such changes
or improvements in units previously sold or shipped.
Additional information on the Q250 and Q280 is given in the
following~manuals:
Publication No.
Quantum 81-45233
Quantum 81-45416
ANSI X3.131-1986
Title
Q250/Q280 Disk Drives. OEM Manual
Q200 Series Programmer's Manual
Small Computer System Interface (SCSI)
Quantum publications may be requested from your Quantum Sales
Representative, or may be ordered from Quantum in the same manner as
spare parts.
Publication No 81-45528 Rev. KL587
UL/CSA/VDE
UL recognition granted under File No. E78016
CSA certification granted under File Nos. LR496896-8 and LR496896-11
VDE certification granted per File No. 11342-3250-1002
WARRANTY
Model Q250 and Q280 disk drives are warranted against defects in
material and workmanship for a period of one year from date of
shipment. The warranty includes parts and labor. This is a limited
~arranty and further details can be obtained from your Quantum sales
representative. All requests for service should be directed to the
Quantum service center in your area.
PATENTS
The product described herein is covered by u.S. Patent No. 4,538,193,
and is the subject of allowed pending patent applications from which
u.S. Patents are expected to issue in 1987.
Copyright 1987 Quantum Corporation. All rights reserved.
Q200 Series and DisCache are trademarks of Quantum Corporation.
AIRLOCK is a registered trademark of Quantum Corporation.
Printed in U.S.A.
ii

TAB L E o F
CON TEN T S
PREFACE . .
ii
SECTION 1.
INTRODUCTION . . . .
1-1
1.1
1.2
Features . . . . . .
Logic Conventions ..
. . . . . . . . 1-1
. . . . . . . . 1-2
SECTION 2.
PRINCIPLES OF OPERATION ..
2-1
2.1 Head Disk Assembly (HDA) . . . . . . .. . ...... 2-1
2.1.1 Base casting Assembly. . . . .. . ...... 2-1
2.1.2 Disk Stack Assembly. . . . . ....... 2-2
2.1.3 Rotary positioner Assembly (Actuator) ....... 2-2
2.1.4 Headstack Assembly. . . . . . . . . . . 2-2
2.1.S Automatic Actuator Lock (AIRLOCK) ......... 2-2
2.1.6 DC Drive Motor. . . . . . ......... 2-2
2.1.7 Air Filtration. ... . . ......... 2-3
2.2 Drive Electronics. . .. . .............. 2-4
2.2. 1 Disk Format . . . . . . . . . .. ....... 2-4
2.2.2 Simplified Explanation--Block Diagram ....... 2-4
2.2.3 SCSI Bus Physical Interface. . ...... 2-8
2.2.4 SCSI Bus Signal Descriptions ............ 2-10
2.2.S SCSI Bus Timing. . .. ...... . . 2-11
2.2.6 Power Requirements. . . . .. ...... . 2-14
2.2.7 Shorting Plug Options. . ........... 2-16
2.2.8 Flex Circuit .................... 2-19
2.3 PCB Functional Elements. . .. . ........... 2-19
2.3.1 Power-On-Reset (POR) and Warm Reset ........ 2-19
2.3.2 Motor Control Circuit ............... 2-20
2.3.3 Electronic Return Spring. . . . .. . ..... 2-21
2.3.4 S080 SCSI Bus Controller. . . . ...... 2-21
2.3.S Servo Control, AMC and Servo AGC. . . . .. .. 2-23
2.3.6 Actuator Positioning circuit. . .. . ..... 2-27
2.3.7 Read/Write Circuit. . . . . . . . . . . . . .. 2-27
2.3.8 FYLO Timing Controller IC, and xtal Oscillators .. 2-29
2.3.9 DICEY Data Controller IC. ........ . 2-30
2.3.10 Microprocessor and EPROM ......... 2-32
2.4 Power-Up Sequence/Recalibration. . .......... 2-32
2.S Read Command Sequence. . . . . . . . . ...... 2-33
2.6 write Command Sequence. . .. . ........... 2-33
SECTION 3.
ENGINEERING DRAWINGS . .
3-1
iii

SECTION 4.
APPLICATIONS . . . . . . . .
4-1
4.1 Special Considerations. . . . . . .... 4-1
4.1.1 -REQ/-ACK Handshake. . ...... 4-1
4.1.2 Hints for Software Driver writers ... .. 4-3
4.2 Errors and Media Defects. . . . . . . . . .. . ... 4-5
4 • 2 • 1 Errors. . . . . . . . . . . . . . . .. .... 4 - 5
4.2.2 Allocating Replacement Sectors. . ....... 4-6
4.2.3 Creating the Defect Lists. . . . . . . 4-8
4.2.4 Updating the Drive Using the Defect Lists ..... 4-9
4.3 Grounding, Electrostatic Discharges, and EMI . . ... 4-10
SECTION 5.
MAINTENANCE. . . . •
5-1
5.1 Maintenance Precautions. . . . . . . . . . .. . ... 5-1
5.2 Level 1 Maintenance. . . . . . . . . . .. . ..... 5-1
5.3 Level 2 Maintenance. . . . ............ 5-2
5.4 Connector Maintenance. . . . . .. . ......... 5-2
5.5 PCB Waveforms and Techniques. . . . . . . . . .. .• 5-2
5.5.1 Special Test Equipment ............... 5-2
5.5.2 Techniques and Waveform Descriptions ........ 5-3
5.5.3 Test Connector J5 Signals. . . . . . . .. .. 5-4
SECTION 6. PARTS LISTS ... .
6.1 Spare Parts List .... .
6.2 Reference Parts List(s) ..
iv
. . 6-1
6-1
6-2

2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
LIS T o F
FIG U RES
Exploded View . . . . . . .. ...... . . 2-1
Inside View of Drive, Showing Air Filtration. . . . . . . 2-3
Disk Format: Wedges, Sectors, and Tracks. . . . . . . . . 2-5
Electronics Block Diagram .. ............ 2-6
J1 Connector. . . . . . . .. ..... ..... 2-9
SCSI Bus. Typical Circuit of a Signal Line ....... 2-10
SCSI Bus Timing Diagram . . . . • . . . . . . . . . . . . 2-13
Drive Startup Current Profile . . . . .. ...... 2-16
General PCB Layout; Plug, Terminator and ......... 2-17
Connector Locations
· . . . . . . . . 2 -2 2
5080 Conceptual Block Diagram. . . . .
5080 Interface Diagram . . . . . . .
Servo AMC and ADC Circuit Waveforms.
Read Circuit Waveforms . . . . . . . . .
· . . . . . . . 2-22
· . .. .. 2-25
· . . . 2-28
DICEY Block Diagram. . . . . . .. ...
· . . . . . 2-31
Power-Up Sequence. .. .. . . . . . · . . . . .
2-34
Read Command Sequence. . . .. ... . · .
.. . 2-35
write Command Sequence . . . . . .. . · . . . . . .
2-36
Printed
Circuit Board Parts Locations
(PCB-7)
· ·
3-2
Schematic,
PCB-7,
Sheet
1 · · · · · · · ·
3-3
Schematic,
PCB-7, Sheet
2 · · · · · · · · · · · ·
3-4
Schematic,
PCB-7,
Sheet
3 · · · · · · · · · · · · · · · ·
3-5
Printed
Circuit Board Parts Locations
(PCB-8)
· ·
3-6
Schematic,
PCB-8, Sheet
1 · · · · · · · · ·
3-7
Schematic,
PCB-8,
Sheet
2 · · · · · · · · · · · · · · · ·
3-8
Schematic,
PCB-8, Sheet
3 · · · · · · · · · · · · · ·
3-9
Printed
Circuit Board Parts Locations
(PCB-9)
· · · · · ·
3-10
Schematic,
PCB-9, Sheet
1 · · · · · · · · ·
3-11
Schematic,
PCB-9, Sheet
2 · · · · · · · · ·
3-12
Schematic,
PCB-9, Sheet
3 · · · · · · · · · ·
3-13
-REQ/-ACK Handshake. Q250/Q280 Target Sends Data . . 4-2
Buffer Full and Empty Ratios. . . . . . . . . . . . . . . 4-3
In-Line Sparing of Defective Sectors. . . .. . ... 4-7
In-Line Sparing Overflow of Defective Sectors . . . . . . 4-7
Sparing of Field-Found Defective Sectors. . . . . . . . . 4-8
Test Waveforms(1)
Test Waveforms(2)
Test Waveforms(3)
v
· . . . . 5-6
· . 5-7
· . . . . . 5-8

2-1
2-2
2-3
4-1
5-1
LIS T o F TAB L E S
J1 Pin Assignments. . ..... .
DC Power Requirements . . . . .. ...
Microprocessors and Buffer RAM. . . . . .
Available Spare and Defective Sectors .
Test Connector J5 Signals . .
vi
. 2-9
. . . • . • 2-15
· • • 2-32
· . . 4-8
· . • 5-5

1.1 Features
Q250 and Q280 drives feature on-board, ANSI-standard, Small Computer
System Interface (SCSI) controllers, and, with the exception of a
plug-in EPROM IC, both models use the same printed circuit board
(PCB). These drives require no operational adjustments. All
electronics except the spindle motor, headstack, flex circuit, heads,
and actuator rotor are contained on the PCB. A single IC is mounted on
the flex circuit inside the sealed assembly.
The following features of the Q250/Q280 drives enable high data
throughput:
o Seeks are initiated immediately--other commands are
processed simultaneously.
o 14 KByte FIFO data buffer balances the transfer of data to
and from the SCSI bus as well as to and from the drive.
o Optional DisCache increases data buffer size to 60 KBytes.
(See the Q200 Series Programmers Manual for details
concerning this option.)
o Cylinder and head skewing scheme minimizes latency when
accessing data sequentially across cylinder boundaries.
o Defect management scheme minimizes seeks to spare sectors.
o Multiple block transfer of up to 64K-1 blocks, each with up
to 2 Kbytes.
o RLL 1,7 (run-length-Iimited) encoding increases data density
on the disks.
1-1

SCSI commands relieve the host system of many tasks, such as defect
management, error correction, and physical sector addressing.
Programmable options allow users flexible ways to handle defects
initially and throughout the product's life. For example, (1)
defective sectors can be automatically reassigned without the need
to reformat, (2) data can be corrected with a Reed-Solomon error
correcting code (ECC) , or (3) all error detection and correction can
be handled in the host computer. The ECC can correct one burst error
of 17 bits, or detect three burst errors of 17 bits each.
Q200 Series
tm
drives employ a hard-sectored format with servo data
factory-written in wedges between all sectors on all surfaces. Thus,
thermal and mechanical effects which tend to misalign heads on the
headstack assembly are minimized, in comparison with other drives
which use a dedicated servo surface. In addition, conservative linear
bit and track densities ensure high data integrity. Logical block
sizes of 512, 1024, and 2048 bytes are supported.
1.2
Logic Conventions
Signals on the SCSI bus are all true or asserted when they are at low
level, and false or non-asserted when they are at high level. In this
document, the names of such signals are always preceded by a minus, as
"-ACK," and the timing diagrams are drawn to show the signals asserted
when they are low, as they might be observed with an oscilloscope.
other signals, as on the PCB, are indicated as follows:
Signal Type
Asserted when low
Asserted when high
Differential
Analog
Examples
-paR
+POR
Asserted when +READ SIG is more
positive than -READ SIG
WRITE CURRENT, 5 V
Note that the ANSI Standard for SCSI, ANSI X3.131-1986 uses, for
example, "-ACK" when listing connector pin connections, but describes
the signals as "ACK" in the text, and shows positive true signals
"+ACK" on timing diagrams.
1-2

SECTION 2. PRINCIPLES OF OPERATION
2.1
Head Disk Assembly (HDA)
2.1.1 Base Casting Assembly
The single piece, aluminum alloy base casting provides a mounting
surface for the rest of the drive mechanism, PCB, and shock mount
brackets. See Figure 2-1 for relative locations.
yo '\~'ST ~:K ASSEMBLY
r- HEADS
/
ACTUATOR
UPPER AND LOWER
MAGNETS
FACEPLATE
DISK CLAMP
MAGNETIC DISK
! I!
/t:tD
/' '
/' !
MOUNTING HOLES
Figure 2-1: Exploded View
2-1
RECIRCULATION ~
FIL TER ",
,
BASE CASTING
PRINTED CIRCUIT
BOARD
~ MOUNTING
/' BRACKET
/~/

2.1.2 Disk Stack Assembly
Three aluminum alloy disks (two for the Q250) are placed on the motor
hub and clamped in place. A thin film magnetic metal is sputtered on
the surfaces of the disks, and lubricated with a carbon overcoat that
prevents head and media wear when the heads are in contact with the
head surface. This only occurs in the landing zone outside the data
area, and when the disks are not rotating at full speed.
2.1.3 Rotary positioner Assembly (Actuator)
The positioner is a proprietary design consisting of upper and lower
permanent magnet plates, and a rotary single phase coil molded to
the headstack mounting hub shaft. The magnets are composed of two
alternating poles bonded to the magnet plates which, in turn, are
bolted to the base casting. Resilient crash stops are mounted to the
magnet plates. These prevent the heads from being driven into the
spindle or off of the disk surface.
2.1.4 Headstack Assembly
The headstack assembly consists of the read/write heads, spacers,
flex circuit, and rotary positioner assembly. The head arms and rotary
positioner assembly balance each other so that the mass center of the
entire stack is at the center of the mounting hub. The heads are
mini-composite slider-type heads, mounted to Whitney-style spring
steel flexures. The heads and actuator are connected by the flex
circuit, which contains a read preamplifier/write driver chip.
2.1.5
Automatic Actuator Lock (AIRLOCK)
AIRLOCK is a mechanical means of locking the heads tack in the landing
zone, and is covered by u.s. Patents and pending patent applications.
The dedicated landing zone for the heads ensures data integrity and
prevents damage during shipment. When dc power is removed from the
motor, an electronic return spring extracts energy from the spinning
motor and pulls the headstack into the landing zone. AIRLOCK latches
it in place. As dc power is applied to the motor and the disk stack
starts spinning, airflow increases, and the airvane on AIRLOCK
rotates, releasing the headstack.
2.1.6 DC Drive Motor
To achieve accurate speed control with minimum electromagnetic
interference, the Q250/Q280 uses a brushless dc spindle motor in a
closed-loop digital servo system, synchronized by a 2 MHz clock. The
motor is dynamically balanced, four pole, three phase, and rotates at
3662 rpm. A 12 V motor control IC commutates the motor coils in
2-2

accordance with signals from three Hall-effect devices mounted at 120
degrees around the motor. The IC also limits the motor current on
start up and produces dynamic braking to stop the motor quickly.
contaminants are kept out of the drive by mounting the motor inside a
heavy aluminum housing, bolted to the base casting. Two conductive
ferro-fluid magnetic seals prevent outside air from entering the drive
through the bearing core or along the bearing shaft. Motor components
are processed and coated to eliminate dust, chips, and oxides, and
final assembly is in a Class 100 clean room environment. EMI (Elec-
tromagnetic Interference) and electrostatic discharge (ESD) are
reduced by grounding the rotating shaft with a brush of conductive
teflon.
2.1.7 Air Filtration
The Q250 and Q280 are Winchester drives with a nominal flying height
of 11 microinches .
.3 MICRON CIRCULATION
FILTER
Figure 2-2: Inside View of Drive, Showing Air Filtration
2-3

To keep the air circulating within the drive free of particles, the
drives are assembled in a Class 100 clean room environment, and then
sealed with a metal cover. During the life of the drive, the rotating
disks pump the enclosed air through an internal 0.3 micron recircula-
tion filter, as shown in Figure 2-2. Another 0.3 micron filter, not
shown, allows outside air into the sealed area of the drive to
equalize internal and external pressures.
2.2 Drive Electronics
2.2.1 Disk Format
Q200 Series drives employ 823 user tracks (refer to Figure 2-3), while
seven tracks are reserved for disk drive system uses -- such as defect
lists, serial number ID and factory test data. Each data track con-
tains thirty-two sectors and thirty-two servo wedges. Each user data
area consists of a preamble and synchronization area, 512 bytes of
data, and 12 bytes of ECC. A short postamble flushes the ECC buffers
in DICEY.
within the servo wedges are the servo tracks--three times as many as
the data tracks--written in staggered sequence so they don't overlap
on the disk. In a wedge, a servo track starts with a unique qual area
that identifies the area as a wedge, and ends with a servo burst. As
with the data areas, each burst begins with a preamble and synchroni-
zation area. In the bursts, this is followed by the servo track num-
ber, the head number (bursts A and C) or the sector number (bursts B
and D), a checksum that allows error detection, and a short postamble.
At 3662 rpm, a complete sector, including wedge and 512-byte data
area, passes under its head in 512 microseconds. The data itself
passes under the head in about 410 microseconds, giving a maximum user
data transfer rate of about 10 M bits/sec, i.e., 1.25 MBytes/sec.
2.2.2 Simplified Explanation--Block Diagram
This section summarizes the operation of the drive, as an introduction
to the more detailed sections that follow. Refer to Figure 2-4, a
simplified block diagram of the system.
2-4

TRACKS
QUAL.
AREA
50us
PRE
AMBLE
'-
'-
SERVO
TRACKS
I /
-~~~-j
+ 10i
/
/
TO
CENTER
OF DISK
1
SERVO & DATA
TRACK
LAYOUT
----T----- -
STo~A~
/
/
/
/ 105
c=J [
/ 104
/
/
rr---w...---I--<- /
'-'-
'-
S
Y
N
C
/ 103
/
PRE
AMB
LE
~ I e
'-
'-'-'-'-
TRACK
NO.
\
102
101
S
Y
N
C
'-'-
'-'-
'-
P
0
S
'-
T
DATA
512 BYTES
452us
DETAIL
OF A BURST
E
C
C
~
CHECKSUM
{
HEAD NO. (BURSTS A&C)
SECTOR NO. (BURSTS B&D)
P
0
S
T
[
LOGICAL~
TRACK NO.5
DETAIL
OF
ONE SECTOR
12 BYTES
Figure 2-3: Disk Format: Wedges, Sectors, and Tracks
2-5

Power-On
Voltages may be applied in any sequence. When the dc voltages are
low, as when the power has failed or has just been applied, the power-
on-reset (PaR) circuit resets the major circuits and keeps them reset
until the voltages are high enough and stable.
At initial power-on, the drive is recalibrated: the actuator seeks to
the inner, outer, and middle tracks; at each location, servo-burst
amplitude measurements are made and from these the microprocessor
calculates and stores adaptive gain parameters that are later used to
optimize seek and settle times.
-------,
I
-------,
HEAD
DISK
ASM
(HDA)
R/W
HEADS
PRE-AMP
WRITE
DRIVER
I
I
I
______ ...J
ELECTRONIC
RETURN
SPRING
UB
2MHz
RESET uP
OTHER CIRCUIT
ALE. -WR. -RD
*64KB WITH DISCACHE
Figure 2-4: Electronics Block Diagram
2-6
+12V
+5V
50BO
12MHz
SCSI
BUS
TO
HOST

Architecture
A standard 8-bit microprocessor operated at 12 MHz controls each Q200
Series drive. An 8031 is used for drives without DisCache, an 8032
for drives with it. Firmware is in a plug-in 32 K X 8 EPROM. Dif-
ferent EPROMS are used for the Q250 and Q280, and for drives with and
without DisCache. Special EPROMs may be used for custom applications.
communication between the major circuit components is over the 8-bit
MAD (multiplexed address/data) bus. DICEY, a proprietary data-
controller IC, manages access to the buffer, which is 16 KBytes of
dynamic RAM (64 KBytes for drives with DisCache). The upper 2 KBytes
of RAM (4 KBytes with DisCache) is reserved for Q250/Q280 use. DICEY
is the DMA controller, performs serial to parallel and parallel to
serial conversions, handles all RLL encoding and decoding, and
generates the ECC syndrome.
SCSI Bus Operations
Communications with the host and other SCSI devices is over the SCSI
bus. The interface is implemented with a 5080 SCSI Controller IC that
can play the role of initiator or target, and performs disconnect/
reconnect and arbitration functions.
Before the disk is written to, a full sector of incoming SCSI data is
accumulated in buffer RAM (via DMA transfers). As the disk is being
read from, data is also stored in RAM. After a full sector is read,
the data is checked with the error-correcting code (at the user's
option), transferred through the 5080 via DMA, then on to the SCSI
bus. Users can select the action to be taken in the event that an
error is detected, via the MODE SELECT command.
Servo
While track-following, track and sector numbers of the current posi-
tion are stored in buffer RAM--the microprocessor knows the exact head
position at all times. When a READ or WRITE command arrives, the
microprocessor immediately starts a seek by commanding the head posi-
tion DAC (digital-to-analog converter) via the MAD bus. The DAC
output is converted to a high current, which drives the actuator.
New track and sector numbers are read on the fly from the servo
bursts, forming a closed loop. The microprocessor accelerates, then
decelerates, the actuator via the head position DAC to achieve the
seek in the shortest time.
As servo bursts pass under the head, their amplitudes are measured by
the AMC (amplitude measurement circuit), and placed on the MAD bus by
the servo ADC (analog-to-digital converter). When seeking, the micro-
processor reads head position from the burst with the highest ampli-
tude, if possible. Once the head is on track, the microprocessor
2-7

keeps the head following the track exactly, by adjusting the head
position so that the amplitudes of the two servo bursts written on
each side of the data track are equal. For example, in Figure 2-3,
bursts A and D on logical track a are kept equal.
There is one head for each surface: four on the Q250, six on the Q280.
Each head can either read or write. When reading, the output is
amplified first by the preamplifier chip in the HDA, then by an AGC
(automatic-gain-control) amplifier. That output is filtered, then
differentiated to find the zero crossings, and converted to pulses by
a pulse detector. A phase-locked loop circuit derives synchronized
data and clock signals for DICEY. Careful design makes drop-ins or
drop-outs rare. RLL 1,7 encoding allows 1.33 data bits to be stored
for every magnetic transition on the disk.
write
The preamplifier/write driver chip inside the HDA selects the head
(under command of the microprocessor) and sends current reversals to
the head, which writes magnetic transitions on the disk.
2.2.3
SCSI Bus Physical Interface
A 50-pin connector is provided at position J1 on the PCB for con-
necting to the standard SCSI bus. See Figures 2-5 and 2-9. The
standard SCSI single-ended non-shielded connector is used. J1 is a
Universal Header connector and has a key slot to prevent installing
the mating connector improperly. The recommended mating connector is
AMP receptacle PIN 1-499508-2 (with strain relief) or PIN 1-746195-2
(without strain relief), or equivalent. Unkeyed mating connectors
should not be used due to the danger of plugging the connector in
backwards.
A 50-conductor flat cable or a 25-signal twisted-pair ribbon cable
with a minimum conductor size of 28 AWG and a characteristic impedance
of 100 ohms +/- 10% is recommended. SCSI devices are daisy-chained
together using a common cable. To minimize discontinuities and signal
reflections, cables of different impedances should not be used in the
same bus. Table 2-1 gives J1 pin assignments. Note that to achieve
satisfactory transmission quality, all odd pins except pin 25 are
connected to ground; pin 25 is left open. Maximum total cable length
is 20 feet (6 meters), a length suitable for use in a cabinet.
2-8

Ground
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
CENTER KEY SLOT
DDDDDDDDDDDDDDDCCCCCCCCCC
DOCOCDOCCCCCCDCCCCCCCCCCC
CONNECTOR PCB
POSITION #1 INDICATOR
Figure 2-5:
Jl Connector
Table
2-1: Jl
Pin Assignments
Signal
Name
2
-Data
Bit
0 (-DBO)
4 -Data Bit
1
(-DBl)
6
-Data
Bit 2
(-DB2)
8
-Data Bit
3
(-DB3)
10
-Data Bit
4
(-DB4)
12 -Data Bit 5
(-DB5)
14 -Data Bit 6
(-DB6)
16
-Data Bit
7
(-DB7)
18
-Data Bit
P
(-DBP)
20
Ground
22 Ground
24 Ground
Open
26
Terminator Power
(TERMPWR)
28
Ground
30
Ground
32
-ATN
34
Ground
36
-BSY
38
-ACK
40
-RST
42
-MSG
44
-SEL
46
-C/D
48
-REQ
50
-I/O
2-9

2.2.4 SCSI Bus Signal Descriptions
All signals are true low and use open collector drivers (see Figure
2-6 for a typical circuit). A termination is required at each
physical end of the bus. Three resistor networks in sockets are
provided as terminators. Drives are shipped from the factory with
the terminators plugged in. See Figure 2-9 for locations on the PCB.
5'1
CAUTION
Only the two devices at the physical ends of the SCSI bus
are allowed to have terminators: remove terminators from
all other devices on the bus (unplug all three terminator
packages). If the additional terminators are not removed,
the bus drivers may be damaged because they will sink more
current from the +5 V supply than the 48 rnA they are rated
to carry.
CAUTION
Plug-in terminator packages are polarized, and must be
plugged in correctly. On each package, pin 1 is marked
with a dark band, and must face the "1" that is screened on
the PCB. All terminators face the same way. If in doubt
about the correct orientation, consult Figure 2-9.
TERMPWR (PIN26)
r--------- __ ~~---- __ ~--------------~--~------~--------~
5V
-SIGNAL
~----~----~--------~---------------+--~------4---~------1
GROUND
~----~----~--~----~---------------r----------T---~----~
DEVICE
WITH
TERMINATOR
"----------.. -------)
V
DEVICES WITHOUT TERMINATORS
DEVICE
WITH
TERMINATOR
Figure 2-6: SCSI Bus. Typical Circuit of a Signal Line
2-10
5V

Each Q250/Q280 bus driver has the following output characteristics:
True (Signal Asserted) = 0.0 to 0.4 V dc at 48 mAo
False (Signal Non-Asserted) = 2.5 to 5.25 V dc.
Each signal received by the Q250 or Q280 must have the following input
characteristics:
True (Signal Asserted) = 0.0 to 0.8 V dc.
Maximum total input load = -0.4 mA at 0.4 V dc.
False (Signal Non-Asserted) = 2.0 to 5.25 V dc.
Minimum input hysteresis = 0.2 V dc.
SCSI Bus Signals
Up to eight devices can be supported on the SCSI bus, but communica-
tion is allowed between only two SCSI devices at any given time.
Information transfers on the SCSI DATA BUS are asynchronous and fol-
low a defined -REQ/-ACK (request/acknowledge) handshake protocol. One
byte of information can be transferred with each handshake. There are
a total of 18 logic signals: nine control signals and nine signals
that comprise an 8-bit DATA BUS with parity. Each of the signals is
described briefly below.
-BSY (BUSY). An "oR-tied" signal that indicates that the bus is being
used.
-SEL (SELECT). A signal used by an initiator to select a target or by
a target to reselect an initiator.
-C/D (CONTROL/DATA). A signal driven by a target that indicates
whether CONTROL or DATA information is on the DATA BUS. Assertion
indicates CONTROL.
-I/O (INPUT/OUTPUT). A signal driven by a target that controls the
direction of data movement on the DATA BUS with respect to an ini-
tiator. Assertion indicates input to the initiator. This signal is
also used to distinguish between SELECTION and RESELECTION phases.
-MSG (MESSAGE). A signal driven by a target during the MESSAGE phase.
-REQ (REQUEST). A signal driven by a target to indicate a request for
a -REQ/-ACK data transfer handshake.
-ACK (ACKNOWLEDGE). A signal driven by an initiator to indicate an
acknowledgement for a -REQ/-ACK data transfer handshake.
2-11