Quatech MPA-100 User manual

MPA-100
RS-232 SYNCHRONOUS
ADAPTER CARD
User's Manual
QUATECH, INC. TEL: [phone]
5675 Hudson Industrial Parkway FAX: [phone]
Hudson, Ohio 44236 http://www.quatech.com
INTERFACE CARDS FOR IBM PC/AT AND PS/2

Warranty Information
Quatech Inc. warrants the MPA-100 to be free of defects for
one (1) year from the date of purchase. Quatech Inc. will repair or replace any adapter that
fails to perform under normal operating conditions and in accordance with the procedures
outlined in this document during the warranty period. Any damage that results from improper
installation, operation, or general misuse voids all warranty rights.
The authors have taken due care in the preparation of this document and any associated software
program(s). In no event will Quatech Inc. be liable for damages of any kind, incidental or
consequential, in regard to or arising out of the performance or form of the materials presented
herein and in the program(s) accompanying this document. No representation is made regarding
the suitability of this product for any particular purpose.
Quatech Inc. reserves the right to edit or append to this document or the product(s) to which it
refers at any time and without notice.
Please complete the following information and retain for your records. Have this information
available when requesting warranty service.
Serial Number:
Communication ISA Adapter
Single Channel RS-232 SynchronousProduct Description:
MPA-100
Model Number:
Date of purchase:
MPA-100 User's Manual i

The information contained in this document cannot be reproduced in any form without the
written consent of Quatech, Inc. Likewise, any software programs that might accompany this
document can be used only in accordance with any license agreement(s) between the purchaser
and Quatech, Inc. Quatech, Inc. reserves the right to change this documentation or the product to
which it refers at any time and without notice.
The authors have taken due care in the preparation of this document and every attempt has been
made to ensure its accuracy and completeness. In no event will Quatech, Inc. be liable for
damages of any kind, incidental or consequential, in regard to or arising out of the performance
or form of the materials presented in this document or any software programs that might
accompany this document.
Quatech, Inc. encourages feedback about this document. Please send any written comments to
the Technical Support department at the address listed on the cover page of this document.
Copyright ©2004 by
Quatech Inc.
5675 Hudson Industrial Parkway
Hudson, Ohio 44236
All rights reserved. Printed in the USA
Trademarks:
Quatech,, and Syncdrive are trademarks of Quatech Inc. Other product and company names are
registered trademarks or trademarks of their respective holders.
MPA-100 User's Manual ii

Table of Contents
13-1
13. SPECIFICATIONS ............................................... .
12-1
12. DEFINITION OF INTERFACE SIGNALS ........................ .
11-6
11. EXTERNAL CONNECTIONS .................................... .
10-3
10.2 DCE Configuration ........................................... .
10-2
10.1 DTE Configuration ........................................... .
10-1
10. DTE/DCE CONFIGURATION ................................... .
9-1
9. COMMUNICATIONS REGISTER ................................ ..
8-1
8. CONFIGURATION REGISTER ................................... ..
7-1
7. DIRECT MEMORY ACCESS ..................................... ..
7-6
6.3 SCC Data Encoding Methods .................................... ..
6-5
6.2 Baud Rate Generator Programming .............................. ..
6-2
6.1 Accessing the Registers ......................................... ..
6-1
6. SCC GENERAL INFORMATION ................................. ..
6-4
5.6 SYNCA to RLEN Control - J7 ................................... ..
5-3
5.5 Receive DMA Selection - J9 ..................................... ..
5-3
5.4 Transmit DMA Selection - J8 .................................... ..
5-2
5.3 Interrupt Level Selection - J5 & J6 ............................... ..
5-1
5.2 Interrupt Sharing Configuration - J4 ............................. ..
5-1
5.1 DTE/DCE Configuration - J2, J11, & J12 ......................... ..
5-1
5. JUMPER CONFIGURATIONS ................................... ..
4-2
4.1 Using Terminal Count to Generate Interrupts ...................... ..
4-1
4. INTERRUPTS .................................................... ..
3-1
3. ADDRESSING .................................................... ..
2-1
2. HARDWARE INSTALLATION ................................... ..
1-1
1. INTRODUCTION ................................................ ..
MPA-100 User's Manual iii

MPA-100 User's Manual iv

1. INTRODUCTION
The Quatech MPA-100 is a single channel, synchronous RS-232 compatible serial
communication port for systems utilizing the architecture of the IBM AT personal computer or
compatible. Figure 1 depicts the layout of the MPA-100.
Figure 1 MPA-100 Board Layout
Quatech, Inc.
MPA-100
U1
U2
SW1 SW2
U3
U4
U5
U6
U7
U8
X1 U16 U9
U10
U11
U12
U13
U14
U15
U20
U17
U18
U19
U23
U22
U21
J8
J9
J5 J6
J4
J2
CN1
J7
U29
U28
J12
J11
The MPA-100 occupies an 8 byte block of I/O address space which may be located
anywhere within the available I/O address space in the system.
Communication on the MPA-100 is controlled by a serial communications controller,
hereafter referred to as the SCC (U17). The MPA-100 is compatible with several different types
of SCC, all of which can support asynchronous formats, byte-oriented protocols such as IBM
Bisync, and bit-oriented protocols such as HDLC and SDLC. The SCCs also offer internal
functions such as on-chip baud rate generators, and digital phase-lock loops (DPLL).
The MPA-100 also supports Direct Memory Access (DMA) and interrupts. DMA
channels 1 - 3 can be used for high data transfer rates. Interrupt levels 2-7, 10-12, and 14-15 are
available.
MPA-100 User's Manual 1-1

MPA-100 User's Manual 1-2

2. HARDWARE INSTALLATION
If the default address and interrupt settings are sufficient, the MPA-100 can be quickly
installed and put to use. The factory default settings are listed below in Table 1.
Table 1 Default Resource Settings
DMA/DRQ 1DMA/DRQ 3IRQ 5300 hex
RxDMATxDMAInterruptAddress
1. If the default settings are correct, skip to step 2, otherwise refer to chapters 3, 4, and
7 for detailed information on how to set the address, IRQ, and DMA levels.
2. Turn off the power of the computer system in which the MPA-100 is to be installed.
3. Remove the system cover according to the instructions provided by the computer
manufacturer.
4. Install the MPA-100 in any vacant expansion slot. The board should be secured by
installing the Option Retaining Bracket (ORB) screw.
5. Replace the system cover according to the instructions provided by the computer
manufacturer.
6. Attach and secure the cable connectors to the desired equipment.
MPA-100 User's Manual 2-1

MPA-100 User's Manual 2-2

3. ADDRESSING
The MPA-100 occupies a continuous 8 byte block of I/O addresses. For example, if the
base address is set to 300H, then the MPA-100 will occupy address locations 300H-307H. The
base address of the MPA-100 may be set to any of the first 64 Kbytes (0 - FFFFH) of available
I/O address space through the settings of dip switches SW1 and SW2. SW1 allows the user to
select the higher address signals A15 - A8. SW2 allows the user to select the lower address
signals A7 - A3. The sixth position of SW2 is not used and can be ignored. Figure 2 shows some
examples of different base addresses.
Figure 2 Address switch selection examples
ON
ON
ON
ON
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
1
1
2
2
3
3
4
4
5
5
6
6
Base Address = 300H
Base Address = 3F8H
SW1
SW2
SW1
SW2
A15
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4 A3
NOT USED
A15
A14 A13 A12
A11
A10
A9
A8
A7
A6
A5
A4 A3
NOT USED
A14
MPA-100 User's Manual 3-1

The first four bytes, Base+0 through Base+3, of address space on the MPA-100 contain
the internal registers of the SCC. The next two locations Base+4 and Base+5 contain the
Communications Register and the Configuration Register. The last two address port locations
are reserved for future use. The entire address range of the MPA-100 is shown in Table 2.
Table 2 MPA-100 Address Assignments
ReservedBase + 7
ReservedBase + 6
Configuration RegisterBase + 5
Communications RegisterBase + 4
SCC Control Port, Channel BBase + 3
SCC Data Port, Channel BBase + 2
SCC Control Port, Channel ABase + 1
SCC Data Port, Channel ABase + 0
Register DescriptionAddress
Information on the internal registers of the SCC can be found in Section 6. The two
onboard registers give the user additional options pertaining to DMA, interrupts and the
RS-232-D standard for communication. Information on the Configuration Register and the
Communications Register can be found in Section 8, and Section 9.
MPA-100 User's Manual 3-2

4. INTERRUPTS
The MPA-100 supports eleven interrupt levels: IRQ2 -7, IRQ10 - 12, and IRQ14 - 15,
and selects which interrupt level is in use through jumper packs J5 and J6. The MPA-100 has
three interrupt sources: interrupt on terminal count, interrupt on test mode, and interrupt from the
SCC. The interrupt source is selected by bits D4 and D5 of the Configuration Register, see
Section 8 for details. Interrupts from the SCC can occur on a number of conditions, depending on
the configuration of the SCC’s internal register. The sources include interrupt on next character
received, interrupt on all characters received, interrupt on special condition, interrupt on transmit
buffer empty, and interrupt on External/Status (see the SCC Technical Manual for more
details). Jumper block J4 can be selected to provide for interrupt sharing on the MPA-100.
When using interrupts with the MPA-100, it is required that the application program have
an interrupt service routine (ISR). There are several things that an ISR must do to allow proper
system operation:
1. Do a software interrupt acknowledge to the SCC. This is accomplished by reading
the interrupt vector register, read register 2, in channel B of the SCC. The value
supplied by this read can also be used to vector to the appropriate part of the ISR.
2. Service the interrupt ( read the receiver buffer, write to the transmit buffer, etc.).
3. Write a Reset Highest Interrupt Under Service (IUS) command to the SCC. This is
done by writing a 0x38 to write register 0.
4. Check for any additional interrupts pending in the SCC and service them.
5. For applications running under DOS, a nonspecific End of Interrupt must be
submitted to the interrupt controller. For Interrupts 2-7 this is done by writing a 0x20
to port 0x20. For Interrupts 10-12,14 and 15 this is done by writing a 0x20 to 0x60,
then a 0x20 to 0x20 (Due to the interrupt controllers being cascaded). Note that this
should only be done if it is a requirement of the operating system being used.
For further information on these subjects or any others involving the SCC contact the
manufacturer of the SCC being used for a complete technical manual.
MPA-100 User's Manual 4-1

4.1 Using Terminal Count to Generate Interrupts
The MPA-100 allows the option of generating an interrupt whenever the Terminal Count
(TC) signal is asserted. Terminal Count is an indicator generated by the system’s DMA
controller, which signals that the number of transfers programed into the DMA controller’s
transfer register have occurred. This board feature only works when the interrupt sharing feature
is selected on jumper J4.
MPA-100 User's Manual 4-2

5. JUMPER CONFIGURATIONS
The MPA-100 utilizes various jumper blocks which allow the user to customize their
hardware configuration. The following sections explain the function and setting of each of the
jumper blocks on the MPA-100.
5.1 DTE/DCE Configuration - J2, J11, & J12
The jumper packs J2, J11, and J12 control the DTE/DCE configuration of the MPA-100.
J2 determines the board setting (DTE or DCE) while the jumper packs J11 and J12 control the
routing of the signals to the DB-25 connector. All three jumper packs must be set exclusively to
either DTE or DCE for correct operation of the MPA-100.
Table 3 DTE/DCE Jumper Selections
1-2, 3-4, 5-6, 7-81-5, 2-6, 3-7, 4-8J12
1-2, 3-4, 5-6, 7-8, 9-10, 11-12,
13-14, 15-16
1-9, 2-10, 3-11, 4-12, 5-13,
6-14, 7-15, 8-16
J11
no connection1-2J2
DCE
DTE (Default)
J11 and J12 may be configured for DTE by setting all jumpers vertical on the board and for DCE
by setting all jumpers horizontal on the board.
5.2 Interrupt Sharing Configuration - J4
J4 is a three pin jumper which determines the configuration for the interrupts. By
selecting pins 1 & 2, the user has the ability to share interrupts with other Quatech adapter cards.
The MPA-100 will drive the interrupt onto the bus only when an interrupt occurs. Otherwise, the
output is high impedance. If pins 2 & 3 of J4 are selected, then interrupts abide by the IBM
specification and cannot be shared. Table 4 summarizes the jumper block selections for J4.
Table 4 Jumper Block J4 Selections
2-3No Interrupt sharing
1-2
Interrupt Sharing (Default)
PinsInterrupt Function
MPA-100 User's Manual 5-1

5.3 Interrupt Level Selection - J5 & J6
Jumper blocks J5 and J6 select the interrupt level that the MPA-100 utilizes. Interrupt
levels IRQ2 - IRQ7 reside on J5, while interrupt levels IRQ10 - IRQ12 and IRQ14 - IRQ15
reside on J6. Table 5 and Table 6 summarize the jumper block selections for J5 and J6. The
IRQ levels are also marked on the MPA-100 silkscreen for easy identification.
Table 5 Jumper block J5 selections.
6-12IRQ7
5-11IRQ6
4-10
IRQ5 (Default)
3-9IRQ4
2-8IRQ3
1-7IRQ2(9)
PinsInterrupt Level
Table 6 Jumper block J6 selections.
5-10IRQ15
4-9IRQ14
3-8IRQ12
2-7IRQ11
1-6IRQ10
PinsInterrupt Level
MPA-100 User's Manual 5-2

5.4 Transmit DMA Selection - J8
J8 Selects the DMA channel to be used for Transmit DMA. Three channels (1 - 3) are
available on the MPA-100 for DMA. When selecting a DMA channel, both the DMA
acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be
selected. Table 7 summarizes the jumper block selections for J8.
Table 7 Jumper block J8 selections.
6-12
5-11
Channel 3 (Default)
4-10
3-9Channel 2
2-8
1-7Channel 1
PinsDMA Channel
5.5 Receive DMA Selection - J9
J9 selects the DMA channel to be used for Receive DMA. Three channels (1 - 3) are
available on the MPA-100 for DMA. When selecting a DMA channel, both the DMA
acknowledge (DACK) and the DMA request (DRQ) for the appropriate channel need to be
selected. Table 8 summarizes the jumper block selections for J9.
Table 8 Jumper block J9 selections.
6-12
5-11Channel 3
4-10
3-9Channel 2
2-8
1-7
Channel 1 (Default)
PinsDMA Channel
MPA-100 User's Manual 5-3

NOTE:
Since it is illegal to perform DMA on transmit and receive on the
same DMA channel, jumper blocks J7 and J8 should never have the
same pins connected. This could result in damage to the system.
5.6 SYNCA to RLEN Control - J7
J7 controls the signal path from the RLEN bit in the Communications Register to the
SYNCA input to the SCC. If J7 is installed and the SCC is in external SYNC mode, setting the
RLEN bit high will assert the SYNCA pin. Note: the RLEN output is still affected when used to
control the SYNCA pin.
Table 9 Jumper J7 Selections
no connections
RLEN (Default)
1-2SYNCA
Jumper J1Function
MPA-100 User's Manual 5-4

6. SCC GENERAL INFORMATION
The Serial Communications Controller (SCC) is a dual channel, multi-protocol data
communications peripheral. The MPA-100 provides a single channel for communications,
however, to provide full DMA capabilities with complete modem control line support, both
channels of the SCC can be utilized. The SCC can be software configured to satisfy a wide
variety of serial communications applications. Some of its protocol capabilities include:
1) Asynchronous Communications
5, 6, 7, or 8 bits per character
1, 1-1/2, or 2 stop bits
Odd, even, or no parity
Times 1, 16, 32, or 64 x clock modes
Break generation and detection
Parity, overrun and framing error detection
2) Byte-oriented Synchronous Communications
Internal/external character synchronization
1 or 2 sync characters in separate registers
Automatic Cyclic Redundancy Check (CRC) generation/detection
3) SDLC/HDLC (Bit Synchronous) Communications
Abort sequence generation and checking
Automatic zero insertion and deletion
Automatic flag insertion between messages
Address field recognition
I-field residue handling
CRC generation and detection
SDLC loop mode with EOP recognition/loop entry and exit
4) NRZ, NRZI, or FM encoding/decoding
MPA-100 User's Manual 6-1

6.1 Accessing the Registers
The mode of communication desired is established and monitored through the bit values
of the internal read and write registers. The register set of the SCC includes 16 write registers and
9 read registers. These registers only occupy four address locations, which start at the MPA-100's
physical base address that is configured via the on board switches. This and all other addresses
are referenced from this base address in the form Base + Offset. An example of this is Base + 1
for the SCC Control Port, Channel A.
There are two register locations per SCC channel, a data port and a control port .
Accessing the internal SCC registers is a two step process that requires loading a register
pointer to perform the addressing to the correct data register. The first step is to write to the
control port the operation and address for the appropriate channel. The second step is to either
read data from or write data to the control port. The only exception to this rule is when accessing
the transmit and receive data buffers. These registers can be accessed with the two step process
described or with a single read or write to the data port. The following examples illustrate how
to access the internal registers of the SCC. Also, Table 10 describes the read registers and
Table 11 describes the write registers for each channel.
The MPA-100 has been designed to assure that all back to back access timing
requirements of the SCC are met without the need for any software timing control. The standard
of adding jmp $+2 between IO port accesses is not required when accessing the MPA-100.
Example 1: Enabling the transmitter on channel A.
mov dx,base ; load base address
add dx,ContA ; add control reg A offset (1)
mov al,05H ; write the register number
out dx,al
mov al,08H ; write data to the register
out dx,al
MPA-100 User's Manual 6-2