Renesas CLK-104a User manual

Manual
CLK
-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Page 1
© 2021 Renesas Electronics
Renesas collaborated with Xilinx to design a version of the CLK-104 board to work with Xilinx’s platform for
RFSoC solutions. The CLK-104 board uses an RF-PLL device to provide a reference for up to 12 RF clocks,
including one for an onboard RF-synthesizer device, and the 8V97003 as a reference clock to generate two
output clocks up to 18GHz for ADC/DAC applications. Two versions of the CLK-104 boards are available: the
CLK-104a uses an RF-PLL device with the 8V19N491-24, and the CLK-104b uses the 8V19N882. The rest of
the design is identical for both versions.
The CLK-104 is designed as a plug-in module to the Xilinx ZCU-1275 (16×16) platform. By plugging in to the
mainboard socket, the CLK-104 acquires power supplies, an I2C/SPI interface, and input reference clocks. The
following figure shows the bottom of the CLK-104 board with a male connector to match with ZCU-1275 board.
For information on how to operate and access the CLK-104 board, see the ZCU-1275 User Manual.
Figure 1. Back of CLK-104 Board with Mating Connector with Xilinx ZCU-1275
The CLK-104 board is designed to function as a standalone testing platform. For more information, see the
following sections.
Contents
1. System Overview........................................................................................................................................... 2
2. Standalone Testing........................................................................................................................................ 3
2.1 Power Supply......................................................................................................................................... 3
3. SPI Interface................................................................................................................................................... 3
4. Input Reference Selection............................................................................................................................. 4
5. Using Timing Commander to Program the Devices .................................................................................. 5
6. Output Clock Monitoring/Measurement ...................................................................................................... 5
6.1 Example 1: Phase Noise Plot from J12/J13 (122.88MHz).................................................................... 6
6.2 Example 2: Phase Noise Plot from 8V97003 #1 (1GHz)....................................................................... 6
7. Board Schematics ......................................................................................................................................... 7
8. Revision History ............................................................................................................................................ 7

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Page 2
1. System Overview
The CLK-104 board consists an RF-PLL device (8V19N491-24 or 8V19N882) and two RF-synthesizer devices
(2x 8V97003). RF-PLL device can take one of the following three reference clocks as inputs to its CLK0/nCLK0
and CLK1/nCLK1 (both are differential inputs):
■156.25MHz from Xilinx RFSoC (ZCU-1275) board through above-mentioned connector
■An onboard 10MHz TCXO
■An external clock connected to SMA connectors
The RF-PLL devices generate the following output clocks:
■A differential output for RF-synthesizer #1
■A differential output for RF-synthesizer #1
■A differential output for RF-synthesizer #2
■A differential output to a pair of onboard SMA connectors for monitoring
■6 differential outputs connecting to ZCU-1275 board (through the connector)
A diagram of the CLK-104 board is displayed below.
Figure 2. CLK-104 Board Diagram
The RF-PLL device and two RF-synthesizer devices are accessible by an SPI interface. As stated above, they
can be accessed by an I2C-to-SPI converter from/to the ZCU-1275 board. The I2C signals are within the mating
connector between the two boards. Please note that the SPI port has been connected to an onboard 5×2 header
by which an external SPI master can access all devices on CLK-104 board.
The CLK-104 board can be powered locally or by plugging it into the ZCU-1275. For more information, see
“Standalone Testing.”

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Page 3
2. Standalone Testing
If a Xilinx ZCU-1275 board is not available, the CLK-104 board can be tested standalone. Please complete the
following steps and information below to conduct a standalone test or evaluation.
2.1 Power Supply
The connector between the CLK-104 and ZCU-1275 contains +5V, +3.3V, and ground pins that provide power
supplies to the CLK-104 board when plugged in. Copper pads are available on the CLK-104 board to facilitate
the power supplies coming from a bench power supply. Solder a thick wire on these pads and connect +5V,
+3.3V, and GND to a bench power supply. For the locations of these copper pads, see the following figure.
Figure 3. +5V, +3.3V, and GND Copper Pads are Provided for Local Power Supplies
3. SPI Interface
A 5×2 header is installed to make connections between an external SPI master to the devices on the CLK-104
board. Use an FTDI dangle (C232HM) to connect the SCLK, SDI, SDO, and nCS signals as labelled in the
header below. Please note, jump J4, J5, or J6 one at a time to access one of three devices on the board.
Figure 4. SPI Header for Connecting to 8V19N491-24 or 2x 8V19N882 One at a Time

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Page 4
4. Input Reference Selection
A 4-bit dip-switch (J11) is used to select one of three available reference clocks for the two input clocks of the
RF-PLL (8V19N491-24 or 8V19N882). Two mux devices are used so the two input clocks going to the RF-PLL
device can be selected individually. Please see Dipswitch selection pin allocation below.
Figure 5. Dip-Switch to Individually Select an Input Reference for CLK0/nCLK0 and CLK1/nCLK1
Follow onboard silkscreen labels for “H” or “L” position (see Figure 5) for the Dipswitch (J11) pins. The reference
selection table is as follows.
Table 1. Reference Selections for RF_PLL Inputs (CLK0/nCLK0 and CLK1/nCLK1)
Destination
CLK0_SEL0 Pin
CLK0_SEL1 Pin
Reference Selected
CLK0_P/N
H
H
X
H
L
SMA_IN
L
H
TCXO_IN
L
L
SFP_RCV_CK_P/N
CLK1_SEL0 Pin
CLK1_SEL1 Pin
CLK1_P/N
H
H
SFP_RCV_CK_P/N
H
L
TCXO_IN
L
H
SMA_IN
L
L
X

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Page 5
5. Using Timing Commander to Program the Devices
For ease of use, Renesas’ free-of-charge software tool – Timing Commander is recommended to configure and
program the CLK-104 board/devices (8V19N491-24, 8V19N882, and 8V97003). If you have any questions on
the Timing Commander software download or TCP/TCS files, please contact IDT-Support-
[email protected]s.com.
In the Timing Commander GUI, when the settings file (.tcs) is loaded:
1. Click on the button in the upper-right corner to display the Connection Settings window.
2. Select USB/SPI in the Connection Settings window.
Figure 6. Connection Setting window to select SPI mode
3. Click the chip symbol button in the upper-right corner of the GUI to initiate the connection to the targeted
device.
6. Output Clock Monitoring/Measurement
The following SMA connector pairs are available to monitor/measure the output frequencies from devices on the
CLK-104 board:
■J15/J16 – 8V97001 #1 Output A
■J14/J17 – 8V97001 #1 Output B
■J19/J20 – 8V97001 #2 Output A
■J18/J21 – 8V97001 #2 Output B
■J12/J13 – 8V19N491-24 Output QREF_A2/nQREF_A2
Other outputs are connected to the connector, and therefore, are not accessible.

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Page 6
6.1 Example 1: Phase Noise Plot from J12/J13 (122.88MHz)
Figure 7. Phase Noise Plot of 122.88MHz Output from 8V19N491-24 QREF_A2/nQREF_A2
6.2 Example 2: Phase Noise Plot from 8V97003 #1 (1GHz)
Figure 8. Phase Noise Plot of 1000MHz Output from 8V97002 #1 ROUT_A/nROUT_A

CLK-104a/b Boards Using Renesas RF-PLL and RF-Synthesizer Solutions Manual
R31UH0011EU0100 Rev.1.00
Nov 26, 2021
Page 7
7. Board Schematics
The board schematics are located at the end of this document.
8. Revision History
Revision
Date
Description
1.00
Nov 26, 2021
Initial release.

5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Jumped to use local SPI header
Silkscreen:
Pin 1 position: #1 Pin 2 position: #2
UTIL_5V0_A
UTIL_5V0_A VCC_3V3
VCC_3V3 UTIL_5V0_A
VIN_5V
VCC_3V3 VCC_DIG_3V3
VCC_DIG_3V3 VCC_DIG_3V3
VCC_DIG_3V3
VCC_DIG_3V3
VCC_DIG_3V3
VCC_DIG_3V3
VCC_DIG_3V3
VCC_DIG_3V3
CS_N492
4 CS_8V97003_2 7
CS_8V97003_1 6
DAC_REFCLK_P 5 DAC_REFCLK_N 5 ADC_REFCLK_P 5 ADC_REFCLK_N 5 PL_CLK_P 5 PL_CLK_N 5 AMS_SYSREF_P 5 PL_SYSREF_P 5
PL_SYSREF_N 5
DDR_PLY_CAP_P 5 AMS_SYSREF_N 5 DDR_PLY_CAP_N 5 SFP_RCV_CLK_P 5 SFP_RCV_CLK_N 5
SDI4,6,7
8V97003_MAXOUT1 6 8V97003_MAXOUT2 7 N492_MAXOUT 4
SYNC_IN 5
SCK 4,6,7
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
311
Tuesday, March 16, 2021
CLK-104
SZ
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
311
Tuesday, March 16, 2021
CLK-104
SZ
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
311
Tuesday, March 16, 2021
CLK-104
SZ
R26 DNP
21
R6 DNP
21
R30 1.00K
21
C11 47uF
1 2
J4
2
1
J5
2
1
R23 DNP
21
R10 10.0K
21
R13
0.00
2
1
J1E
LPAM-20-01.0-L-06-2-K-TR
E1 E1 E2 E2 E3 E3 E4 E4 E5 E5 E6 E6 E7 E7 E8 E8 E9 E9
E10 E10 E11 E11 E12 E12 E13 E13 E14 E14 E15 E15 E16 E16 E17 E17 E18 E18 E19 E19 E20 E20
J1C
LPAM-20-01.0-L-06-2-K-TR
C1 C1 C2 C2 C3 C3 C4 C4 C5 C5 C6 C6 C7 C7 C8 C8 C9 C9
C10 C10 C11 C11 C12 C12 C13 C13 C14 C14 C15 C15 C16 C16 C17 C17 C18 C18 C19 C19 C20 C20
R21 10.0K
21
C12 47uF
1 2
R14 DNP
21
R181 DNP
21
J1A
LPAM-20-01.0-L-06-2-K-TR
A1 A1 A2 A2 A3 A3 A4 A4 A5 A5 A6 A6 A7 A7 A8 A8 A9 A9
A10 A10 A11 A11 A12 A12 A13 A13 A14 A14 A15 A15 A16 A16 A17 A17 A18 A18 A19 A19 A20 A20
R4 10.0K
21
U2
IDTQS3VH253QG8
EA_B_1
1
S1_2
2
YA_7
7
I3B_13 13
S0_14
14
EB_B_15
15
VCC_16
16
I3A_3 3 I2A_4 4 I1A_5 5 I0A_6 6
GND_8 8
YB_9
9I0B_10 10
I1B_11 11 I2B_12 12
R7
DNP
21
FB2 600
21
R27 0.00
2
1
R3 DNP
21
R19 DNP
21
R29 0.00
2
1
C13 1uF
1 2
R17 DNP
21
C5 22uF
12
R25 DNP
21
R8 10.0K
21
R11 0.00
2
1
U1
SC18IS602B
SS0/GPIO0
1
SS1/GPIO1
2
RESET
3
VSS
4
MISO
5
MOSI
6
SDA
7
SCL
8
INT 9
SS2/GPIO2 10
SPICLK 11
VDD 12
SS3/GPIO3 13
A0 14 A1 15 A2 16
R15 DNP
21
C6 47uF
1 2
J1F
LPAM-20-01.0-L-06-2-K-TR
F1 F1 F2 F2 F3 F3 F4 F4 F5 F5 F6 F6 F7 F7 F8 F8 F9 F9
F10 F10 F11 F11 F12 F12 F13 F13 F14 F14 F15 F15 F16 F16 F17 F17 F18 F18 F19 F19 F20 F20
J6
2
1
R31 0.00
2
1
R5 DNP
21
D1 LED Green
A
K
C4 1uF
1 2
R22 10.0K
21
R28 0.00
2
1
C9 1uF
1 2
R24 DNP
21
J1D
LPAM-20-01.0-L-06-2-K-TR
D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D9
D10 D10 D11 D11 D12 D12 D13 D13 D14 D14 D15 D15 D16 D16 D17 D17 D18 D18 D19 D19 D20 D20
R20 10.0K
21
J2
2
1
C2 10uF
1 2
C1 0.1uF
12
C7 47uF
1 2
R9 10.0K
21
J3
3
4
7 12 5
10 9
6 8
R2 DNP
21
C3 0.1uF
12
R12 0.00
2
1
R16 DNP
21
FB1 600
21
R18 DNP
21
C10 22uF
12
C8 1uF
1 2
R1 DNP
21
J1B
LPAM-20-01.0-L-06-2-K-TR
B1 B1 B2 B2 B3 B3 B4 B4 B5 B5 B6 B6 B7 B7 B8 B8 B9 B9
B10 B10 B11 B11 B12 B12 B13 B13 B14 B14 B15 B15 B16 B16 B17 B17 B18 B18 B19 B19 B20 B20
CS_N492
SDI SDO
CLK104_SDA
CS_8V97003_2 CS_8V97003_1
SCK
CLK104_SCL
SYNC_IN
CLK104_SCL CLK104_SDA
SPI_MUX_SEL0 SPI_MUX_SEL1
SPI_MUX_SEL0 SPI_MUX_SEL1
SDO
CS_8V97003_1 CS_8V97003_2
CS_N492
SCK SDI
SDO

5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Silkscreen: LOCK Silkscreen: nINT
Layout note: Place these RC close to the U3 pin 1
Layout note: Place these RC close to the U4 pins
Place the 100-ohm resistor close to Receiver pins
VDD_INP VDD_SPI VDD_LCF VDD_CPF VDD_LCV VDD_SYNC VDD_CPV VDD_VCXO VDD_QCLKA VDD_QCLKB VDD_QCLKC VDD_QCLKD VDD_QCLKE VDD_QCLKV
VDD_QREFA0 VDD_QREFA1 VDD_QREFA2 VDD_QREFB0 VDD_QREFB1 VDD_QREFC VDD_QREFD
VDD_VCXO
VDD_VCXO
CS_N492 3
SCK 3,6,7
SDI 3,6,7
CLK_1
5
nCLK_1
5
CLK_0
5
nCLK_0
5
QREF_A0 6 nQREF_A0 6
QREF_B05
nQREF_B05
QREF_C5
nQREF_C5
QCLK_A0 6 nQCLK_A0 6 QREF_A1 7 nQREF_A1 7 QREF_A2 5 nQREF_A2 5
nQREF_B15
QREF_B15 QCLK_B07
nQCLK_B07
QCLK_C5
nQCLK_C5
QCLK_D
5
nQCLK_D
5
QCLK_E0 5 nQCLK_E0 5
N492_MAXOUT 3
SYNC_IN5
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
411
Thursday, March 18, 2021
CLK-104
SZ
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
411
Thursday, March 18, 2021
CLK-104
SZ
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
411
Thursday, March 18, 2021
CLK-104
SZ
C36 0.1uF
1 2
U3 CVPD-037X-153.6
Cont Volt
1
E/D
2
GND
3OUT 4
Comp Output 5
VCC 6
C25 0.1uF
1 2
R40 0.00
2
1
U4
8V19N491-24
VDD_QCLKB
12
DNU-13
13
VDD_QREFB0
1
QREF_B0
2
nQREF_B0
3
QREF_B1
4
nQREF_B1
5
VDD_QREFB1
6
VDD_QCLKB
7
QCLK_B0
8
nQCLK_B0
9
QCLK_B1
10
nQCLK_B1
11
VDD_QREFC
14
QREF_C
15
nQREF_C
16
VDD_QREFC
17
QCLK_C
20
nQCLK_C
21
VDD_ QCLKC
22
DNU-18
18
VDD_QCLKC
19
DNU-23
23
QREF_D
24
CLD0
36 CR
35 VDD_LCV2
34 CBIAS
33 DNU 32
32 VDD_LCV1
31 VDD_SYNC
30 VDD_QCLKD
29 nQCLK_D
28 QCLK_ D
27 VDD_QREFD
26 nQREF_D
25
nQCLK_E1 48
QCLK_E0 47
nQCLK_E0 46
VDD_QCLKE 45
ICPF
44 VDD_CPF
43 NC 42
42 NC-41
41 VDD_LCF-40
40 VDD_LCF-39
39 LFF
38 LFFR
37
QCLK_E1 49
VDD_QCLKE 50
VDD_QREFA0 51
nQREF_A0 52
QREF_A0 53
nQREF_A1 54
QREF_A1 55
VDD_QREFA1 56
VDD_QCLKA 57
nQCLK_A0 58
QCLK_A0 59
nQCLK_A1 60
QCLK_A1 61
VDD_QCLKA 62
VDD_QREF A2 63
nQREF_A2 64
QREF_A2 65
VDD_QREFA2 66
VDD_INP 67
nCLK_0 68
CLK_0 69
nCLK_1 70
CLK_1 71
RES_CAL 72
LFV 73
VDD_CPV 74
VDD_QCLKV 75
nOSC 76
OSC 77
nQCLK_V 78
QCLK_V 79
VDD_QCLKV 80
LOCK 81
nINT 82
SDAT 83
SELSV 84
SCLK 85
nCS 86
EXT_SYS 87
VDD_SPI 88
EP EP
R45 100
21
C16 1uF
1 2
C22 0.1uF
1 2
C49 33pF
12
C19 1uF
12
C40 0.1uF
1 2
C32 0.1uF
1 2
R37 0.00
2
1
C38 0.1uF
1 2
C26 0.1uF
1 2
C30 0.1uF
1 2
C15 2700pF
12
R33 2.70K
2
1
C45 0.1uF
1 2
J8
Vertical
3 2
1
R41 150
2
1
C28 0.1uF
1 2
C42 0.1uF
1 2
C20 0.1uF
1 2
R43 1.00
2
1
C44 0.01uF
1 2
C41 0.01uF
1 2
C39 0.1uF
1 2
C17 0.1uF
1 2
C50 0.1uF
12
C24 0.1uF
1 2
C14 0.027uF
1 2
C29 0.1uF
1 2
R42 150
2
1
C23 100pF
12
C43 0.1uF
1 2
C35 100pF
12
R44 DNP
21
C33 0.1uF
1 2
C21 0.1uF
1 2
R39 33.0K
2
1
J7
Headerstrip 1X2 SMD
2
1
C27 1uF
12
R32 1.00K
21
C31 0.1uF
1 2
R34 0.00
2
1
C18 0.1uF
1 2
C34 0.01uF
1 2
R38 100
21
R36 5.10K
21
C484.7uF
12
C37 0.01uF
1 2
C4710uF
12
C464.7uF
12
VDD_QREFD VDD_QCLKD VDD_SYNC VDD_LCV
VDD_CPF VDD_LCF
VDD_QREFA0 VDD_QREFA1
VDD_INP
VDD_QCLKV
VDD_SPI
nOSC
OSC
VDD_CPV LFV
VDD_QCLKA
VDD_QREFB0 VDD_QREFB1
VDD_QCLKB VDD_QREFC VDD_QCLKC
VDD_QCLKE
VDD_INP VDD_SPI VDD_LCF VDD_CPF VDD_LCV VDD_SYNC VDD_CPV
VDD_QCLKA VDD_QCLKB VDD_QCLKC VDD_QCLKD VDD_QCLKV
VDD_QREFA1 VDD_QREFA2 VDD_QREFB1 VDD_QREFC VDD_QREFD
VDD_QREFA2
VDD_QCLKE
VDD_QREFA0
VCXO_VC VCXO_OE VCXO_Q_N
VCXO_Q_P
VDD_VCXO
VDD_QREFB0
nOSC OSC

5 5
4 4
3 3
2 2
1 1
D D C C B B A A
Place it Close to Receiver
Clam-shell placement for the two MUX devices
CLK_IN0 ~3dB Pi Attenuator
Place it Close to Receiver
These 6 differential outputs (left and below) going to J1
Silksccreen: EXT_REF_OUT
Silksccreen: N Silksccreen: P
Silkscreen:
"H" at pin 1 side "L" at pin 8 side "CLK0_SEL0" at pin 8 "CLK0_SEL1" at pin 7 "CLK1_SEL0" at pin 6 "CLK1_SEL1" at pin 5
VDD_2.5V1
VCC_3V3
VDD_2.5V2
VDD_2.5V1VDD_2.5V2
VDD_2.5V1 VDD_2.5V1
VDD_2.5V2
CLK_0 4 nCLK_0 4
CLK_1 4 nCLK_1 4
SFP_RCV_CLK_P3
QCLK_C4 DAC_REFCLK_P 3
SFP_RCV_CLK_N3
nQCLK_C4 DAC_REFCLK_N 3
QREF_B14 PL_SYSREF_P 3 nQREF_B14 PL_SYSREF_N 3
QCLK_D4 ADC_REFCLK_P 3 nQCLK_D4 ADC_REFCLK_N 3
QREF_C4 DDR_PLY_CAP_P 3 nQREF_C4 DDR_PLY_CAP_N 3
QCLK_E04 PL_CLK_P 3
QREF_B04 AMS_SYSREF_P 3
nQCLK_E04 PL_CLK_N 3
nQREF_B04 AMS_SYSREF_N 3
QREF_A24 nQREF_A24
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
511
Friday, March 19, 2021
CLK-104
SZ
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
511
Friday, March 19, 2021
CLK-104
SZ
Title:
Size Part Number: Rev.
Date: Sheet: of
Engineer:
Integrated Device Technology
1140 West Warner Rd.
Tempe, AZ 85284
987456321587
AB
511
Friday, March 19, 2021
CLK-104
SZ
R75 180
21
R72 180
21
R67 5.10K
21
C74 0.1uF
1 2
R81 180
21
C57 0.1uF
12
R51 10.0K
21
R46 5.10K
21
R76 180
21
R55 5.10K
21
R69 100
21
C75 0.1uF
1 2
R48 10.0K
21
R83 180
21
C60 0.1uF
1 2
R65 DNP
21
R52 49.9
2
1
R58 200
2
1
C53 0.1uF
1 2
C73 0.1uF
1 2
R63 0.00
2
1
C66 0.1uF
1 2
C51 0.1uF
1 2
C72 0.1uF
1 2
R73 180
21
C71 0.1uF
1 2
R68 100
21
R61 5.10K
21
R47 5.10K
21
R77 180
21
ON
J11
Dip Switch 4
8 7 5
2 1 3 4
6
R57 200
2
1
C55 0.1uF
12
C65 0.1uF
1 2
U6
DOT050F-010.0M
NC_1
1NC_2 2
GND
3
OUT 4
NC_5 5
VDD
6
R66 5.10K
21
R78 180
21
R70 180
21
R59 200
2
1
J12
1
C67 0.1uF
1 2
R50 18
2
1
R53 270
21
C58 0.1uF
1 2
C63 0.1uF
1 2
R62 5.10K
21
C52 0.1uF
1 2
R74 180
21
FB3 600
500mA 0402
21
C62 0.1uF
1 2
U5
854S057
VDD_1
1
PCLK0
2
VT0
3
NPCLK0
4
SEL1
5
SEL0
6
PCLK1
7
VT1
8
NPCLK1
9
GND_10
10
GND_11
11
NPCLK2
12
VT2
13
PCLK2
14
NQ
15
Q
16
NPCLK3
17
VT3
18
PCLK3
19
VDD_20
20
J13
1
C69 0.1uF
1 2
C61 0.1uF
12
R49 100
21
R80 180
21
C56 1uF
12
R56 5.10K
21
C70 0.1uF
1 2
R71 180
21
C59 0.1uF
1 2
R79 180
21
R60 200
2
1
R54 270
21
C54 0.1uF
1 2
R82 180
21
R64 DNP
21
J10
1
FB4 600
500mA 0402
21
U7
854S057
VDD_1
1
PCLK0
2
VT0
3
NPCLK0
4
SEL1
5
SEL0
6
PCLK1
7
VT1
8
NPCLK1
9
GND_10
10
GND_11
11
NPCLK2
12
VT2
13
PCLK2
14
NQ
15
Q
16
NPCLK3
17
VT3
18
PCLK3
19
VDD_20
20
C68 0.1uF
1 2
C64 0.1uF
1 2
SFP_RCV_CLK_P
SMA_IN nSMA_IN
SFP_RCV_CLK_N
CLK0_SEL0 CLK0_SEL1 SMA_IN TCXO_IN nSMA_IN nTCXO_IN
TCXO_IN
nTCXO_IN
CLK1_SEL0 CLK1_SEL1
SFP_RCV_CLK_P SMA_IN SFP_RCV_CLK_N nSMA_IN
TCXO_IN nTCXO_IN
CLK1_SEL1 CLK1_SEL0 CLK0_SEL1 CLK0_SEL0