Renesas SH7262 Series Guide

APPLICATION NOTE
REJ06B0999-0100 Rev. 1.00 Page 1 of 36
Jun. 30, 2010
SH7262/SH7264 Group
Hardware Design Guide
Summary
This application note contains tips on designing a system using the SH7264. As a technical reference it will help the
designer avoid common mistakes and get their product up and running when doing their first SH2A design.
Target Device
SH7262/SH7264 MCU (In this document, SH7262/SH7264 are described as "SH7264".)
Contents
1. Power Supplies .................................................................................................................................2
2. Reset.................................................................................................................................................7
3. Oscillator Circuit..............................................................................................................................10
4. Operating Mode Control..................................................................................................................12
5. External ROM..................................................................................................................................17
6. Handling of Pins..............................................................................................................................21
7. On-chip Resource Access...............................................................................................................26
8. Endianness......................................................................................................................................27
9. Power-down Modes.........................................................................................................................28
10. References......................................................................................................................................34
Related Application Notes
For more information, refer to the following application notes:
•SH7262/SH7264 Group Guidelines for Hi-Speed USB 2.0 Board Design
•SH7262/SH7264 Group Using Deep Standby Mode in Power-down Mode
•SH7262/SH7264 Group Connecting the NOR Flash Memory
•SH7262/SH7264 Group Interfacing Serial Flash Memory Using the Renesas Serial Peripheral Interface
About Active-low Pins (Signals)
The symbol "#" suffixed to the pin (or signal) names indicates that the pins (or signals) are active-low.
REJ06B0999-0100
Rev. 1.00
Jun. 30, 2010

SH7262/SH7264 Group Hardware Design Guide
REJ06B0999-0100 Rev. 1.00 Page 2 of 36
Jun. 30, 2010
1. Power Supplies
1.1 Power Supplies
CPU core voltage is between 1.1 V and 1.3 V, and I/O power supply voltage is between 3.0 V and 3.6 V. This LSI
(SH7264) uses both digital and analog power supplies. Place the digital circuit and analog circuit as far as possible on
the board.
Table 1 lists the digital power supplies. Table 2 lists the analog power supplies. Figure 1 describes the note on using the
PLL oscillator circuit.
Table 1 Digital Power Supplies
Symbol Name Voltage Range Description
Vcc Power Supply 1.1 to 1.3 V Power supply pin
Connect all Vcc pins to the system power
supply. The system does not work when any
of those pins are open.
Vss Ground 0 V Ground pin
Connect all Vss pins to the system power
supply (0 V). The system does not work
when any of those pins are open.
PVcc I/O circuit power supply 3.0 to 3.6 V Power supply pin for I/O pins. Connect all
PVcc pins to the system power supply. The
system does not work when any of those
pins are open.
USBDPVcc (2) Transceiver digital pin
power supply 3.0 to 3.6 V Power supply for USB pins
USBDPVss (3) Transceiver digital pin
ground 0 V Ground for USB pins
USBDVcc (1) Transceiver digital core
power supply 1.1 to 1.3 V Power supply for USB core
USBDVss (3) Transceiver digital core
ground 0 V Ground for USB core
USBUVcc (1) Power supply for 480-
MHz USB 2.0
host/function modules
1.1 to 1.3 V Power supply for 480-MHz modules
USBUVss (3) Ground for 480-MHz
USB 2.0 host/function
modules
0 V Ground for 480-MHz modules
Notes:1. USBAVcc, USBDVcc, and USBUVcc must be at the same electric potential as the Vcc.
2. USBAPVcc and USBDPVcc must be at the same electric potential as the PVcc.
3. USBAVss, USBDVss, USBUVss, USBAPVss, and USBDPVss must be at the same potential as
the Vss.

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Table 2 Analog Power Supplies
Symbol Name Voltage Range Description
PLLVcc PLL power supply 1.1 to 1.3 V Power supply for internal PLL oscillator
PLLVss PLL ground 0 V Ground pin for internal PLL oscillator
USBAPVcc (2) (4) Transceiver analog pin
power supply 3.0 to 3.6 V Power supply for USB pins
USBAPVss (3) (4) Transceiver analog pin
ground 0 V Ground for USB pins
USBAVcc (1) (4) Transceiver analog core
power supply 1.1 to 1.3 V Power supply for USB pins
USBAVss (3) (4) Transceiver analog core
ground 0 V Ground for USB core
AVcc (5) (7) Analog power supply 3.0 to 3.6 V A/D Converter power supply pin
AVss (5) (7) Analog ground 0 V A/D Converter ground pin
AVref (6) (7) Analog reference voltage 3.0 to 3.6 V A/D Converter reference voltage pin
Notes:1. USBAVcc, USBDVcc, and USBUVcc must be at the same electric potential as the Vcc.
2. USBAPVcc and USBDPVcc must be at the same electric potential as the PVcc.
3. USBAVss, USBDVss, USBUVss, USBAPVss, and USBDPVss must be at the same electric
potential as the Vss.
4. Isolate analog power supplies (USBAVcc, USBAVss, USBAPVcc, and USBAPVss) from the digital
power supplies.
5. AVcc must be set as PVcc −0.3 V ≤AVcc ≤PVcc. AVss must be at the same electric potential as
the Vss.
Do not open pins AVcc and AVss when not using the A/D Converter, or in software standby mode.
When not using the A/D Converter, connect AVcc to PVcc, and AVss to Vss, respectively.
6. Set the reference voltage range of the AVref pin as 3.0 V ≤AVref ≤AVcc.
7. Isolate AVref and AVcc (also A/D Converter analog input pin) from the digital circuit with the AVss.
AVss must be connected on a stable digital ground (Vss) on board.

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Jun. 30, 2010
PLLVcc
PLLVss
Vcc
Vss
Power supply
Signal lines prohibited
Note: When designing the PLLVcc and PLLVss connection pattern for the PLL, signal lines from the board
power supply pins must be as short as possible and pattern width must be as wide as possible to
reduce inductive interferences. Since the analog power supply pins of the PLL are sensitive to the
noise, the system may mulfunction due to inductive interference at the other power supply pins. To
prevent such malfunction, do not supply the same resources to the analog power supply pins and the
digital power supply pins Vcc and PVcc on the board if at all possible.
Figure 1 Note on Using PLL Oscillation Circuit

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1.2 Bypass Capacitor
A multilayer ceramic capacitor must be installed as a bypass capacitor for each pair of power supply pins. Install the
bypass capacitor as close as possible to the LSI power supply pins. Connect the bypass capacitor with capacitance
between 0.1 and 0.33 µF (recommended value).
Figure 2 shows an example of installing an external capacitor with the SH7262. Figure 3 shows an example of installing
an external capacitor with the SH7264.
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PLQP0176KB-A
Top view
PF9
PF8
PF7
PF6
PF5
PF4
PF3
PF2
PVcc
PF1
Vss
PF0
Vcc
PE5
PE4
PE3
PE2
PE1
PE0
PVcc
Vss
PD15
PD14
PD13
PD12
PD11
PD10
Vss
PVcc
PD9
PD8
PD7
PD6
PD5
PD4
PD3
Vcc
PD2
Vss
PD1
PVcc
PD0
PC0
PC1
PC2 PC3 PC4 PC5 PC6 Vcc PC7 Vss PC8 PVcc PB1 PB2 PB3 PB4 PB5 PB6 PB7 Vcc PB8 Vss PB9 PVcc PB10 PB11 PB12 PB13 PB14 PB15 Vcc PB16 Vss CKIO PVcc PB17 PB18 PB19 PB20 PB21 PB22 Vcc Vss PVcc RES NMI
Vcc
PF10
Vss
PF11
PVcc
PF12
AUDIO_X1 AUDIO_X2
PG0 PG1
Vcc
PG2
Vss
PG3
PVcc
PG4 PG5 PG6 PG7 PG8 PG9
PG10
Vcc
PG11
Vss
PG12
PVcc
PG13 PG14 PG15 PG16 PG17 PG18 PG19 PG20
Vcc Vss
PVcc
TCK
TMS
TDI
TDO
ASEBRKAK/ASEBRK
TRST
AVcc
AVref
AVss
PH3
PH2
PH1
PH0
USBUVss
USBUVcc
USBAVss
USBAVcc
USBAPVss
USBAPVcc
REFRIN
USBDVss
USBDVcc
VBUS
DP
DM
USBDPVss
USBDPVcc
ASEMD
USB_X2
USB_X1
PVcc
PJ0
Vss
PJ1
Vcc
PJ2
PJ3
Vss
RTC_X2
RTC_X1
PVcc
Vss
PA0
PA1
XTAL
EXTAL
PA2
PLLVss
PA3
PLLVcc
Figure 2 Installing an External Capacitor with the SH7262

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PLQP0208KB-A
Top view
PF9
PF8
PF7
PF6
PF5
PF4
PF3
PF2
PVcc
PF1
Vss
PF0
Vcc
PK7
PK6
PK5
PK4
PE5
PE4
PE3
PE2
PE1
PE0
PK3
PVcc
Vss
PK2
PK1
PK0
PD15
PD14
PD13
PD12
PD11
PD10
Vss
PVcc
PD9
PD8
PD7
PD6
PD5
PD4
PD3
Vcc
PD2
Vss
PD1
PVcc
PD0
PC0
PC1
PC2 PC3 Vss PC4 PVcc PC9 PC10 PC5 PC6 Vcc PC7 Vss PC8 PVcc PB1 PB2 PB3 PB4 PB5 PB6 PB7 Vcc PB8 Vss PB9 PVcc PB10 PB11 PB12 PB13 PB14 PB15 Vcc PB16 Vss CKIO PVcc PB17 PB18 PB19 PB20 PB21 PB22 PJ11 Vcc PJ10 Vss PJ9 PVcc PJ8 RES NMI
Vcc
PF10
Vss
PF11
PVcc
PF12
AUDIO_X1 AUDIO_X2
PK8 PK9
PK10 PK11
PG0 PG1
Vcc
PG2
Vss
PG3
PVcc
PG4 PG5 PG6 PG7 PG8 PG9
PG10
Vcc
PG11
Vss
PG12
PVcc
PG13 PG14 PG15 PG16 PG17 PG18 PG19 PG20
Vcc
PG21
Vss
PG22
PVcc
PG23 PG24
TCK
TMS
TDI
TDO
ASEBRKAK/ASEBRK
TRST
AVcc
PH7
AVref
PH6
AVss
PH5
PH4
PH3
PH2
PH1
PH0
USBUVss
USBUVcc
USBAVss
USBAVcc
USBAPVss
USBAPVcc
REFRIN
USBDVss
USBDVcc
VBUS
DP
DM
USBDPVss
USBDPVcc
ASEMD
USB_X2
USB_X1
PVcc
PJ0
Vss
PJ1
Vcc
PJ2
PJ3
Vss
RTC_X2
RTC_X1
PVcc
PJ4
Vss
PJ5
PJ6
PJ7
PA0
PA1
XTAL
EXTAL
PA2
PLLVss
PA3
PLLVcc
Figure 3 Installing an External Capacitor with the SH7264

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Jun. 30, 2010
2. Reset
2.1 Power-on/Power-off Sequence
Either the 1.2 V power supplies (Vcc, PLVcc, USBAVcc, USBDVcc, and USBUVcc) or 3.3 V power supplies (PVcc,
AVcc, USBAPVcc, and USBDPVcc) can be turned ON or OFF first.
When turning ON the SH7264, make sure to fix pins TRST# and RES# to low level. If not, output pins and I/O pins
(output) may be in undefined state to cause malfunction in the entire system.
To avoid such malfunction described above, make sure to fix pins TRST# and RES# to low level when turning OFF the
SH7264.
2.2 Oscillation Settling Time
When the RES# pin is driven low, the SH7264 enters the power-on reset state. To make sure to reset the SH7264, the
RES# pin must be kept at the low level during the oscillation settling time at power-on, or when exiting from software
standby mode and deep standby mode. Keep the RES# pin at low level for at least 20 tcyc when setting the RES# pin to
low level while the clock is running.
The power-on oscillation settling time (tosc1) is 10 ms, which is specified from when the Vcc exceeds the minimum
operating voltage until the RES# pin exceeds the VIL voltage. Figure 4 shows the relation between power-on/off and
clock, reset signals. This timing is easily accommodated by many "supervisor" ICs available on the market such as
Renesas Electronics RNA51957BFP.
CKIO,
Internal clock
Vcc
RES#
TRST#
Vcc Min.
Power-on oscillation settling time (tOSC1)
Stability oscillation period
Vcc Min.
Normal operation period
(Instruction processing)
Note: Oscillation settling time when the internal oscillator is used.
MD_BOOT1
MD_BOOT0
MD_CLK1
MD_CLK0
Mode hold time (tMDH)
Figure 4 Relations between Power-on/off and Clock, Reset Signals

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2.3 Power-on Reset
The SH7264 has two reset options; power-on reset and manual reset. This section describes sources for the power-on
reset exception handling.
2.3.1 Power-on Reset by the RES# Pin
When the RES# pin is driven low, the SH7264 enters power-on reset state to initialize the CPU’s internal state and all
on-chip peripheral registers (note). In power-on reset state, power-on reset exception handling starts when the RES# pin is
first driven low for a fixed period and then returns to high. For more information on the "fixed period" to drive the
RES# pin low, refer to 2.2 Oscillation Settling Time.
2.3.2 Power-on Reset by the User Debug Interface (H-UDI) Reset Assert Command
When the H-UDI reset assert command is set, the SH7264 enters the power-on reset state to initialize the CPU’s
internal state and all on-chip peripheral registers (note), like the power-on reset by the RES# pin. Power-on reset
exception handling starts in power-on reset state. The period required between the H-UDI reset assert command and the
H-UDI reset negate command is the same as the period to drive the RES# pin low to start the power-on reset.
2.3.3 Power-on Reset by the Watchdog Timer (WDT)
When setting the WDT as watchdog timer mode, and specifying the power-on reset when the WDT watchdog timer
counter (WTCNT) overflows, the SH7264 enters power-on reset state and the WDT starts power-on reset exception
handling, however, the Watchdog reset control/status register (WRCSR) of the WDT and the Frequency control register
(FRQCR) of the Clock Pulse Generator (CPG) are not initialized (note).
Note: For more information on register status, refer to 36.3 Register States in Each Operating Mode in the SH7262
Group, SH7264 Group Hardware Manual.
2.4 Manual Reset
This section describes sources for the manual reset exception handling.
2.4.1 Manual Reset by the Watchdog Timer (WDT)
When setting the WDT as watchdog timer mode, and specifying the manual reset when the WTCNT of the WDT
overflows, the SH7264 enters manual reset state and the WDT starts manual reset exception handling.
When the SH7264 enters manual reset state while the CPU is leaving the bus or the Direct Memory Access Controller
(DMAC) transfers data in burst mode, the manual reset exception handling is deferred until the CPU retrieves the bus.
In manual reset state, the SH7264 initializes CPU and the BN bit in the Bank number register (IBNR) of the Interrupt
controller (INTC), but FPU and other modules are not included (note).
Note: For more information on register status, refer to 36.3 Register States in Each Operating Mode in the SH7262
Group, SH7264 Group Hardware Manual.
2.5 System Reset by the Watchdog Timer (WDT)
Sometimes it is desirable to have the WDT reset the entire system during an overflow condition using the WDTOVF#
signal from the WDT. In this case the WDTOVF# should be not be connected directly to the RES# of the MCU as this
would cause problems. A “tiny” gate can be used to OR the “power-on” reset signal and the WDTOVF# as shown in
Figure 5: System Reset using WDTOVF#.

SH7262/SH7264 Group Hardware Design Guide
REJ06B0999-0100 Rev. 1.00 Page 9 of 36
Jun. 30, 2010
RES
WDTOVF
Reset input
(Low active)
Reset signal to
entire system
(Low active)
Figure 5: System Reset using WDTOVF#

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3. Oscillator Circuit
3.1 Clock Pins
Pins listed in the following table can be connected to crystal resonators or input clocks.
Table 3 Clock pins
Xin Pin
(Crystal resonator can be
connected, or used as
external clock input pin)
Xout Pin
(Crystal resonator can be
connected)
Remarks
EXTAL XTAL 10 MHz to 18 MHz
USB_X1 USB_X2 •When the USB controller is in high-speed:
48 MHz ± 100 ppm
•When the USB controller is NOT in high-speed and
operating as the USB host:
48 MHz ± 500 ppm
•When the USB controller is NOT in high-speed and
operating as the USB function:
48 MHz ± 2500 ppm
AUDIO_X1 AUDIO_X2 •When connecting a crystal resonator
10 MHz to 25 MHz
•When inputting an external clock
1 MHz to 25 MHz
RTC_X1 RTC_X2 32.768 kHz
3.2 Connecting an External Clock
Figure 6 shows an example of connecting an external clock to the SH7264. When leaving the Xout pin as open, the
parasitic capacitance must be less than 10 pF.
Xin
Xout
SH7264
External clock input
Open
Figure 6 Connecting an External Clock