Renesas H8s/2319 series User manual

2003.12.15

16 H8S/2319Group, H8S/2318Group

Hardware Manual

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2300 Series

Rev.5.00

The revision list can be viewed directly by

clicking the title page.

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Renesas 16-Bit Single-Chip Microcomputer

H8S Family/H8S/2300 Series

H8S/2319 Group,

H8S/2318 Group

Hardware Manual

REJ09B0089-0500O

Rev. 5.00, 12/03, page iv of xxx

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is

always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or

property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)

placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or

mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product

best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other

rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in

the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these

materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents

information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp.

without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas

Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before

purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or

errors.

Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas

Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and

algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of

the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss

resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under

circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas

Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such

as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these

materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license

from the Japanese government and cannot be imported into a country other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is

prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

Rev. 5.00, 12/03, page vof xxx

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

they are used as test pins or to reduce noise. If something is connected to the NC pins, the

operation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.

The states of internal circuits are undefined until full power is supplied throughout the chip

and a low level is input on the reset pin. During the period where the states are undefined,

the register settings and the output state of each pin are also undefined. Design your

system so that it does not malfunction because of processing while it is in this undefined

state. For those products which have a reset function, reset the LSI immediately after the

power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these addresses. Do not access these registers; the system’s

operation is not guaranteed if they are accessed.

Rev. 5.00, 12/03, page vi of xxx

Rev. 5.00, 12/03, page vii of xxx

Preface

This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit

architecture as its core, and the peripheral functions required to configure a system.

This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a 16-bit

timer pulse unit (TPU), a watchdog timer (WDT), a serial communication interface (SCI), a D/A

converter, an A/D converter, and I/O ports as on-chip supporting modules. This LSI is suitable for

use as an embedded processor for high-level control systems. Its on-chip ROM are flash memory

(F-ZTAT™*) and mask ROM that provides flexibility as it can be reprogrammed in no time to

cope with all situations from the early stages of mass production to full-scale mass production.

This is particularly applicable to application devices with specifications that will most probably

change.

Note: * F-ZTAT is a trademark of Renesas Technology Corp.

Target Users: This manual was written for users who will be using the H8S/2319 Group,

H8S/2318 Group in the design of application systems. Members of this audience are

expected to understand the fundamentals of electrical circuits, logical circuits, and

microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2319 Group, H8S/2318 Group to the above audience.

Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed

description of the instruction set.

Notes on reading this manual:

•In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

•In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

•In order to understand the details of a register when its name is known

The addresses, bits, and initial values of the registers are summarized in Appendix B, Internal

I/O Registers.

Example: Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

(http://www.renesas.com/eng/)

Rev. 5.00, 12/03, page viii of xxx

H8S/2319 Group, H8S/2318 Group manuals:

Manual Title ADE No.

H8S/2319 Group, H8S/2318 Group Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

Users manuals for development tools:

Manual Title ADE No.

C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-247

Simulator Debugger (for Windows) Users Manual ADE-702-037

High-Performance Embedded Workshop Users Manual ADE-702-201

Application Notes:

Manual Title ADE No.

H8S Family Technical Q & A ADE-502-059

Rev. 5.00, 12/03, page ix of xxx

Main Revisions and Additions in this Edition

Item Page Revision (See Manual for Details)

1.3.1 Pin Arrangement

Figure 1-2 Pin

Arrangement (TFP-

100B, TFP-100G: Top

View)

9 Figure title amended

Table amended

Pin No.

TFP-100B,

TFP-100G FP-100A

1.3.2 Pin Functions in

Each Operating Mode

Table 1-2 Pin

Functions in Each

Operating Mode

13 to 16

Table amended

Pin No.

Type Symbol TFP-100B,

TFP-100G FP-100A

1.3.3 Pin Functions

Table 1.3 Pin

Functions

17 to 23

17.11.2 Socket

Adapters and Memory

Map

Figure 17-21

H8S/2318 F-ZTAT,

H8S/2317 F-ZTAT,

H8S/2315 F-ZTAT,

H8S/2314 F-ZTAT

Socket Adapter Pin

Assignments

596 Figure amended

H8S/2318 F-ZTAT, H8S/2317 F-ZTAT,

H8S/2315 F-ZTAT, H8S/2314 F-ZTAT

TFP-100B,

TFP-100G FP-100A Pin Name

Rev. 5.00, 12/03, page x of xxx

Item Page Revision (See Manual for Details)

“Advanced” deleted from Mnemonic column

Instruc-

tion

Fetch

Branch

Address

Read

Stack

Opera-

tion

Byte

Data

Access

Word

Data

Access

Internal

Opera-

tion

Instruction Mnemonic I J K L M N

BSR BSR d:8 2 2

BSR d:16 2 2 1

JMP JMP @ERn 2

JMP @aa:24 2 1

JMP @@aa:8 2 2 1

JSR JSR @ERn 2 2

JSR @aa:24 2 2 1

JSR @@aa:8 2 2 2

RTE RTE 2 2/3*11

RTS RTS 2 2 1

TRAPA TRAPA #x:2 2 2 2/3*12

A.4 Number of States

Required for Instruction

Execution

895, 897,

901, 902

Table A-5 Number of

Cycles in Instruction

Execution

903 Note 1 amended

The number of state cycles is 2 when EXR is invalid, and 3 when EXR is

valid.

“Advanced” deleted from Instruction column

Instruction1234 5 6789

BSR d:8 R:W NEXT R:W EA W:W:M

stack(H) W:W

stack(L)

BSR d:16 R:W 2nd Internal

operation,

1 state

R:W EA W:W:M

stack(H) W:W

stack(L)

JMP

@@aa:8 R:W NEXT R:W:M aa:8 R:W: aa:8 Internal

operation,

1 state

R:W EA

JSR @ERn R:W NEXT R:W EA W:W:M

stack(H) W:W

stack(L)

JSR @aa:24 R:W 2nd Internal

operation,

1 state

R:W EA W:W:M

stack(H) W:W

stack(L)

JSR

@@aa:8 R:W NEXT R:W:M aa:8 R:W aa:8 W:W:M

stack(H) W:W

stack(L) R:W EA

RTS R:W NEXT W:W:M

stack(H) R:W

stack(L) Internal

operation,

1 state

R:W*4

TRAPA #x:2 R:W NEXT Internal

operation,

1 state

W:W

stack(L) W:W

stack(H) W:W

stack(EXR) R:W:M VEC R:W

VEC+2 Internal

operation,

1 state

R:W*7

Reset

exception

handling

R:W VEC R:W

VEC+2 Internal

operation,

1 state

R:W*5

Interrupt

exception

handling

R:W*6Internal

operation,

1 state

W:W

stack(L) W:W

stack(H) W:W

stack(EXR) R:W:M VEC R:W

VEC+2 Internal

operation,

1 state

R:W*7

A.5 Bus States during

Instruction Execution

Table A-6 Instruction

Execution Cycles

909, 911,

915, 916,

917

Rev. 5.00, 12/03, page xi of xxx

Item Page Revision (See Manual for Details)

Table amended

Product Type Model Marking Package (Package Code)

H8S/2318 HD6432318*3HD6432318TE 100-pin TQFP (TFP-100B)Mask ROM

version HD6432318F 100-pin QFP (FP-100A)

HD64F2318 HD64F2318VTE 100-pin TQFP (TFP-100B)

HD64F2318VTF 100-pin TQFP (TFP-100G)

F-ZTAT

version

HD64F2318VF 100-pin QFP (FP-100A)

H8S/2317 HD6432317*3HD6432317TE 100-pin TQFP (TFP-100B)

HD6432317F 100-pin QFP (FP-100A)

HD6432317S*4HD64F2317STE 100-pin TQFP (TFP-100B)

HD6432317STF 100-pin TQFP (TFP-100G)

Mask ROM

version

HD64F2317SF 100-pin QFP (FP-100A)

HD64F2317 HD64F2317VTE 100-pin TQFP (TFP-100B)

HD64F2317VTF 100-pin TQFP (TFP-100G)

F-ZTAT

version

HD64F2317VF 100-pin QFP (FP-100A)

Appendix E Product

Lineup

Table E-1 H8S/2319

Series, H8S/2318

Series Product Lineup

1084

Appendix F Package

Dimensions

Figure F.2 TFP-100G

Package Dimensions

1087 Figure added

Package Code

JEDEC

JEITA

Mass

(reference value)

TFP-100G

—

Conforms

0.4 g

Dimension including the plating thickness

Base material dimension

14.0 ± 0.2

0.07

0.10

0.5 ± 0.1

14.0 ± 0.2

0.4

1.20 Max

*0.17 ± 0.05

0° – 8°

75 51

125

100 26

*0.18 ± 0.05

1.0

1.2

0.16 ± 0.04

0.15 ± 0.04

1.00

0.10 ± 0.10

As of January, 2003

Unit: mm

Rev. 5.00, 12/03, page xii of xxx

Rev. 5.00, 12/03, page xiii of xxx

Contents

Section 1 Overview............................................................................................................. 1

1.1 Overview........................................................................................................................... 1

1.2 Block Diagram.................................................................................................................. 8

1.3 Pin Description.................................................................................................................. 9

1.3.1 Pin Arrangement.................................................................................................. 9

1.3.2 Pin Functions in Each Operating Mode............................................................... 13

1.3.3 Pin Functions ....................................................................................................... 17

Section 2 CPU ...................................................................................................................... 25

2.1 Overview........................................................................................................................... 25

2.1.1 Features................................................................................................................ 25

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 26

2.1.3 Differences from H8/300 CPU ............................................................................ 27

2.1.4 Differences from H8/300H CPU.......................................................................... 27

2.2 CPU Operating Modes...................................................................................................... 28

2.3 Address Space................................................................................................................... 31

2.4 Register Configuration...................................................................................................... 32

2.4.1 Overview.............................................................................................................. 32

2.4.2 General Registers................................................................................................. 33

2.4.3 Control Registers ................................................................................................. 34

2.4.4 Initial Register Values.......................................................................................... 35

2.5 Data Formats..................................................................................................................... 36

2.5.1 General Register Data Formats............................................................................ 36

2.5.2 Memory Data Formats......................................................................................... 38

2.6 Instruction Set................................................................................................................... 39

2.6.1 Overview.............................................................................................................. 39

2.6.2 Instructions and Addressing Modes..................................................................... 40

2.6.3 Table of Instructions Classified by Function ...................................................... 41

2.6.4 Basic Instruction Formats .................................................................................... 51

2.7 Addressing Modes and Effective Address Calculation..................................................... 52

2.7.1 Addressing Mode................................................................................................. 52

2.7.2 Effective Address Calculation ............................................................................. 55

2.8 Processing States............................................................................................................... 59

2.8.1 Overview.............................................................................................................. 59

2.8.2 Reset State............................................................................................................ 60

2.8.3 Exception-Handling State.................................................................................... 61

2.8.4 Program Execution State...................................................................................... 63

2.8.5 Bus-Released State............................................................................................... 63

2.8.6 Power-Down State............................................................................................... 63

Rev. 5.00, 12/03, page xiv of xxx

2.9 Basic Timing..................................................................................................................... 64

2.9.1 Overview.............................................................................................................. 64

2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 64

2.9.3 On-Chip Supporting Module Access Timing....................................................... 66

2.9.4 External Address Space Access Timing .............................................................. 67

2.10 Usage Note........................................................................................................................ 67

2.10.1 TAS Instruction.................................................................................................... 67

Section 3 MCU Operating Modes .................................................................................. 69

3.1 Overview........................................................................................................................... 69

3.1.1 Operating Mode Selection (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT,

H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT)...................................................... 69

3.1.2 Operating Mode Selection (Mask ROM, ROMless, H8S/2319 F-ZTAT, and

H8S/2319C F-ZTAT) .......................................................................................... 70

3.1.3 Register Configuration......................................................................................... 72

3.2 Register Descriptions........................................................................................................ 72

3.2.1 Mode Control Register (MDCR) ......................................................................... 72

3.2.2 System Control Register (SYSCR)...................................................................... 73

3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Versions Only)........................ 74

3.3 Operating Mode Descriptions........................................................................................... 75

3.3.1 Mode 1 (H8S/2319C F-ZTAT Only)................................................................... 75

3.3.2 Mode 2 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only)............................. 75

3.3.3 Mode 3 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only)............................. 75

3.3.4 Mode 4 (Expanded Mode with On-Chip ROM Disabled)................................... 75

3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled)................................... 76

3.3.6 Mode 6 (Expanded Mode with On-Chip ROM Enabled) .................................... 76

3.3.7 Mode 7 (Single-Chip Mode)................................................................................ 76

3.3.8 Modes 8 and 9 (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT,

and H8S/2314 F-ZTAT Only).............................................................................. 76

3.3.9 Mode 10 (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT,