Renesas RA Series Guide

Application Note
R01AN6060EU0100 Rev.1.00 Page 1 of 44
Sep.14.21
Renesas RA Family
RA2 Quick Design Guide
Introduction
This document answers common questions and points out subtleties of the MCU that might be missed
unless the hardware manual was extensively reviewed. The document is not intended to be a replacement
for the hardware manual; it is intended to supplement the manual by highlighting some key items most
engineers will need to start their own design. It also discusses some design decisions from an application
point of view.
Target Device
RA2 MCU Series
Contents
1. Power Supplies........................................................................................................................4
1.1 References..............................................................................................................................................5
2. Emulator Support.....................................................................................................................6
2.1 SWD Interface.........................................................................................................................................7
2.2 Serial Programming Interface using SCI.................................................................................................8
2.3 Combination Debug Interface.................................................................................................................. 9
3. MCU Operating Modes............................................................................................................9
4. Option Setting Memory..........................................................................................................10
4.1 Option Setting Memory Registers .........................................................................................................11
5. Clock Circuits.........................................................................................................................12
5.1 Reset Conditions...................................................................................................................................13
5.2 Clock Frequency Requirements............................................................................................................13
5.2.1 Requirements for USB Communications ............................................................................................14
5.2.2 Requirements for Programming and Erasing ROM or Data Flash......................................................14
5.3 Lowering Clock Generation Circuit (CGC) Power Consumption...........................................................14
5.4 Writing the System Clock Control Registers .........................................................................................14
5.5 Clock Setup Example............................................................................................................................15
5.6 HOCO Accuracy....................................................................................................................................15
5.7 Flash Interface Clock.............................................................................................................................16
5.8 Board Design.........................................................................................................................................16
5.9 External Crystal Resonator selection....................................................................................................16
5.10 External Clock Input ..............................................................................................................................17
6. Reset Requirements and the Reset Circuit............................................................................17
6.1 Pin Reset...............................................................................................................................................18
6.2 Power-On Reset....................................................................................................................................18

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6.3 Independent Watchdog Timer Reset.....................................................................................................18
6.4 Watchdog Timer Reset..........................................................................................................................18
6.5 Voltage-Monitoring Resets....................................................................................................................19
6.6 Software Reset......................................................................................................................................19
6.7 Other Resets .........................................................................................................................................19
6.8 Determination of Cold/Warm Start ........................................................................................................19
6.9 Determining the Reset Source..............................................................................................................19
7. Memory .................................................................................................................................20
7.1 SRAM....................................................................................................................................................20
7.2 Peripheral I/O Registers........................................................................................................................21
7.3 On-Chip Flash Memory .........................................................................................................................21
7.3.1 Background Operation ........................................................................................................................22
7.3.2 ID Code Protection..............................................................................................................................22
7.3.3 Memory Protection Unit.......................................................................................................................23
7.4 Restriction on Endianness.....................................................................................................................24
8. Register Write Protection.......................................................................................................24
9. I/O Port Configuration ...........................................................................................................25
9.1 Multifunction Pin Selection Design Strategies.......................................................................................25
9.2 Setting Up and Using a Port as GPIO...................................................................................................25
9.2.1 Internal Pull-Ups..................................................................................................................................27
9.2.2 Open-Drain Output..............................................................................................................................27
9.2.3 Drive Capacity.....................................................................................................................................27
9.3 Setting Up and Using Port Peripheral Functions...................................................................................27
9.4 Setting Up and Using IRQ Pins.............................................................................................................28
9.5 Unused Pins..........................................................................................................................................30
9.6 Nonexistent Pins....................................................................................................................................31
9.7 Electrical Characteristics.......................................................................................................................31
10. Module Stop Function............................................................................................................31
11. Interrupt Control Unit .............................................................................................................31
12. Low Power Consumption.......................................................................................................33
13. Buses ....................................................................................................................................36
13.1 Bus Error Monitoring..............................................................................................................................37
13.1.1 Bus Error Types...................................................................................................................................37
13.1.2 Operation When a Bus Error Occurs...................................................................................................37
14. 24-Bit Sigma-Delta A/D Converter (SDADC24)......................................................................37
15. Operational Amplifier (OPAMP) with Configurable Switches..................................................39

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16. General Layout Practices.......................................................................................................40
16.1 Digital Domain vs. Analog Domain........................................................................................................40
16.2 High Speed Signal Design Considerations ...........................................................................................41
16.3 Signal Group Selections........................................................................................................................41
17. References............................................................................................................................42
Revision History............................................................................................................................44

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1. Power Supplies
The RA family has digital power supplies and analog power supplies. The power supplies use the following
pins.
Table 1. Digital Power Supplies
Symbol
Name
Description
VCC
Power supply
Power supply pin. Connect to the system power
supply. Connect this pin to VSS via a 0.1-µF
capacitor placed close to the VCC pin.
VSS
Ground
Ground
VCL
Power supply
Connect this pin to VSS via a capacitor close to the
VCL pin. The value depends upon the specific MCU
Group.
VCC_USB*1
USB FS power supply
USB Full-speed power supply pin. Connect this pin to
VCC. Connect this pin to VSS_USB via a 0.1-µF
capacitor placed close to the VCC_USB pin.
VSS_USB
USB FS ground
USB Full-speed ground pin. Connect this pin to VSS.
VCC_DCDC*2
Switching regulator power
supply
In DCDC mode, connect this pin to VCC. Connect
this pin to VSS through a 0.1-µF capacitor placed
close to the VCC_DCDC pin. In LDO mode, leave
this pin open.
VSS_DCDC*2
Switching regulator
ground pin
In DCDC mode, connect this pin to VSS. In LDO
mode, leave this pin open.
VLO
Switching regulator pin
In DCDC mode, connect this pin to an external
inductor then connect it to VCL pin. Place the
inductor and capacitor close to the pin.
Note 1: Only used on RA2A1. VCC_USB can be either input or output. As input, it supplies the USB
transceiver. As output, it is the voltage out from the USB LDO Regulator, and needs an external
capacitor. When the USB LDO Regulator is not used, connect to VCC. When the regulator is used,
connect to VSS through a 1.0-µF capacitor.
Note 2: Only used on RA2L1. Please see the chapter “Internal Voltage Regulator” in the RA2L1 Hardware
User’s Manual for implementation guidelines.

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Table 2. Analog Power Supplies
Symbol
Name
Description
AVCC0*3
Analog power supply
Analog voltage supply pin for the respective modules.
Connect this pin to the same voltage as the VCC pin.
AVSS0*3
Analog ground
Analog ground for the respective modules. Connect
this pin to the same voltage as the VSS pin.
VREFH0*1
12-bit ADC high reference
voltage
Reference voltage input pin for the 12-bit A/D.
Connect this pin to AVCC0 if the 12-bit A/D converter
is not used.
*4
VREFL0*1
12-bit ADC low reference
voltage
Analog reference ground pin for the 12-bit A/D
converter. Connect this pin to AVSS0 if the 12-bit A/D
converter is not used.*4
VREFH*2
12-bit DAC analog supply
Reference voltage input pin for the D/A converter.
Connect this pin to AVCC0 if the D/A converter is not
used.
VREFL*2
12-bit DAC analog ground
Reference ground pin for the D/A converter. Connect
this pin to AVSS0 if the D/A converter is not used.
AVCC1*2
24-bit SDADC analog
supply voltage
Analog voltage supply pin for the 24-bit SDADC
module.
AVSS1*2
24-bit SDADC analog
ground
Analog ground pin for the 24-bit SDADC module.
VREFI*2
24-bit SDADC external
reference supply
External voltage reference for the 24-bit SDADC,
multiplexed with the SBIAS output. As an input, this
pin has a voltage range of 0.8 V to 2.4 V, set in 0.2-V
increments. Connect this pin to AVSS1 through a
0.22-µF capacitor.
Notes 1: For RA2A1, this applies to the 16-bit ADC.
2: Present on RA2A1 only.
3: Not present on RA2E2
4: For RA2E2, connect VREFH0 to VCC and VREFL0 to VSS if the 12-bit ADC is not used.
1.1 References
Further information regarding the power supply for the RA MCU Group can be found in the following
documents:
•R01UH0888 RA2A1 Group, RA2A1 Group User’s Manual: Hardware
•R01UH0852 RA2E1 Group, RA2E1 Group User’s Manual: Hardware
•R01UH0919 RA2E2 Group, RA2E2 Group User’s Manual: Hardware (preliminary)
•R01UH0853 RA2L1 Group, RA2L1 Group User’s Manual: Hardware
Chapter numbers may vary between Arm Cortex-M4 and Arm Cortex-M33 devices.
Chapter 1, “Overview”, lists power pins in each package with recommended bypass capacitors.
Chapter 5, “Resets”, discusses the Power-on reset and how to differentiate this from other reset sources.
Chapter 7, “Low Voltage Detection”, provides details on the Low-Voltage Detection Circuit that can be used
to monitor the power supply. Chapter 6, “Option-Setting Memory”, additionally describes how to enable
Low-Voltage Detection 0 Circuit automatically at startup.
If you plan to use the on-chip Analog to Digital Converters (ADC) or the Digital to Analog Converter (DAC),
refer to one of the following chapters in the respective Hardware User’s Manuals for details on how to
provide filtered power supplies for these peripherals:

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•12-Bit A/D Converter (ADC12)
•16-Bit A/D Converter (ADC16)
•24-Bit Sigma-Delta A/D Converter (SDADC24)
•8-Bit D/A Converter (DAC8)
•12-Bit D/A Converter (DAC12)
Table 3. RA2 MCU Groups, User’s Manual: Hardware
Chapter Name
Description
Overview
Lists power pins in each package with notes on termination and bypassing.
Resets
Discusses the Power-on Reset and how to differentiate this from other
reset sources.
Low Voltage Detection
Provides details on the Low-Voltage Detection Circuit that can be used to
monitor the power supply.
Low Power Modes
Using low power modes may allow you to reduce the voltage of the power
supply. See this chapter for details on how operating modes affect power
supply requirements.
12-Bit A/D Converter
16-Bit A/D Converter
24-Bit Sigma-Delta A/D
Converter
8-Bit D/A Converter
12-bit D/A Converter
If you plan to use the on-chip A/D or D/A converters, these chapters give
details on how to provide filtered power supplies for these peripherals.
Clock Generation Circuit
Provides detailed descriptions on how to configure and use the available
clocks, including PCB design recommendations.
2. Emulator Support
RA2 MCU devices have an emulator interface that supports both debugging, using SWD communication,
and serial programming using SCI communication. This emulator makes it easy to switch between
debugging and serial programming.
The SWD emulator interface can be connected to an ARM-standard 10-pin or 20-pin socket. TXD and RXD
pins are added for serial programming using SCI communication.
Emulator support is useful for product development and prototyping, but may not be needed once a design
moves to production. If emulator support is no longer needed for a design, make sure to configure the ports
according to the “Handling of Unused Pins” section of the related MCU Hardware User’s Manual. See also
section 9.5 in this document.

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2.1 SWD Interface
Figure 1. SWD Interface Connections
Note: 1. The output of the reset circuit of the user system must be open collector.

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2.2 Serial Programming Interface using SCI
Figure 2. Serial Programming Interface using SCI Connections
Note: 1. The output of the reset circuit of the user system must be open collector.

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2.3 Combination Debug Interface
Figure 3. Debug Interface for both SWD and programming with SCI Connections
Note: 1. The output of the reset circuit of the user system must be open collector.
3. MCU Operating Modes
The RA2MCU series can enter one of two modes after reset: Single-chip mode or SCI/USB boot mode. The
boot mode is selected by the MD pin:
Table 4. Operating Modes Available at Reset
Operating Mode
MD
On-Chip Flash Memory
Single-chip mode
1
Enable
SCI/USB boot mode
0
Enable
Figure 4 shows operating mode transitions as determined by the mode-setting pin.

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Figure 4. Mode Setting Pin Level and Operating Mode
Note that USB boot mode is only available on devices that have the USB Full Speed peripheral, such as
RA2A1. For the RA2A1 MCU Group, USB boot mode doesn’t exist in 32-pin products.
A typical MCU boot mode circuit includes a jumper and a couple of resistors to allow selections to connect
the MD pin to VCC or Ground.
Figure 5. Typical Circuit for MCU Boot Mode Selection
4. Option Setting Memory
The option setting memory determines the state of the MCU after a reset. It is allocated to the configuration
setting area and the program flash area of the flash memory. The available methods of setting are different
for the two areas.
The registers are detailed in the “Option Setting Memory” chapter in the Hardware User’s Manual.
The flash option registers occupy space in the code flash memory map. Although the registers are located in
a portion of the flash memory that was reserved on the RA MCUs, it is possible that some customers may
store data in these locations inadvertently. The user must check to ensure that no unwanted data is written to
these locations or else unexpected behavior of the chip may result. Additionally, when using binary files for
programming, the user must ensure that reserved areas of memory are not programmed due to the
addresses of the configuration setting area. For instance, settings in the flash option registers can enable the
Independent Watchdog Timer (IWDT) immediately after reset. If data stored in program ROM inadvertently
overlaps the option setting memory register, it is possible to turn on the IWDT on without realizing it. This will
cause the debugger to have communications problems with the board.
The figure below shows the option setting memory area, which consists of the option function select registers
on RA2A1. The Option Setting Memory may be different for each device. Please consult MCU User’s Manual
for the specific device details.

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Figure 6. Option Function Select Registers for RA2A1
4.1 Option Setting Memory Registers
The following is a summary of the Option Setting Memory registers. Make sure that they are configured
properly before startup.
•OFS0 register
Independent Watchdog Timer (IWDT) auto start
IWDT timeout, frequency, windowing, interrupt type, and low power mode behavior
Watchdog Timer (WDT) auto start
WDT timeout, frequency, windowing, and interrupt type
•OFS1 register
LVD0 enable after reset
HOCO startup after reset
Renesas FSP Configurator supports setting of option memory in BSP settings, as shown in Figure 7 for
RA2A1 MCU.

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Figure 7. Option Memory Settings in FSP Configuration for RA2A1 MCU
5. Clock Circuits
Most RA2 MCUs have six primary oscillators. Five of these may be used as the source for the main system
clock. The remaining oscillator is dedicated to the Independent Watchdog Timer. In a typical system, the
main clock is driven with an external crystal or clock. This input is directed to internal selectors and frequency
dividers, where it is further directed to the main system clock (ICLK), flash clock, CPU clock, and peripheral
module clocks. For some devices, the clock distribution also includes additional clocks for ADC and USB
peripherals. Note that RA2E2 devices do not have external crystal or clock input pins. Refer to the Hardware
User’s Manual “Clock Generation Circuit” chapter for the block diagram of the clock generation circuit.
Each clock has specific tolerances and timing values. Refer to the Hardware User’s Manual “AC
Characteristics” section in the “Electrical Characteristics” chapter for the Frequency and Clock Timing
specifications. Refer to the Hardware User’s Manual “Clock Generation Circuit” chapter for the relationship
between the various clock frequencies.

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Table 5. RA2 Oscillators
Oscillator
Input Source
Frequency
Primary Uses
Main clock*4
(MOSC)
External
crystal/resonator
-or-
1 MHz to 20 MHz*3
Main system clock (ICLK), Peripheral
clocks, CAN clock, CAC clock,
CLKOUT, flash clock*3, SDADC
clock*1
External clock
Up to 20 MHz
Sub-clock*4
(SOSC)
External
crystal/resonator
32.768 kHz
Real-time clock, main system clock
(ICLK) in low power modes,
CLKOUT, AGT clock, CAC clock,
Real-time clock
High-speed on-chip
(HOCO)
On-chip oscillator
24/32/48/64 MHz
Main system clock (ICLK), Peripheral
clocks, CAC clock, CLKOUT, USB
clock*2, SDADC clock*1
Middle-speed on-
chip (MOCO)
On-chip oscillator
8 MHz
Main system clock (ICLK) at startup,
Peripheral clocks, CLKOUT, CAC
clock
Low-speed on-chip
(LOCO)
On-chip oscillator
32.768 kHz
Main system clock (ICLK) in low
power modes and during main
oscillator stop detection, Peripheral
clocks, Systick timer, AGT clock,
CLKOUT, CAC clock, Real-time
clock, Independent Watchdog Timer
clock
Independent
Watchdog (IWDT)
On-chip oscillator
15 kHz
Independent Watchdog Timer clock,
CAC clock
Note 1: SDADC clock is only present on RA2A1 devices.
2: USB clock is only present on RA2A1 devices.
3: On RA2A1 devices, the flash clock (FCLK) is driven independently from MOSC, and can be
sourced from MOSC, SOSC, HOCO, MOCO, or LOCO.
4: Not present on RA2E2
Some devices, such as RA2E2, do not include the option for an external crystal or clock. In this case, the
oscillator sources for the main clock are limited to the on-chip oscillators.
5.1 Reset Conditions
After reset, RA2 MCUs begin running with the middle-speed on-chip oscillator (MOCO) as the main clock
source. At reset, the main oscillator is stopped by default. The HOCO and IWDT may be on or off depending
on the settings in the Option Setting Memory (see section 4).
5.2 Clock Frequency Requirements
Minimum and maximum frequencies are shown in the following tables. Details can be found in the
“Overview” section of the “Clock Generation Circuit” chapter in the MCU Hardware User’s Manual, including
external and internal clock source specifications. Additional details can be found in the “AC Characteristics”
section of the “Electrical Characteristics” chapter in the MCU Hardware User’s Manual.
Table 6. Frequency Range for RA2 MCU Internal Clocks
ICLK 4
PCLKB
PCLKD
FCLK 1
UCLK 2
CANMCLK 3
Maximum Frequency [MHz]
48
32
64
32
48
20
Minimum Frequency [MHz]



1
48
1
Note 1: Only on RA2A1. The FCLK must run at a frequency of at least 1 MHz when programming or
erasing ROM or data flash.
2: For devices with USB peripheral function.
3: For devices with CAN peripheral function.
4: For RA2E1, RA2E2 and RA2L1, ICLK must run at a frequency of at least 1 MHz when
programming or erasing ROM or data flash.

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5.2.1 Requirements for USB Communications
The USB 2.0 Full-Speed Module (USBFS) requires a 48-MHz USB clock signal (UCLK).
For RA2 devices with a USBFS Module, the HOCO is the clock source for UCLK. Therefore, the HOCO must
be configured for 48-MHz operation when using the USBFS Module.
5.2.2 Requirements for Programming and Erasing ROM or Data Flash
For RA2A1, the FCLK must be at least 1 MHz to perform programming and erasing on internal ROM and
data flash.
For all other RA2 devices, the ICLK must be at least 1 MHz to perform programming and erasing on internal
ROM and data flash.
5.3 Lowering Clock Generation Circuit (CGC) Power Consumption
To aid in saving power, set the dividers for any unused clocks to the highest possible value whenever
possible. Also, if not using a clock then make sure that it has been stopped by setting the appropriate
register(s). The registers for controlling each clock source are shown in the table below.
Table 7. Clock Source Configuration Registers
Oscillator
Register
Description
Main clock*1
MOSCCR
Starts/stops main clock oscillator
Sub-clock*1
SOSCCR
Starts/stops sub-clock oscillator
High-speed on-chip (HOCO)
HOCOCR
Starts/stops HOCO
Middle-speed on-chip (MOCO)
MOCOCR
Starts/stops MOCO
Low-speed on-chip (LOCO)
LOCOCR
Starts/stops LOCO
Note 1: Not present on RA2E2 devices.
5.4 Writing the System Clock Control Registers
Care should be taken when writing to the individual bit fields in the System Clock Division Control Register
(SCKDIVCR) and System Clock Source Control Register (SCKSCR).
When the clock source of the peripheral module clock is switched, the duration of the peripheral module
clock cycle becomes longer during the clock source transition period. See Figure 8.
To ensure correct processing after the clock frequency changes, first write to the relevant Clock Control
register to change the frequency, then read the value from the register, and finally perform the subsequent
processing.

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Figure 8. Timing of Clock Source Switching
5.5 Clock Setup Example
Renesas FSP provides a simple, visual clock configuration tool for RA2A1 MCU shown as follows. This
configurator configures code in the board support package to initialize the Clock Generation Circuit based on
user selection, with proper precautions as indicated in the MCU hardware user manual.
Figure 9. Clock Settings Using Renesas FSP Configurator
5.6 HOCO Accuracy
The internal high-speed on-chip oscillator (HOCO) runs at 24 MHz, 32 MHz, 48 MHz, or 64 MHz for RA2
devices, with a typical accuracy of +/-2% or better. HOCO accuracy specifications are characterized for
various ambient operating temperature (Ta) ranges. See the “Electrical Characteristics” of the Hardware
User’s Manual for the clock accuracy specifications in the desired temperature range.
The HOCO may be used as an input to the clock generation circuit. When the HOCO is used this way, no
external oscillator is required. This may be an advantage when space constraints or other limitations require

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a reduced component count in a PCB design. However, there are performance tradeoffs and limitations due
to the clock accuracy which should be evaluated for your application.
For RA2E2 devices, there are is no external crystal or external clock input. An internal clock (HOCO, MOCO,
or LOCO) must be selected as the main system clock.
5.7 Flash Interface Clock
On RA2A1 devices, the Flash interface Clock (FCLK) is used as the operating clock when programming and
erasing internal flash (ROM and DF) and for reading from the data flash. For other RA2 devices, ICLK is
used as the operating clock when programming and erasing the internal flash.
Therefore, the frequency setting of the relevant clock will have a direct impact on the amount of time it takes
to read from the data flash. If the user’s program is reading from the data flash, or performing programming
or erasures on internal flash, then using the maximum FCLK or ICLK frequency is recommended.
The flash programming clock must run at a frequency of at least 1 MHz when writing or erasing ROM or data
flash. Please note that the clock frequency does not have any impact upon reading from ROM or reading and
writing to RAM.
5.8 Board Design
Refer to the “Usage Notes” section of the Clock Generation Circuit (CGC) chapter in the Hardware User’s
Manual for more information on using the CGC and for board design recommendations.
In general, place the crystal resonator and its load capacitors as close to the MCU clock pins (XTAL/EXTAL,
XCIN/XCOUT) as possible. Avoid routing any other signals between the crystal resonator and the MCU.
Minimize the number of connecting vias used on each trace.
5.9 External Crystal Resonator selection
An external crystal resonator may be used as the main clock source for most RA2 devices. The external
crystal resonator is connected across the EXTAL and XTAL pins of the MCU. The frequency of the external
crystal resonator must be in the frequency range of the main clock oscillator.
Selection of a crystal resonator will be largely dependent on each unique board design. Due to the large
selection of crystal resonators available that may be suitable for use with RA2 MCU devices, carefully
evaluate the electrical characteristics of the selected crystal resonator to determine the specific
implementation requirements.
The following diagram shows a typical example of a crystal resonator connection.
Figure 10. Example of Crystal Resonator Connection
Careful evaluation must be used when selecting the crystal resonator and the associated capacitors. The
external feedback resistor (Rf) and damping resistor (Rd) may be added if recommended by the crystal
resonator manufacturer.

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Figure 11. Equivalent Circuit of the Crystal Resonator
Selection of the capacitor values for CL1 and CL2 will affect the accuracy of the internal clock. To
understand the impact of the values for CL1 and CL2, the circuit should be simulated using the equivalent
circuit of the crystal resonator in the figure above. For more accurate results, also take in to account the stray
capacitance associated with the routing between the crystal resonator components.
5.10 External Clock Input
A digital clock input may be used as the main clock source for most RA2 devices. Figure 12 shows an
example of connecting an external clock input. To operate the oscillator with an external clock signal, set the
MOMCR.MOSEL bit to 1. The XTAL pin becomes high impedance.
Figure 12. Equivalent circuit for external clock
Notes: The frequency of the external clock input can only be changed when the main clock oscillator is
stopped. Do not change the frequency of the external clock input when the setting of the Main Clock
Oscillator Stop bit (MOSCCR.MOSTP) is 0.
6. Reset Requirements and the Reset Circuit
There are 12 or 13 types of resets for Arm®Cortex-M23 devices.

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Table 8. RA2 Device Resets
Reset Name
Source
Pin reset
RES# is driven low
Power-on reset
VCC rises (voltage detection: VPOR)
Independent watchdog timer reset
The independent watchdog timer underflows, or a refresh occurs
Watchdog timer reset
The watchdog timer underflows, or a refresh occurs
Voltage monitor 0 reset
VCC falls (voltage detection Vdet0)
Voltage monitor 1 reset
VCC falls (voltage detection Vdet1)
Voltage monitor 2 reset
VCC falls (voltage detection Vdet2)
SRAM parity error reset
SRAM parity error detection
SRAM ECC error reset*1
SRAM ECC error detection
Bus master MPU error reset
Bus master MPU error detection
Bus slave MPU error reset
Bus slave MPU error detection
Stack pointer error reset
Stack pointer error detection
Software reset
Register setting
Note 1: Not present on RA2E1 or RA2E2 devices.
6.1 Pin Reset
When the RES# pin is driven low, all processing is aborted and the MCU enters a reset state. To reset the
MCU while it is running, RES# should be held low for the specified reset pulse width. Refer to the “Reset
Timing” section of the “Electrical Characteristics” chapter of the Hardware User’s Manual for more detailed
timing requirements. Also refer to section 2 of this document, “Emulator Support” for details on reset circuitry
in relation to debug support.
There is no need to use an external capacitor on the RES# line because the POR circuit holds it low
internally for a good reset and a minimum reset pulse is required to initiate this process.
6.2 Power-On Reset
There are two conditions that will generate a power-on reset (POR):
1. If the RES# pin is in a high-level state when power is supplied.
2. If the RES# pin is in a high-level state when VCC is below VPOR.
After VCC has exceeded the power-on reset voltage (VPOR) and the power-on reset time (tPOR) has elapsed,
the chip is released from the power-on reset state. The power-on reset time is a period that allows for
stabilization of the external power supply and the MCU. Refer to the “POR and LVD Characteristics” section
of the “Electrical Characteristics” chapter of the Hardware User’s Manual for voltage level and timing details.
Because the POR circuit relies on having RES# high concurrently with VCC, don’t place a capacitor on the
reset pin. This will slow the rise time of RES# in relation to VCC, preventing the POR circuit from properly
recognizing the power-on condition.
If the RES# pin is high when the power supply (VCC) falls to or below VPOR, a power-on reset is generated.
The chip is released from the power-on state after VCC has risen above VPOR and the tPOR has elapsed.
After a power on reset, the PORF bit in RSTSR0 is set to 1. Following a pin reset, PORF is cleared to 0.
6.3 Independent Watchdog Timer Reset
This is an internal reset generated by the Independent Watchdog Timer (IWDT).
When the IWDT underflows, an independent watchdog timer reset is optionally generated (NMI can be
generated instead) and the IWDTRF bit in RSTSR1 is set to a 1. After a short delay the IWDT reset is
canceled. Refer to MCU User’s Manual for the specific timing.
6.4 Watchdog Timer Reset
This is an internal reset generated by the Watchdog Timer (WDT).
When the WDT overflows, a watchdog timer reset is optionally generated (NMI can be generated instead),
and the WDTRF bit in RSTSR1 is set to a 1. After a short delay the WDT reset is canceled. Refer to MCU
User’s Manual for the specific timing.

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6.5 Voltage-Monitoring Resets
The RA2 MCU family includes circuitry that allows the MCU to protect against unsafe operation during
brownouts. On-board comparators check the supply voltage against three reference voltages, Vdet0, Vdet1,
and Vdet2. As the supply dips below each reference voltage an interrupt or a reset can be generated. The
detection voltages Vdet0, Vdet1, and Vdet2 are each selectable from 3 different levels.
When VCC subsequently rises above Vdet0, Vdet1, or Vdet2, release from the voltage-monitoring reset proceeds
after a stabilization time has elapsed.
Low Voltage Detection is disabled after a power on reset. Voltage monitoring can be enabled by using the
Option Function register OFS1. For more details, see the chapter “Low Voltage Detection (LVD)” in the
Hardware User’s Manual.
After an LVD Reset, the LVDnRF (n = 0, 1, 2) bit in RSTSR0 is set to 1.
6.6 Software Reset
The software reset is an internal reset generated by a software setting of the SYSRESETREQ bit in the
AIRCR register in the Arm core. When the SYSRESETREQ bit is set to 1, a software reset is generated.
When the internal reset time (tRESW2) elapses after the software reset is generated, the internal reset is
canceled and the CPU starts the reset exception handling. Refer to MCU User’s Manual for the specific
timing.
For details on the SYSRESETREQ bit, see the ARM® Cortex®-M23 Technical Reference Manuals.
6.7 Other Resets
Most peripheral functions within the MCU can generate a reset under specific fault conditions. No hardware
configuration is required to enable these resets. Refer to the relevant chapters in the Hardware User’s
Manual for details of the conditions that will generate a reset for each peripheral function.
6.8 Determination of Cold/Warm Start
The RA2 MCUs allow the user to determine the cause of the reset processing. The CWSF flag in RSTSR2
indicates whether a power on reset caused the reset processing (cold start) or a reset signal input during
operation caused the reset processing (warm start.)
The flag is set to 0 when a power on reset occurs. Otherwise, the flag is not set to 0. The flag is set to 1
when 1 is written to it through software. It is not set to 0 even when 0 is written to it.
6.9 Determining the Reset Source
The RA2 MCUs allow the user to determine the reset signal generation source. Read RSTSR0, RSTSR1,
and RSTSR0 to determine which reset was the source of the reset. Refer to the Hardware User’s Manual
section “Determination of Reset Generation Source” for the flow diagram.
The following sample code shows how to determine if a reset is caused by Power On Reset or Software
Reset using CMSIS based register structure in Renesas FSP.
/* Power on Reset */
if(1 == R_SYSTEM->RSTSR0_b.PORF)
{
/* Do something */
}
/* Software Reset */
if(1 == R_SYSTEM->RSTSR1_b.SWRF)
{
/* Do something */
}

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7. Memory
7.
The RA2 MCUs support a 4-GB linear address space ranging from 0000 0000h to FFFF FFFFh that can
contain program, data, and external memory bus. Program and data memory share the address space.
Separate buses are used to access each, increasing performance and allowing same-cycle access of
program and data. Contained within the memory map are regions for on-chip RAM, peripheral I/O registers,
program code flash, and data flash.
Figure 13. RA2A1 Memory Map
7.1 SRAM
The RA2 MCUs provide on-chip SRAM modules with either parity-bit checking or ECC (Error Correction
Code). The following table lists the SRAM specifications for RA2A1 MCU. The SRAM capacity varies by
device. Consult the Hardware User’s Manual for specifics.