Renesas RA Family RA2 Quick Design Guide
R01AN6060EU0100 Rev.1.00 Page 2 of 44
Sep.14.21
6.3 Independent Watchdog Timer Reset.....................................................................................................18
6.4 Watchdog Timer Reset..........................................................................................................................18
6.5 Voltage-Monitoring Resets....................................................................................................................19
6.6 Software Reset......................................................................................................................................19
6.7 Other Resets .........................................................................................................................................19
6.8 Determination of Cold/Warm Start ........................................................................................................19
6.9 Determining the Reset Source..............................................................................................................19
7. Memory .................................................................................................................................20
7.1 SRAM....................................................................................................................................................20
7.2 Peripheral I/O Registers........................................................................................................................21
7.3 On-Chip Flash Memory .........................................................................................................................21
7.3.1 Background Operation ........................................................................................................................22
7.3.2 ID Code Protection..............................................................................................................................22
7.3.3 Memory Protection Unit.......................................................................................................................23
7.4 Restriction on Endianness.....................................................................................................................24
8. Register Write Protection.......................................................................................................24
9. I/O Port Configuration ...........................................................................................................25
9.1 Multifunction Pin Selection Design Strategies.......................................................................................25
9.2 Setting Up and Using a Port as GPIO...................................................................................................25
9.2.1 Internal Pull-Ups..................................................................................................................................27
9.2.2 Open-Drain Output..............................................................................................................................27
9.2.3 Drive Capacity.....................................................................................................................................27
9.3 Setting Up and Using Port Peripheral Functions...................................................................................27
9.4 Setting Up and Using IRQ Pins.............................................................................................................28
9.5 Unused Pins..........................................................................................................................................30
9.6 Nonexistent Pins....................................................................................................................................31
9.7 Electrical Characteristics.......................................................................................................................31
10. Module Stop Function............................................................................................................31
11. Interrupt Control Unit .............................................................................................................31
12. Low Power Consumption.......................................................................................................33
13. Buses ....................................................................................................................................36
13.1 Bus Error Monitoring..............................................................................................................................37
13.1.1 Bus Error Types...................................................................................................................................37
13.1.2 Operation When a Bus Error Occurs...................................................................................................37
14. 24-Bit Sigma-Delta A/D Converter (SDADC24)......................................................................37
15. Operational Amplifier (OPAMP) with Configurable Switches..................................................39
