Samsung SGH-V100 User manual

SGH-V100
SERVICE
Manual
GSMTELEPHONECONTENTS
1.Specification
2.CircuitDescription
3.FlowChartofTroubleshooting
4.ExplodedViewsand PartsList
5.ElectricalPartsList
6.BlockDiagrams
7.PCB Diagrams
GSMTELEPHONE

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1.SGH-V100 Specification
1-1
GSM900
Phase1EGSM900 Phase2DCS1800 Phase1PCS1900
Freq.Band[MHz]
Uplink/Downlink 890~915 935~960 880~915 925~960 1710~1785 1805~1880 1850~1910 1930~1990
ARFCNrange1~124 0~124 &
975~1023 512~885 512~810
Tx/Rxspacing 45MHz45MHz95MHz80MHz
Mod.Bit rate/
Bit Period 270.833kbps 3.692us270.833kbps 3.692us270.833kbps 3.692us270.833kbps 3.692us
TimeSlot
Period/FramePeriod 576.9us 4.615ms576.9us 4.615ms576.9us 4.615ms576.9us 4.615ms
Modulation 0.3GMSK0.3GMSK0.3GMSK0.3GMSK
MS Power33dBm~13dBm33dBm~5dBm30dBm~0dBm30dBm~0dBm
PowerClass 5pcl~15pcl5pcl~19pcl0pcl~15pcl0pcl~15pcl
Sensitivity-102dBm-102dBm-100dBm-100dBm
TDMAMux 8 8 8 8
Cell Radius35Km35Km2Km-
1. GSMGeneralSpecification

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1-2
SGH-V100 Specification
TXPower
control levelGSM900
5 33±2 dBm
6 31±2 dBm
7 29±2 dBm
8 27±2 dBm
9 25±2 dBm
10 23±2 dBm
11 21±2 dBm
12 19±2 dBm
13 17±2 dBm
14 15±2 dBm
15 13±2 dBm
16 11±3 dBm
17 9±3dBm
18 7±3 dBm
19 5±3 dBm
TXPower
control levelDCS1800
0 30±3 dBm
1 28±3 dBm
2 26±3 dBm
3 24±3 dBm
4 22±3 dBm
5 20±3 dBm
6 18±3 dBm
7 16±3 dBm
8 14±3 dBm
9 12±4 dBm
10 10±4 dBm
11 8±4dBm
12 6±4 dBm
13 4±4 dBm
14 2±5 dBm
15 0±5 dBm
TXPower
control levelPCS1900
0 30±3 dBm
1 28±3 dBm
2 26±3 dBm
3 24±3 dBm
4 22±3 dBm
5 20±3 dBm
6 18±3 dBm
7 16±3 dBm
8 14±3 dBm
9 12±4 dBm
10 10±4 dBm
11 8±4dBm
12 6±4 dBm
13 4±4 dBm
14 2±5 dBm
15 0±5 dBm
2. GSMTXpower class

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2.SGH-V100 CircuitDescription
2-1
1.SGH-V100 RFCircuit Description
1)RXPART
1. ASM(F950)→Switching Tx, Rx pathforGSM900, DCS1800 and PCS1900 by logic controlling.
2. ASMControlLogic(U701, U702, U703)→TruthTable
VC1VC2VC3
GSMTxModeHL L
DCS/PCSTxModeLHL
PCSRxModeL L H
GSM/DCSRxModeLLL
3. SAWFILTER
ToconvertElectromagneticFieldWavetoAcoustic Wave and then pass thespecificfrequency band.
-PCS SAWFILTER(F951)
==> For filtering thefrequency band between 1930 and 1990MHz
4. TC-VCXO (U703)
To generatethe13MHzreference clockto drivethelogic and RF.
Afteradditionalprocess,thereference clockappliestotheU900 RxIQdemodulatorand TxIQmodulator.
Theoscillator forRXIQdemodulatorand Txmodulatorare controlledbyserialdatatoselectchanneland usefast lock
modeforGPRShigh class operation.
5. Si4200 (U901)
Thischipintegratesthree differential-inputLNAs.
TheGSMinputsupportstheE-GSM,DCSinputsupportstheDCS1800, PCSinputsupportsthePCS1900. TheLNA
inputsarematchedtothe200 ohmdifferentialoutputSAWfiltersthrough eternalLCmatching network.
Image-reject mixerdownconvertstheRFsignal toa100 KHzintermediatefrequency(IF)withtheRFLOfromSI4133T
frequencysynthesizer.TheRFLOfrequencyisbetween 1737.8 ~1989.9 MHz.
TheMixeroutput isamplifiedwithananalog programmablegainamplifier(PGA),whichiscontrolled by AGAIN.
ThequadratureIFsignal isdigitizedwith high resolution A/Dconverts(ADC).
6. Si4201 (U900)
TheSI4201 down-convertstheADCoutput to baseband withadigital100 KHzquadratureLOsignal.Digitaldecimation
and IIRfiltersperformchannelselection toremoveblocking and reference interface signals.
Afterchannelselection, thedigitaloutput is scaledwithadigitalPGA,whichiscontrolledwiththeDGAIN.DACsdrive
adifferentialanalog signalontotheRXIP,RXIN,RXQP,RXQN pinstointerface tostandardanalog-inputbaseband IC.

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2-2
SGH-V100 Circuit Description
2)TXPART
Baseband IQsignalfedinto offsetPLL,thisfunction isincludedinsideofU902 chip.
SI4200 chip generatesmodulatorsignalwhich powerlevel isabout1.5dBmand fedintoPowerAmplifier(U951).
ThePAoutputpowerand power ramping arewell controlledbyAuto
PowerControlcircuit.We useoffsetPLL below
Modulation Spectrum
200kHzoffset
30 kHzbandwidth
GSM-35dBc
DCS-35dBc
PCS-35dBc
400kHzoffset
30 kHzbandwidth
GSM-66dBc
DCS-65dBc
PCS-66dBc
600kHz~1.8MHzoffset
30 kHzbandwidth
GSM-75dBc
DCS-68dBc
PCS-75dBc
2. Baseband CircuitdescriptionofSGH-V100
1.PSC2006
1.1. PowerManagement
Sevenlow-dropoutregulatorsdesignedspecificallyforGSMapplicationspowertheterminaland helpensureoptimal
systemperformance and long batterylife.Aprogrammableboostconverterprovides supportfor1.8V, 3.0V,and 5.0V
SIMs,while a self-resetting, electronicallyfusedswitchsuppliespowertoexternalaccessories.Ancillarysupportfunctions,
suchasanLEDdriverand twocall-alertdrivers,aidinreducing both boardarea and systemcomplexity.
Athree-wireserial interface unit(SIU)providesaccess tocontroland configuration registers.Thisinterface givesa
microprocessor full controlofthePSC2006 and enables systemdesignerstomaximize bothstandby and talktimes.
Supervisoryfunctions.including aresetgenerator,aninputvoltagemonitor,and athermal monitor,supportreliablesystem
design. Thesefunctionsworktogethertoensurepropersystembehaviorduring start-up orinthe eventofafault
condition(lowmicroprocessorvoltage,insufficientbatteryenergy, orexcessivedietemperature).
1.2. BatteryChargeManagement
Abatterychargemanagementblock providesfast,efficientcharging ofasingle-cell Li-ion battery. Usedinconjunction
witha current-limited voltagesource and anexternalPMOSpass transistor,thisblocksafelyconditionsnear-deadcells
and providestheoption ofhaving fast-charge and top-off controlledinternally orby thesystem'smicroprocessor.
1.3. BacklightLED Driver
ThebacklightLEDdriverisalow-side, programmable currentsource designedtocontrol thebrightness ofthekeyboard
and LCDillumination. ThedriverisenabledbyEN_LED,and itscurrentsetting isdeterminedbyLED[0:2].Provided
EN_LEDis‘1’,thedrivercan beprogrammedtosink from12.5mAto 100mAin 12.5mAsteps.LED_DRVis
capableofsinking 100mAataworst-casemaximumoutputvoltageof0.6V.Forefficientuse,theLEDsisconnected
betweenthebatteryand theLED_DRVoutput.

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SGH-V100 Circuit Description
2-3
1.4. VibratorMotorDirver
Thevibratormotordriverisalow-side, programmablevoltagesource designedto drive a small dcmotorthatsilently
alertstheuserofanincoming call.ThedriverisenabledbyEN_VIB,and itsvoltagesetting isdeterminedbyVIB[0:2].
ProvidedEN_VIBisalogic1, thedrivercan beprogrammedtomaintainamotorvoltageof1.1Vto 2.5Vin 20mV
stepsand whilesinking up to 100mA.Forefficientuse,thevibratormotorshould be connected betweenthemain battery
and theVIB_DRVoutput.
2.Connector
2-1. LCDConnector
LCDisconsisted ofmainLCD(color65KSTNLCD)and small LCD(4-grayLCD).ChipselectsignalsofEMIpart in
thetrident,CLCD_EN_FOand GLCD_EN_FO,canenableEachLCD.LED_EN_FOsignalenableswhiteLEDofmain
LCDand EL_EN_FOsignalenablesEL ofsmall LCD.ThesetwosignalsarefromIOpartoftheDSP inthetrident.
RSTsignalfrom2006 initiatestheinitialprocess oftheLCD.
16-bit datalines(D(0)_FO~D(15)_FO)transfersdata and commandstoLCDthrough emi_filter.Data and commandsuse
A(2)_FOsignal.If this signal ishigh, InputstoLCDare commands.If it islow,InputstoLCDaredata.Thesignal
whichinformstheinputoroutputstatetoLCD,isrequired. But this system isnotnecessarythis signal.So
CP_WEN_FOsignal isusedtowritedataorcommandstoLCD.PowersignalsforLCDareV_batand V_ccd.
SPK1Pand SPK1NfromCSP1093 areusedforaudiospeaker.And VIB_EN_FOfromenablesthemotor.
2-2. JTAG Connector
TridenthastwoJTAG portswhichareforARMcore and DSP core(DSP16000).Sothis systemhastwo portconnector
fortheseports.Pins’initialsforARMcore are‘CP_’and pins’initialsforDSP core are‘DSP_’.CP_TDIand
DSP_TDIsignalareusedforinputofdata.CP_TDO and DSP_TDO signalsareusedfortheoutputofthedata.CP_TCK
and DSP_TCKsignalsareusedforclock becauseJTAG communication isasynchronous.CP_TMSand DSP_TMS
signalsaretest modesignals.Thedifference betweentheseistheRESET_INTsignalwhichisforARMcoreRESET.
2-3. IRDA
This systemusesIRDA module,HSDL_3201, HP’s.Thishas signals,IRDA_EN(enablesignal),IRDA_RX(inputdata)
and IRDA_TX(outputdata).Thesesignalsare connectedtoPPIoftrident.Itusestwo powersignals.V_ccdisusedfor
circuit and V_bat isusedforLED.
2-4. Keypadconnector
Thisisconsisted ofkeyinterface pinsamong PPIinthetrident,KEY_ROW[0~4]and KEY_COL[0~4].Thesesignals
composethematrix. Result ofmatrixinformsthekeystatusto keyinterface inthetrident.Somepinsare connectedto
varistor forESDprotection. And poweron/off keyis seperatedfrom thematrix. So poweron/off signal isconnectedwith
PSC2006 toenablePSC2006. SVC_GREEN,SVC_REDand SVC_BLUEarefromOCTL ofCSP1093. Thesesignals
decidethe colorofLED,service indicator.Eighteen keyLEDusetheV_batsupply voltage.These are connectedto
BACKLIGHTsignal inthePSC2006. This signalenablesLEDswithcurrentcontrol.FLIP_SNSinformsthestatusof
folder (open orclosed)tothetrident.Thisusesthehall effectIC,A3210ELH.AmagnetundermainLCDenables
A3210ELH whichison thekeyFPCB.

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2-4
SGH-V100 Circuit Description
3.IFconnetor
It is18-pinconnector,and uses18-pinatpresent.Theyaredesignedto useSDS,DEBUG,DLC-DETECT,JIG_ON,
VEXT,VTEST,VF,CF,VBATand GND.Theyconnectedto powersupplyIC,microprocessorand signalprocessor IC.
4.Audio
AOUTAPfromCSP1093 isconnectedtothemainspeaker.AOUTAN isconnectedtothespeakervia audio-amp.
AOUTBNand AOUTBPare connectedtothe ear-micspeakervia ear-jack. MICINand MICOUTare connectedtothe
mainMIC.And AUXINand AUXOUTare connectedtotheEar-mic.
YMU762MA3isaLSI forportabletelephonethat iscapableofplaying high qualitymusicby utilizing FM synthesizer
and ADPCMdecorderthatareincludedinthisdevice.
Asasynthesis,YMU762MA3isequipped 16 voiceswith differenttones.Since thedevice iscapableofsimultaneously
generating up tosynchronouswiththeplay oftheFM synthesizer, various sampled voicescan beusedas sound effects.
Since theplay dataofYMU762MA3areinterpretedatanytimethrough FIFO,thelength ofthedata(playing period)is
not limited, sothedevice canflexiblysupportapplication suchasincoming call melody musicdistribution service.The
hardwaresequencerbuilt inthisdevice allowsplaying ofthe complexmusicwithoutgiving excessiveloadtotheCPUof
theportabletelephones.Moreover,theregistersoftheFM synthesizercan beoperated directlyfor real timesound
generation, allowing, forexample, utilization ofvarious sound effectswhen using thegamesoftwareinstalledinthe
portabletelephone.
YMU759 includesaspeakeramplifierwith high rippleremovalratewhosemaximumoutput is550mW(SPVDD=3.6V).
Thedevice isalsoequippedwithconventionalfunction including avibartorand a circuit forcontrolling LEDs
synchornouswithmusic.
Fortheheadphone,it isprovidedwithastereophonicoutput terminal.
Forthepurposeofenabling YMU762MA3to demonstarteitsfull capablities,Yamahapurposeto use"SMAF:Synthetic
musicMobileApplication Format"asadatadistribution format that iscompatiblewiht multimedia.Since theSMAFtakes
astructurethatsetsimportance on thesynchronization betweensound and images, variouscontentscan bewrittenintoit
including incoming call melody withwordsthatcan beusedfortraning karaoke,and commercialchannel thatcombines
texts,imagesand sounds,and others.ThehardwaresequencerofYMU762MA3 directlyinterpretsand playsblocks
relevant tosysthesis(playing music and reproducing ADPCMwithFM synthesizer) thatareincludedin datadistributedin
SMAF.
5.Memory
This systemusesIntel’smemory, 28F6408W30BH70. It isconsisted of64Mbitsflashmemoryand 8MbitsSRAM.It
has16 bit dataline,D[0~15]whichisconnectedtotrident,LCDorCSP1093. Ithas22 bit address lines,A[1~22].They
are connectedtoo. CP_CSROMENand CO_CSROM2ENsignals,chipselectsignalsinthetridentenabletwomemories.
They use3 volt supply voltage,V_ccdand 1.8 volt supply voltage,Vcc_1.8ainthePSC2006. During wrting process,
CP_WENislowand it enableswriting process toflashmemoryand SRAM.During reading process,CP_OENislow
and it output information whichislocatedat the address from thetrident intheflashmemory orSRAMto datalines.
Eachchipselectsignalsinthetridentselect memoryamong 2 flashmemoryand2SRAM.Reading orwriting procedure
isprocessedafterCP_WENorCP_OENisenabled. MemoriesuseFLASH_RESET,whichisbufferedsignalofRESET
fromPSC2006, forESDprotection. A[0]signalenableslowerbyteofSRAMand UPPER_BYTE signalenableshigher
byteofSRAM.

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SGH-V100 Circuit Description
2-5
6. Trident
Trident isconsisted ofARMcore and DSP core.Ithas20K*16bitsRAM144K*16bitsROMintheDSP.Ithas
4K*32bitsROMand 2K*32bitsRAMintheARMcore.DSP isconsisted oftimer, onebit input/outputunit(BIO),JTAG,
EMIand HDS(HardwareDevelopmentSystem).ARMcoreisconsisted ofEMI,PIC(ProgrammableInterruptController),
reset/power/clock unit,DMAcontroller,TIC(TestInterface Controller), peripheralbridge,PPI,SSI(SynchronousSerial
Interface),ACC(Asynchronouscommunicationscontrollers),timer,ADC,RTC(Real-TimeClock)and keyboardinterface.
DSP_AB[0~8],address linesofDSP core and DSP_DB[0~15], datalinesofDSP core are connectedtoCSP1093.
A[0~20],address linesofARMcore and D[0~15], datalinesofARMcore are connectedtomemory, LCDand YMU759.
ICP(InterprocessorCommunication Port)controlsthe communication betweenARMcore and DSP core.
CSROMEN,CSRAMENand CS1NtoCS4NintheARMcore are connectedtoeachmemory. WENand OENcontrol
theprocess ofmemory. ExternalIRQ(InterruptReQuest)signalsfromeach units,suchas,YMU,Ear-jack, Ear-mic and
CSP1093, needthe compatibleprocess.
SomePPIpinshasmany specialfunctions.CP_KB[0~9] receivethestatusfromkeyFPCB and areusedforthe
communicatiosusing IRDA(IRDA_RX/TX/EN)and datalink cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR).And
UP_CS/SCLK/SDI,controlsignalsforPSC2006 areoutputtedthrough PPIpins.Ithas signalportforcharging(CHG_DET,
CHG_STAT0),SIM_RESET and FLIP_SNSwithwhichweknowsopen.closedstatusof folder.Ithas JTAG control
pins(TDI/TDO/TCK) forARMcore and DSP core.Itrecieves13MHz clockinCKIpinfromexternalTCXO and receives
32.768KHz clockfromX1RTC.ADC(Analog toDigitalConvertor) partreceivesthestatusoftemperature, batterytype
and battery voltage.And controlsignals(DSP_INT,DSP_IOand DSP_RWN) forDSP core areused. ItenablesmainLCD
and small LCD withDSP IPpins.
7. CSP1093
CSP1093 integratesthetiming and controlfunctionsforGSM2+mobile application withtheADCand DACfunctions.
TheCSP1093 interfacestothetrident, via a 16-bit parallel interface.Itservesastheinterface thatconnectsaDSP tothe
RFcircuitryinaGSM2+mobiletelephone.DSP canload 148 bitsofburstdataintoCSP1093’sinternalregister,and
programCSP1093’sevent timing and controlregisterwiththe exact timetosend theburst.Whenthetiming portion of
the event timing and controlregistermatchestheinternalquarter-bit counterand internalframe counter,the148 bitsin
theinternalregisterareGMSKmodulatedaccording toGSM2+standards.Theresulting phaseinformation istranslated
intoIand Qdifferentialoutputvoltagesthatcan be connected directlytoanRFmodulatorat theTXOPand TXON pins.
TheDSP isnotifiedwhenthetransmission iscompleted. For receiving baseband data,aDSP can programCSP1093’s
event timing and controlregisterwiththe exact timetostartreceiving Iand Qsamplesthrough TXIPand TXINpins.
Whenthat timeisreached, the controlportion ofthe event timing and controlregisterwill start thebaseband receive
section converting Iand Qsamplepairs.Thesamplesarestoredinadouble-bufferedregisteruntil theregistercontains
32 samplepairs.CSP1093 then notifiestheDSP which hasampletimetoreadtheinformation outbeforethenext32
samplepairsarestored. Thevoice band ADCconverterissuesaninterrupt totheDSP wheneverit finishesconverting a
16-bit PCMword. TheDSP thenreadsthenewinputsample and simultaneouslyloadsthevoice band outputDAC
converterwithanewPCMoutputword. Thevoice band outputcan be connected directlytoaspeakerviaAOUTAN and
AOUTAPpinsand be connectedtoaEar-micspeakerviaAOUTBNand AOUTBPpins.
8. X-TAL(13MHz)
This systemusesthe13MHzTCXO,TCO-9141B,Toyocom.AFCcontrolsignalformCSP1093 controlsfrequencyfrom
13MHzx-tal.Itgeneratesthe clockfrequency. Thisclockisinvertedthrough NOTgate,TC7S04FUand isconnectedto
CSP1093. 13MHz clockforYMU759 usesanot-invertedclock. ClockforRFpartsuses sametype.

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2-6
SGH-V100 Circuit Description
3.VideoOndemand descriptionofSGH-V100
1)ECD(A3)
ECD(A3)isanapplication and multi-mediaprocessortargetedforthemobilemarket.Thisincludescell phone,PDAsand
accessories.The chipscanservemobile applicationsregardless ofthe cellulartechnology itself.It isafull duplexA/V
codec assembledwithalargevariety ofapplication. Application islikethis.Streaming isvideoand audio. Capturing is
videoand digitalstill.Playing isaudio, videoand still picture.The chipsupportsthefollowing standardand
recommendations.It is MPEG-4, H.263, MP3, G.7231, GSM-AMRand ACC,WMFRTFD1.0, 3GPP Packet-Switched
Streaming Service(26.234)Release4.
Thesolution isbasedontheARMplatformasahigh-performance,fully programmable coreprocessor,withthe addition
ofvideocapture and videoencoding acceleratorand displayH/Wblocksforenhancing performance and quality, and
reducing powerconsumption ofthetotalsolution.
ThemajorblocksinECD(A3)are asfollows:
-ARM920 MacroCell
-256KBOn-chipSRAMDataMemory
-4 x 40KBFramebuffers
-HostInterface(HIF)
-ExternalBusInterface(EBI)
-AudioInterface(AIF)
-VideoCaptureUnit(VCU)
-Motion Estimation unit(MEU)
-DisplayUnit(DU)
-UART
-I2C
-16 GerneralPurposeInputs/Outputs(GPIO)
-RealTimeClock(RTC)
-InterruptControlUnit(ICU)
-PowerManagementunit
2)OSD
OSD(LC78715)isasystemLSIto output moviefromECD(A3)withOSDtoLCDpanel.Outputdata consistsofdigital
65536 colorsmoviedata and 256 colorOSD.
OSD(LC78715)hasRGBpicturememory(formovie and picture176 x 220 x 16 bit)and2OSDframememories(176 x
220 x 8 bit).
-Features
-LCDI/F
driverLC13002 isavailable
-CPU(TRIDENT)I/F
Address has17 bitswidth. Datahas16 bitswidth. WhentheMsbit ofaddress is"1, CPU(TRIDENT)can
access(write/read) registers.WhentheMsbit ofaddress is"0",CPUcanaccess framememories.Databiswidthis
selectable16bit or8bit.
-ECD(movie engine)I/F
-OSDblockcopy function

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SGH-V100 Circuit Description
2-7
RectangleOSDdatainaframememorycan be copiedtoanotherplace by OSDblockcopy function. Thisfunction
isavailablebothininter frame copy and inintraframe copy.
-Systemclock
Systemclockis27 MHz.
3)CODEC(STW5094)
CODEC(STW5094)isalowpowerStereoAudioDACdevice withHeadphonesAmplifiersforhigh qualityMP3and FM
radiolistening. TheSTW5094 includesalsoan high performance lowpowercombinedPCMCODEC/FILTERtailoredto
implement the audiofront-end functionsrequiredbylowvoltagelowpowerconsumption digitalcellularterminalswith
addedMP3and FMradiolistening.
STW5094 offersanumberofporgrammablefunctionsaccessedthrough anI2C-buscompatibleinterface.TheSTW5094
StereoAudioDACsection is suitedforMP3, orany otherstereosource,listening. Itsupportsall theMP3ratesfrom
8kHzto 48kHz.The audio dataserial interface isI2scompatible and can beprogrammedto handle16 to 24 bit word
lengthinputdata.TheinternalDtoAconvertersworkwith 18bit inputresolution. TheSTW5094 Voice Codec section
can be configuredeitherasa14-bit linearorasan 8-bit compandedPCMcoder.TheVoice Codec can be eitherthe
standard 8kHzvalueorthe extended 16kHzone.Inaddition totheStereoAudioDACand CODEC/FILTERfunction,
STW5094 includesaTone/Ring/DTMFgeneratorthatcan beused bothinAudioListening mode and inVoice Codec
mode,asidetone controlfunction tailoredto handle anexternalon-hook off-hook button.
4)FLASHMEMORY(INTEL)
The3-Volt Advanced+BootBlockFlashMemory product lineisahigh performance memory utilize reliable.This
FLASHmemoryfeature1.65V-2.5Vor2.7V-3.6VI/Osand alow Vcc/Vpp operating rangeof2.7V-3.6VforRead,
Program,and Eraseoperations.Buswidth ofthismemoryis16bit.A3chipismultimediaprocessor,thereforeA3chip
needsoperation program.Theprogram is storedthismemorybyDownloaderPGM.A3systemusesIntel'sthismemory,
GE28F160C3BC70. It isconsisted of16Mbitsflashmemory. Ithas16 bit dataline,D[0~15]whichisconnectedtoA3
chipIthas20 bit address lines,A[1~20].Theyare connectedtoo. _XCSO,chipselectsignalsintheA3chipenablethis
memory. Thisuses3 volt supply voltage.During writing process, _X_WRislowand it enableswriting process toflash
memory. During reading process, _X_RDislowand it output information whichislocatedat the address from theA3
chipintheflashmemory. Reading orwriting procedureisprocessedafter_X_WRor_X_RDis
5)NAND FLASHMEMORY(K9F5608U08-DIB0)
Thismemory offeredin 32Mx8bit,theK9F5608U08-DIB0is256Mbit with *Mbit capacity. Thedevice isofferedin 3
Volt Vcc.ItsNAND cell providesthemostcost-effectivesolution forthesolidstatemass storagemarket.Aprogram
operation programsthe528-bytepageintypical200usec and aneraseoperation can beperformedintypical2msec on a
16K-byteblock. Datainthepage can beread outat50nsec cycletimeperword. TheI/Opins serve astheportsfor
address and datainput/outputaswell ascommand input.Theon-chipwrit controlautomatesall programand erase
functionsincluding pulserepetition, whererequired, and internalverification and margining ofdata.Thismemoryisan
optimumsolution forlargenonvolatilestorage applications suchsolidstatefilestorage and otherportable applications
requiring non-volatility. A3systemusesSAMSUNG Semiconductor'smemory, K9F5608U08-DIB0. It isconsisted of256M
bitsNAND flashmemory. Multimedia contents(MPEGand MP3)arestoredthismemory by downloaderProgram.Ithas
8bit I/Oline,XD[0~7]whichisconnectedtoA3chipThesepins'sfunction areusedtoinputcommand, address and data,
and to outputdataduring read operations.TheI/Opinsfloat to high-zwhenthe chipisdeselected orwhentheoutputs
aredisabled. XA(0)isCOMMAND LATCHENABLE(CLE).TheCLE inputcontrolsthe activating pathforcommands
sent tothe command register.Whenactivehigh, commandsarelatchedintothe command registerthrough theI/Oports

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2-8
SGH-V100 Circuit Description
on therising edgeofthe WEsignal.
XA(1)isADDRESS LATCHENABLE(ALE).inputcontrolsthe activating pathforaddress totheinternaladdress.
Address arelatchedontherising edgeofWEwithALE high. _XCS3ischipenable and _X_RDisReadEnable and
_X_WEisWriteEnable.GPIO15 isREADY/BUSY OUTPUT.Thepin output indicatesthestatusofthedevice operation.
Whenlow,it indicatesthataprogram,eraseor randomread operation isin process and returnsto high stateupon
completion. It isan open drain outputand doesnotfloat to high-zwhenthe chip deselected orwhen outputsaredisabled
6)AudioAmplifier(LM4890)
TheLM4890 isadualaudio poweramplifiercapableofdelivering 200mWofcontinuousaveragepowerintoan 8 ohm
loadwith 0.1% froma5Vpowersupply.
Boomeraudio poweramplifierwasdesignedspecificallyto providehigh quality outputpowerwithaminimalamountof
externalcomponentsusing surface mountpacking. Since theLM4890 doesnotrequirebootstrapcapacitorsorsnubber
networks,it isoptimallysuitedforlow-powerportablesystems.TheLM4890 featuresanexternallycontrolled, lowpower
consumption shutdownmodewhichisvirtuallyclickless and popless,aswell asaninternal thermalshutdown protection
mechanism.Theunity-gainstableLM4890 can be configured by externalgain-setting resistors.

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3.SGH-V100 FlowChartofTroubleshooting
3-1
1.Baseband
1. Power ON
Checkthecurrent
consumptionmore
than100mA
'PowerOn'doesnotwork
ChecktheVoltage
morethan3.3V
Downloadagain
ChargetheBattery
Checkthepin
15 ofU100 is
morethan2.8VCheckU100 andC113
U100 pin46,39
=2.8VCheckU100 andC112
Checktheclock
signal atpin4of
U704
Freq=13MHz ?
Vrms≥300mV ?
Vpp isaround
900mVpp ?
Checktheclockgenerationcircuit
(related toU703 andU704)
Checktheinitial operation
END
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
U100 pin13
=1.8V
No
Yes

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3-2
SGH-V100 FlowChartofTroubleshooting

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SGH-V100 FlowChartofTroubleshooting
3-3
2. Initial
Checkthesignal at the
pin28 ofU100 is
"High"whenthephone
isbooton
Initial Failure
CheckU100
END
No
Yes
Checkthepin22 of
U100 is"High"
Yes
ChecktheU700
Checkthepin4of
U703 isaround2.8VCheckthesoldered statusofU703,
R715,U100
Yes
No
No
Yes
Yes
CheckLCDconnectorCN201,
andresolderbridge
Yes
Checkthepin4of
U703 isaround2.8VCheckthesoldered statusof
U703,U704
No

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3-4
SGH-V100 FlowChartofTroubleshooting

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SGH-V100 FlowChartofTroubleshooting
3-5

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3-6
SGH-V100 FlowChartofTroubleshooting
3. SimPart
Checkthepin1ofCN100.
voltage3V ?
Phonecan'taccess SIMcard
Checkthecircuitrelated toU100
ResolderorchangeCN100
END
No
Yes
Yes
Yes
Yes
No
Checktherelated circuitofCN100
No
CheckthecircuitaroundU601 output
andvlotagesupplycircuitry
Yes
Checktherelated circuitofU601 and
U100
No
ChecktheSIM
connector's(CN100)
connectiontoSIMcard
Checkthecircuitaround
CN100 input
circuitry

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SGH-V100 FlowChartofTroubleshooting
3-7

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3-8
SGH-V100 FlowChartofTroubleshooting
4. ChargingPart
Checkthepin17,18 of
CN300 isTA_VEXT>4?
Abnormal chargingpart
Checkthepin2of
U101 is"low"?
ReplaceTA,CheckCN300
ChecktheU101
ChecktheQ101
END
No
Yes
Yes
Yes
Yes
No
No
Checkthepin3of
Q101 is"low"?
Checkthepin5of
U101 is"3.2~4.2V"?ChecktheU101
No
Yes
Checkthe ICHRGis
1V(duringcharging)and
around180mV(full
charging)?
NoResolderorchangeR111
Yes

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SGH-V100 FlowChartofTroubleshooting
3-9