SeaLevel ACB-ULTRA.LPCI User manual

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
ACB-ULTRA.LPCI
User Manual | 5104

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Contents
CONTENTS...........................................................................................................................................................2
INTRODUCTION ...................................................................................................................................................3
BEFORE YOU GET STARTED ...............................................................................................................................4
SOFTWARE INSTALLATION ................................................................................................................................6
HARDWARE INSTALLATION ............................................................................................................................... 7
TECHNICAL DESCRIPTION .................................................................................................................................8
SPECIFICATIONS ...............................................................................................................................................17
APPENDIX A –TROUBLESHOOTING................................................................................................................18
APPENDIX B –HOW TO GET ASSISTANCE .....................................................................................................19
APPENDIX C –ELECTRICAL INTERFACE ........................................................................................................20
APPENDIX D –SILK SCREEN –5104 PCB.......................................................................................................22
APPENDIX E –COMPLIANCE NOTICES...........................................................................................................23
WARRANTY ........................................................................................................................................................24

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Introduction
The ACB-ULTRA.LPCI adapter provides the PC with a single channel high-speed multi-protocol serial
interface suitable for the most popular communication protocols. This sync/async card provides an ideal
solution for high-speed applications including LAN/WAN connectivity. Utilizing the Zilog Z16C32 (IUSC™)
on chip DMA controller eliminates bus bandwidth constraints that are placed on typical interface adapters,
allowing data rates to reach 10M bps in burst mode. By utilizing the Z16C32's 32 byte FIFO buffer coupled
with 256K of on board memory, higher data rates are achieved.
The ACB-ULTRA.LPCI meets the PCISIG size requirements for an MD1 Low Profile adapter. This allows the
ACB-ULTRA.LPCI to be used in a variety of modern systems, including low profile servers, network
appliances and ‘All in One’ desktop computers. A standard height bracket is available for implementations
in a standard height PCI slot. The ACB-ULTRA.LPCI is a ‘Universal Bus’ adapter, allowing for use in either
+5 or +3.3V PCI slots and provides compliance with the PCISIG PCI Bus Specification Revision 2.2/2.3,
which requires ATX power support for both 5V and 3.3V.
Other Sealevel Sync Products
PC/104
ACB-104 (P/N 3512) - Z85230 RS-232/422/485/530/530a/V.35
ACB-104.ULTRA (P/N 3514) - Z16C32 RS-232/422/485/530/530a/V.35
Low Profile PCI
ACB-MP.LPCI (P/N 5102) - Z85230 RS-232/422/485/530/530a/V.35
ACB-232.LPCI (P/N 5103) - Z85230 RS-232
PCI
ACB-MP.LPCI (P/N 5102S) - Z85230 RS-232/422/485/530/530a/V.35
ACB-232.LPCI (P/N 5103S) - Z85230 RS-232
PCMCIA
PC-ACB-MP (P/N 3612) - Z85233 RS-232/422/485/530/530a/V.35

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Before You Get Started
What’s Included
The ACB-ULTRA.LPCI is shipped with the following items. If any of these items is missing or damaged,
please contact Sealevel for replacement.
•ACB-ULTRA.LPCI Adapter
•5104 includes low profile PCI bracket
•5104S includes standard size PCI bracket
Advisory Conventions
Warning
The highest level of importance used to stress a condition where damage could result to the
product, or the user could suffer serious injury.
Important
The middle level of importance used to highlight information that might not seem obvious or a
situation that could cause the product to fail.
Note
The lowest level of importance used to provide background information, additional tips, or other
non-critical facts that will not affect the use of the product.

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Optional Items
Depending upon your application, you are likely to find one or more of the following items useful for
interfacing the ACB-ULTRA.LPCI to real-world signals. All items can be purchased from our website
(http://www.sealevel.com) or by calling 864-843- 4343.
Part No.
Description
CA-178
6’ shielded cable with a DB-25F connector to an ITU-T ISO-2593 style connector (V.35) and converts
the Sealevel DB-25 implementation to the ITU-T V.35 mechanical standard.
CA-104
6’ extension cable with one DB-25M connector and one DB25Fconnector, pinned one-to-one, for use
with RS-232 and RS-530.
CA-107
10” shielded cabling adapter with a DB-25F (RS-530) to a DB-37M (RS-449 DTE). RS-530 is replacing
RS-449 in Telecom applications, but there is still a very large installed base of equipment that still
uses the RS-449 pin-out. Both standards use RS-422 to define the electrical specifications and are
interchangeable via this adapter cable.
CA-159
6’ shielded cable with a DB-25F (RS-530) to a DB-15M (X.21) and converts the standard DB-25
implementation of RS-530 or RS-422 to the ITU-T X.21 standard.

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Software Installation
Windows 2000/XP Installation
Do not install the adapter until the software has been successfully installed. .
1. Begin by locating, selecting, and installing the correct software from the Sealevel software driver
database.
2. Select the Part Number (5104) for your adapter from the listing. Select ‘Download Now’ for the
version of SeaMAC software (Route56 for Linux v2.0.10).
3. The setup file will automatically detect the operating environment and install the proper
components. Next (depending on the OS version) select the ‘Run this program from its current
location’ or ‘Open’ option. Follow the information presented on the screens that follow.
4. A screen may appear with the declaration: “The publisher cannot be determined due to the
problems below: Authenticode signature not found.” Please select the ‘Yes’ button and proceed
with the installation. This declaration simply means that the Operating System is not aware of the
driver being loaded. It will not cause any harm to your system.
5. During setup, the user may specify installation directories and other preferred configurations. This
program also adds entries to the system registry that are necessary for specifying the operating
parameters for each driver. An uninstall option is also included to remove all registry/INI file entries
from the system.

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Hardware Installation
The adapter can be installed in any PCI (5V or 3.3 V) expansion slot.
Do not install the Adapter in the machine until the software has been fully installed.
1. Turn off power. Disconnect the power cord.
2. Remove the PC case cover.
3. Locate an available PCI slot and remove the blank metal slot cover.
4. Gently insert the PCI adapter into the slot. Make sure that the adapter is seated properly.
5. Replace the screw. (This is required to ensure FCC Part 15 compliance.)
6. Replace the cover.
7. Connect the power cord and power up the machine.
The ACB-ULTRA.LPCI is now ready for use.

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Technical Description
The ACB-ULTRA.LPCI adapter was designed for seamless integration into any PCI based system. The ACB-
ULTRA.LPCI adapter requires a PCI slot, one IRQ, an 8 byte block of I/O address and a 16K block or 256K
block of memory address and additionally, the IUSC requires a 256 byte block of memory. The memory
range of this adapter can be configured to reside in the lower 1 Megabyte memory only or anywhere in
upper memory. Low memory (not available on PCI 2.2 or higher systems) must be configured as 16 X 16K
blocks of page memory. High memory can be configured as a 256K linear block or 16K paged memory.
Features
•Single channel high speed sync/async wide area network (WAN) interface
•RS-232, RS-422/449, EIA-530, V.35 and RS-485 serial interface capability with versatile cabling
options
•Multi-protocol capable including PPP (point-to-point protocol), Frame Relay, X.25, high-speed
Async, Bi-Sync, Mono-Sync, HDLC, SDLC, etc.
•Ideal for T1, Fractional T1, E1, and ISDN and other WAN applications
•On-board Z16C32 (IUSC™) with built in DMA controller and 32 byte FIFO buffer
•Up to 10 Mbps burst mode
•256K of on-board RAM
•Link list DMA supported
•32-bit data path
•OEM Security feature available as an option
Z16C32 IUSC™
The ACB-ULTRA.LPCI is based on a single Zilog Z16C32 IUSC (Integrated Universal Serial Controller). The
IUSC has a built-in DMA controller that allows high-speed data transfers directly to and from the 256K block
of on-board memory. The IUSC’s built-in DMA controller supports 4 different modes of DMA transfer: Single
Buffer, Pipelined, Array, and Link List. An on-board 20MHz oscillator clocks the IUSC.

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Technical Description, Continued
RAM
The memory window is located by BIOS PCI setup or the Set PCI function. The window size is a 16K paged
or 256K linear block. In paged mode the registers are located in the I/O registers.
•Low Memory options: 16 pages of 16K memory blocks totaling 256K (not available on PCI 2.2 or
later systems).
•High Memory options: 16 pages of 16K memory blocks totaling 256K or one linear block of 256K
memory.
Control and Status Registers Defined
The control and status registers occupy 8 consecutive locations. The following tables provide a functional
description of the bit positions.
Address
Mode
D7
D6
D5
D4
D3
D2
D1
D0
Base+0
RD
{0}
{0}
{0}
{1}+
P17
P16
P15
P14
Base+0
WR
ACCEN
MEM/IUC
X
X
P17
P16
P15
P14
Base+1
RD
{0}
{0}
{0}
{0}
{0}
{0}
{0}
{0}
Base+1
WR
X
X
X
X
X
X
X
X
Base+2
RD
LIN/PAGED
{0}
{1}
{0}
{0}
{0}
{0}
{0}
Base+2
WR
LIN/PAGED
X
X
X
X
X
X
X
Base+3
RD
{0}
{0}
INTPEND
RESTAT
{1}
{0}
{0}
{0}
Base+3
WR
SW Board Reset
X
X
X
X
X
X
X
Base+4
RD
{0}
IRQEN
{0}
{0}
{0}
{0}
{0}
{0}
Base+4
WR
X
IRQEN
X
X
X
X
X
X
Base+5
RD
LL
RL
{0}
{0}
M3
M2
M1
M0
Base+5
WR
LL
RL
X
X
M3
M2
M1
M0
Base+6
RD
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Base+7
RD
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
X = do not care { }= always this value

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© Sealevel Systems, Inc. 5104 & 5104S Manual | SL9076 7/2021
Technical Description, Continued
Control and Status Name Definition
Field
Description
ACCEN
1 = Host access to RAM or IUSC enabled; 0 = Host access to RAM or IUSC disabled. (0 on power-up)
MEM/IUC
1 = Enable Host access to RAM; 0 = Enable Host access to IUSC. (0 on power-up)
P17-P14
These bits select which of sixteen 16K RAM pages is visible at the address selected by MA18-MA14.
IRQEN
1 = Interrupts enabled, 0 = Interrupts disabled. (0 on power-up)
INTPEND
IUSC interrupt status: 1 = No interrupt pending on IUSC; 0 = Interrupt pending on IUSC.
RESTAT
Reset status: 1 = On-board reset inactive; 0 = On-board reset active.
RL
Remote loopback
LL
Local loopback
M0-M3
I/O mode select to SP505 (all 0 on power-up)
See Interface Selection table for valid interface options
SD0-SD15
Optional security feature. Unique value per customer or application. (default value = FFFF)
LIN/PAGE
1=256K linear block in high memory only, 0=16X16K pages in low or high memory, (0 on power-up)
Interface Selection
The ACB-ULTRA.LPCI supports a variety of electrical interfaces. Reference the Control and Status Registers
Defined section of this manual for this bit description. There is line termination on RXD, RXC, and TXC in
the following modes: RS-530, RS-530A, RS-485T, and V.35.
Reset Circuit
Writing any value to base+3 will reset the Z16C32. Only one write is required. This starts a reset sequence,
which lasts about 320 ns. During the reset sequence base+3 bit D4 will read 0. When the reset is complete,
base+3 bit D4 will read 1.
The Z16C32 should not be accessed until the reset sequence is complete.
TSET Clock Select
Port5 of Z16C32 is used to select TSET clock source.
•0 selects 16C32 TXC as source
•1 selects received TXC as source