SeaLevel PIO-96.PCI User manual

Part # 8009
Sealevel Systems, Inc
155 Technology Place
P.O. Box 830
Liberty, SC 29657 USA
Phone: [phone]
FAX: [phone]
www.sealevel.com
PIO-96.PCI
USER MANUAL
TM

Contents
INTRODUCTION..................................................................................................1
OVERVIEW .................................................................................................................1
WHAT’S INCLUDED....................................................................................................1
INSTALLATION.................................................................................................1
CARD SETUP..............................................................................................................1
SOFTWARE INSTALLATION ........................................................................................1
Linux Users.....................................................................................................1
SYSTEM INSTALLATION .............................................................................................2
TECHNICAL DESCRIPTION............................................................................3
SOFTWARE ................................................................................................................3
LINUX USERS.............................................................................................................3
3RD PARTY SOFTWARE SUPPORT................................................................................4
ELECTRICAL CHARACTERISTICS.................................................................................5
Pull Ups...........................................................................................................6
50 pin ribbon cable pin out..........................................................................7
PROGRAMMING................................................................................................8
APPLICATION PROGRAMMERS INTERFACE (API) .......................................................8
Reading the Inputs:.......................................................................................8
Reading the Outputs:....................................................................................8
Presetting an Output Port:...........................................................................8
Writing the Outputs:.....................................................................................8
Interrupts:.......................................................................................................8
Port Configuration:......................................................................................9
Relative Addressing vs. Absolute Addressing........................................10
Addressing Continued...............................................................................12
DIRECT HARDWARE CONTROL...............................................................................14
Reading the Inputs:....................................................................................14
Reading the Outputs:.................................................................................14
Presetting an Output Port:........................................................................14
Writing the Outputs:..................................................................................14
Port Configuration:...................................................................................14
Interrupts.....................................................................................................14
Register Description (for direct hardware control)..............................15
Control Words.............................................................................................16
SPECIFICATIONS............................................................................................18
ENVIRONMENTAL SPECIFICATIONS..........................................................................18
POWER CONSUMPTION...........................................................................................18

MEAN TIME BETWEEN FAILURES (MTBF).............................................................18
PHYSICAL DIMENSIONS...........................................................................................18
APPENDIX A -TROUBLESHOOTING........................................................19
APPENDIX B -HOW TO GET ASSISTANCE.............................................20
APPENDIX C -SILK-SCREEN......................................................................21
APPENDIX D -COMPLIANCE NOTICES..................................................22
FEDERAL COMMUNICATIONS COMMISSION STATEMENT........................................22
EMC DIRECTIVE STATEMENT ................................................................................22
WARRANTY.......................................................................................................23
FIGURES
Figure 1-Electrical Characteristics.........................................................5
Figure 2-Pull Up Resistors.........................................................................6
Figure 3-50 Pin Ribbon Cable Pin Out....................................................7
Figure 4-Control Words/Port Direction.................................................9
Figure 5-Absolute byte Address (any configuration) ..........................11
Figure 6-Relative byte Address................................................................11
Figure 7-Absolute Bit Address (Same for any configuration)...........12
Figure 8-Relative Byte Address (Print and fill in for your configuration)
.................................................................................................................13
Figure 9-Bit Relative Address (Print and fill in for your configuration)
.................................................................................................................13
Figure 10-I/O Configuration....................................................................16
Figure 11-Interrupt Control ....................................................................17
Figure 12-Interrupt Mode Select............................................................17
Figure 13-Interrupt Read..........................................................................17
© 2001l Sealevel Systems, Incorporated. All rights reserved.

Introduction and Installation
Sealevel Systems PIO-96.PCI Page 1
Introduction
Overview
The Sealevel Systems PIO-96.PCI provides twelve eight-bit ports compatible
with 8255 mode 0. Each port may be individually configured as inputs or
outputs.
What’s Included
The PIO-96.PCI is shipped with the following items. If any of these items is
missing or damaged, contact the supplier.
•PIO-96.PCI Adapter
•Sealevel Software CD
Industry Standard Relay Rack Cables and options are available:
•Part number CA135 for Edge Connection
•Part number CA167 for IDC Connection
•Part number TB07-50 pin terminal block
Installation
Card Setup
The PIO-96.PCI is a fully compliant PCI ‘Plug and Play’ adapter. All card
resources (i.e. I/O address, IRQ selection) are auto-assigned by either your
system BIOS or your ‘Plug and Play’ operating system.
Software Installation
For proper operation install software first. To install the software place the CD
in your CD-ROM tray and the auto-run program will start. If auto-run is not
available browse the CD and choose “index.htm”. Choose Install Software at
the beginning of the CD. Select the Digital I/O software drivers and install
SeaIO prior to installing hardware.
Linux Users
Refer to the installation instructions at the beginning of the CD for details on
installing the Sealevel Systems digital I/O cards in Linux.

Introduction and Installation
Sealevel Systems PIO-96.PCI Page 2
System Installation
The PIO-96.PCI can be installed in any of the PCI expansion slots.
1. Turn off PC power. Disconnect the power cord.
2. Remove the PC case cover.
3. Locate an available PCI slot and remove the blank metal slot cover.
4. Remove the clamping portion of the bracket from the card.
5. Gently insert the PIO-96.PCI into the slot. Make sure that the adapter
is seated properly.
6. Feed the four 50-pin ribbon cables through the cutout bracket and
connect them to the card.
7. Replace the bracket retaining screw.
8. Install the clamping portion of the bracket
9. Replace the computer cover.
10. Connect the power cord. Installation is complete.

Technical Description
Sealevel Systems PIO-96.PCI Page 3
Technical Description
The PIO-96.PCI provides 96 channels of digital I/O configurable as inputs or outputs, which can
be utilized for PC based control and automation including sensors, switches, satellite antenna
control systems, video and audio studio automation, security control systems, and other
industrial automation systems.
Software
The PIO-96.PCI ships with Sealevel Systems’ SeaI/O suite of Windows 98/NT/ME/2000
drivers. SeaI/O provides the user with a consistent and straightforward API, allowing the
developer to concentrate on the details of the application as opposed to low level driver
development. Popular development environments, including Visual C++, Visual Basic, and
Delphi, are supported for application development. SeaI/O includes sample applications and a
utility for configuring the driver parameters under Windows, further simplifying installation.
Linux Users
The PIO-96.PCI ships with software for Linux, including a kernel-mode driver, API, and the
SeaIOTst diagnostic tool. The kernel-mode driver is provided as a module, so future driver
upgrades may be performed with minimal (usually zero) downtime. The Linux API is identical to
its Windows counterpart, facilitating quick and easy ports of existing SeaI/O-aware applications
to the Linux operating system. All source code for the Linux software suite is provided under
the GNU Public License (GPL v2.0), to assist in "roll-your-own"-type applications.

Technical Description
Sealevel Systems PIO-96.PCI Page 4
3rd Party Software Support
Third party software support for many HMI/MMI and other process control software is included
on the product installation CD. For the most up to date information on third party software
support, please visit http://www.sealevel.com/3rdpartysw.htm.

Technical Description
Sealevel Systems PIO-96.PCI Page 5
Electrical Characteristics
The Table , below provides the electrical characteristics of each Input/Output. Each port is
buffered with a 74LS245 octal bi-directional transceiver. Each input is capable of sinking up to
24 mA, while each output can source up to 15 mA.
Recommended Operating Conditions
Min Max
Input 0 V 5.25 V
Source 15 mA
Sink 24 mA
Electrical Characteristics
High Level Input Voltage Min 2 V
Low Level Input Voltage Max 0.8 V
High Level Output Voltage Min 2 V at 15 mA
Typically 3.4 V at 3 mA
Low Level Output Voltage Max 0.55 V at 24 mA
Figure 1-Electrical Characteristics

Technical Description
Sealevel Systems PIO-96.PCI Page 6
Pull Ups
Ten pin bussed resistor packs are installed to provide pull-ups to the input ports. These are
installed on all ports. The pull-up resistor packs are rated at 10K ohms. Figure 2 below provides
the bussed resistor and corresponding port. The resistors insure that no line is floating which is
not connected. This provides consistent biasing on all un-terminated lines.
Bussed Corresponding Bussed Corresponding
Resistor Port Resistor Port
RP1 Port A1 RP7 Port A3
RP2 Port B1 RP8 Port B3
RP3 Port C1 RP9 Port C3
RP4 Port A2 RP10 Port A4
RP5 Port B2RP11 Port B4
RP6 Port C2 RP12 Port C4
Figure 2-Pull Up Resistors

Technical Description
Sealevel Systems PIO-96.PCI Page 7
50 pin ribbon cable pin out
Figure 3-50 Pin Ribbon Cable Pin Out
Description Pin #
Port A
A0 47
A1 45
A2 43
A3 41
A4 39
A5 37
A6 35
A7 33
Port B
B0 31
B1 29
B2 27
B3 25
B4 23
B5 21
B6 19
B7 17
Port C
C0 15
C1 13
C2 11
C3 9
C4 7
C5 5
C6 3
C7 1
GND All Even pins
+5V 49

Technical Description
Sealevel Systems PIO-96.PCI Page 8
Programming
Application Programmers Interface (API)
Most modern operating systems do not allow direct hardware access. The SeaIO driver and API
have been included to provide control over the hardware in Windows and Linux environments.
The purpose of this section of the manual is to help the customer with the mapping of the API to
the actual inputs for the PIO-96.PCI specifically. Complete documentation of the API can be
found in its accompanying help file.
Reading the Inputs:
The API presents the inputs as active low. If an input is driven high (2V to 5.25 V) it will read as a
logical zero (0), if driven low (0V to 0.8V) it will read as a logical one (1). If an input is not
driven it will read as a zero (0) due to the 10K ohm pull up resistors on each port.
Reading the Outputs:
The API returns the complement of value that is currently being used to drive the outputs. The
outputs cannot be read with relative addressing, absolute addressing must be used. Refer to
Relative Addressing vs. Absolute Addressingfor more information.
Presetting an Output Port:
Each port has an output register associated with it. This register may be written and retains its
value whether the port is configured as an input or an output. To preset the value of an output port
the program should write to the port when it is configured as an input then configure it as an
output. Inputs cannot be written to with relative addressing, absolute addressing must be used.
See Relative Addressing vs. Absolute Addressingbelow.
Writing the Outputs:
The outputs are active high. Writing a one (1) corresponds to 5V while writing a zero (0)
corresponds to 0V, at the output.
Interrupts:
Interrupt sampling can be set up in the API. Port A1 bit zero is the interrupt source (pin 47).
Refer to the API section in the SeaI/O help file for more detailed information.

Technical Description
Sealevel Systems PIO-96.PCI Page 9
Port Configuration:
Each eight-bit port can be configured as inputs or outputs. The API provides a set adapter state
call to access the control words. For this device, four control word is used. Refer to the
following table.
Note: The control panel also allows you to configure the device. Your program can over ride the
control panel configuration when executed, but the control panel configuration will be the default
on power up. The default settings are based on the settings in the control panel application when
last changed and saved after re-booting.
Control Word 0: Bank 1 (A1, B1, C1)
Control Word 1: Bank 2 (A2, B2, C2)
Control Word 2: Bank 3 (A3, B3, C3)
Control Word 3: Bank 4 (A4, B4, C4)
Control Words
I/O Configuration
CWnD0 Port C1 see below 1 on power up
CWnD1 Port B1 1 = input 0 = output 1 on power up
CWnD2 0 or 1 (no effect)
CWnD3 Port C1 see below 1 on power up
CWnD4 Port A1 1 = input 1 on power up
CWnD5 0 or 1 (no effect)
CWnD6 0 or 1 (no effect)
CWnD7 Always a 1
n = port number
CWnD3 CWnD0 Port C direction
00output
01input
10input
11input
Figure 4-Control Words/Port Direction

Technical Description
Sealevel Systems PIO-96.PCI Page 10
Relative Addressing vs. Absolute Addressing
The SeaIO API makes a distinction between “absolute” and “relative” addressing modes. In
absolute addressing mode, the Port argument to the API function acts as a simple byte offset
from the base I/O address of the device. For instance, Port #0 refers to the I/O address base + 0;
Port #1 refers to the I/O address base + 1.
Relative addressing mode, on the other hand, refers to input and output ports in a logical fashion.
With a Port argument of 0 and an API function meant to output data, the first (0th) output port on
the device will be utilized. Likewise, with a Port argument of 0 and an API function designed to
input data, the first (0th) input port of the device will be utilized.
In all addressing modes, port numbers are zero-indexed; that is, the first port is port #0, the
second port is #1, the third #2, and so on.

Technical Description
Sealevel Systems PIO-96.PCI Page 11
Tables : API Port/bit reference numbers for Absolute and Relative Addressing
R = Read
W = Write
R/W = Read or Write
Port API Port # Absolute Address
(function)
A1 0 ( R/W )
B1 1 ( R/W )
C1 2 ( R/W )
A2 8 ( R/W )
B2 9 ( R/W )
C2 10 ( R/W )
A3 16 ( R/W )
B3 17 ( R/W )
C3 18 ( R/W )
A4 24 ( R/W )
B4 25 ( R/W )
C4 26 ( R/W )
Figure 5-Absolute byte Address (any configuration)
Port API Port # Relative
Address (function) Port Type
A1 0 ( R ) Input
B1 1 ( R ) Input
C1 2 ( R ) Input
A2 0 ( W ) Output
B2 1 ( W ) Output
C2 2 ( W ) Output
A3 3 ( W ) Output
B3 4 ( W ) Output
C3 5 ( W ) Output
A4 3 ( R ) Input
B4 6 ( W ) Output
C4 7 ( W ) Output
Figure 6-Relative byte Address
Given: Inputs A1, B1, C1, A4
Outputs A2, B2, C2, A3, B3, C3, B4, C4

Technical Description
Sealevel Systems PIO-96.PCI Page 12
Addressing Continued
Bank 1 –P2 Bank 2 –P3 Bank 3 –P4 Bank 4 –P5
Address Port-Bit Address Port-Bit Address Port-Bit Address Port-Bit
0A1-064 A2-0128 A3-0192 A4-0
1A1-165 A2-1129 A3-1193 A4-1
2A1-266 A2-2130 A3-2194 A4-2
3A1-367 A2-3131 A3-3195 A4-3
4A1-468 A2-4132 A3-4196 A4-4
5A1-569 A2-5133 A3-5197 A4-5
6A1-670 A2-6134 A3-6198 A4-6
7A1-771 A2-7135 A3-7199 A4-7
8B1-072 B2-0136 B3-0200 B4-0
9B1-173 B2-1137 B3-1201 B4-1
10 B1-274 B2-2138 B3-2202 B4-2
11 B1-375 B2-3139 B3-3203 B4-3
12 B1-476 B2-4140 B3-4204 B4-4
13 B1-577 B2-5141 B3-5205 B4-5
14 B1-678 B2-6142 B3-6206 B4-6
15 B1-779 B2-7143 B3-7207 B4-7
16 C1-080 C2-0144 C3-0208 C4-0
17 C1-181 C2-1145 C3-1209 C4-1
18 C1-282 C2-2146 C3-2210 C4-2
19 C1-383 C2-3147 C3-3211 C4-3
20 C1-484 C2-4148 C3-4212 C4-4
21 C1-585 C2-5149 C3-5213 C4-5
22 C1-686 C2-6150 C3-6214 C4-6
23 C1-787 C2-7151 C3-7215 C4-7
Figure 7-Absolute Bit Address (Same for any configuration)

Technical Description
Sealevel Systems PIO-96.PCI Page 13
The following two tables are provided for the user in the event that he/she wishes to record their
particular relative addressing setup, provided its constant. Print this page and fill in the tables
starting in the top left corner of each and work from top to bottom, left to right. Start with zero
on the first input and increment by one on each additional input. Next move to outputs and again
start with zero and increment by one on each additional output.
Bank 1 –P2 Bank 2 –P3 Bank 3 –P4 Bank 4 –P5
Address Port Address Port Address Port Address Port
A1 A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4
Figure 8-Relative Byte Address (Print and fill in for your configuration)
Bank 1 –P2 Bank 2 –P3 Bank 3 –P4 Bank 4 –P5
Address Port-Bit Address Port-Bit Address Port-Bit Address Port-Bit
A1-0A2-0A3-0A4-0
A1-1A2-1A3-1A4-1
A1-2A2-2A3-2A4-2
A1-3A2-3A3-3A4-3
A1-4A2-4A3-4A4-4
A1-5A2-5A3-5A4-5
A1-6A2-6A3-6A4-6
A1-7A2-7A3-7A4-7
B1-0B2-0B3-0B4-0
B1-1B2-1B3-1B4-1
B1-2B2-2B3-2B4-2
B1-3B2-3B3-3B4-3
B1-4B2-4B3-4B4-4
B1-5B2-5B3-5B4-5
B1-6B2-6B3-6B4-6
B1-7B2-7B3-7B4-7
C1-0C2-0C3-0C4-0
C1-1C2-1C3-1C4-1
C1-2C2-2C3-2C4-2
C1-3C2-3C3-3C4-3
C1-4C2-4C3-4C4-4
C1-5C2-5C3-5C4-5
C1-6C2-6C3-6C4-6
C1-7C2-7C3-7C4-7
Figure 9-Bit Relative Address (Print and fill in for your configuration)

Technical Description
Sealevel Systems PIO-96.PCI Page 14
Direct Hardware Control
In systems where the users program has direct access to the hardware (DOS) the tables below
gives the mapping and functions that the PIO-96.PCI provide. The address of each eight-bit port
is calculated as shown in the table on the following page, the cards base address plus an offset.
Reading the Inputs:
The inputs are active high. If an input is driven high (2V to 5.25 V) it will read as a logical one, if
driven low (0V to 0.8V) it will read as a logical zero. If an input is not driven it will read as a one
due to the 10K ohm pull up resistors on each port.
Reading the Outputs:
The value that is currently being usedto drive the outputs will be returned.
Presetting an Output Port:
Each port has an output register associated with it. This register may be written and retains its
value whether the port is configured as an input or an output. To preset the value of an output port
the program should write to the port when it is configured as an input then configure it as an
output.
Writing the Outputs:
The outputs are active high. Writing a one (1) corresponds to 5V while writing a zero (0)
corresponds to 0V, at the output.
Port Configuration:
Each port can be configured as an input or an output by writing to its direction control bit, refer
to the tables below.
Interrupts
Interrupts can be set up as shown in the tables below.

Technical Description
Sealevel Systems PIO-96.PCI Page 15
Register Description (for direct hardware control)
Address
Hex Mode D7 D6 D5 D4 D3 D2 D1 D0
Base+0 Port A1 RD/WR
PA1D7 PA1D6 PA1D5 PA1D4 PA1D3 PA1D2 PA1D1 PA1D0
Base+1 Port B1 RD/WR
PB1D7 PB1D6 PB1D5 PB1D4 PB1D3 PB1D2 PB1D1 PB1D0
Base+2 Port C1 RD/WR
PC1D7 PC1D6 PC1D5 PC1D4 PC1D3 PC1D2 PC1D1 PC1D0
Base+3 Control Word
Port 1 WR CW1D7
00CW1D4 CW1D3 CW1D2 CW1D1 CW1D0
Base+4 Interrupt
configuration
Port 1
RD/WR 00000IRQEN1 IRQC11 IRQC10
Base+5 Interrupt
status for
Port 1 -- 4
RD 0000IRQST4 IRQST3 IRQST2
IRQST1
Base+8 Port A2 RD/WR
PA2D7 PA2D6 PA2D5 PA2D4 PA2D3 PA2D2 PA2D1 PA2D0
Base+9 Port B2 RD/WR
PB2D7 PB2D6 PB2D5 PB2D4 PB2D3 PB2D2 PB2D1 PB2D0
Base+A
Port C2 RD/WR
PC2D7 PC2D6 PC2D5 PC2D4 PC2D3 PC2D2 PC2D1 PC2D0
Base+B
Control
Word Port 2
WR CW2D7 00CW2D4 CW2D3 CW2D2 CW2D1 CW2D0
Base+C
Interrupt
configuration
Port 2
RD/WR 00000IRQEN2 IRQC21 IRQC20
Base+10
Port A3 RD/WR
PA3D7 PA3D6 PA3D5 PA3D4 PA3D3 PA3D2 PA3D1 PA3D0
Base+11
Port B3 RD/WR
PB3D7 PB3D6 PB3D5 PB3D4 PB3D3 PB3D2 PB3D1 PB3D0
Base+12
Port C3 RD/WR
PC3D7 PC3D6 PC3D5 PC3D4 PC3D3 PC3D2 PC3D1 PC3D0
Base+13
Control
Word Port 3
WR CW3D7 00CW3D4 CW3D3 CW3D2 CW3D1 CW3D0
Base+14
Interrupt
configuration
Port 3
RD/WR 00000IRQEN3 IRQC31 IRQC30
Base+18
Port A4 RD/WR
PA4D7 PA4D6 PA4D5 PA4D4 PA4D3 PA4D2 PA4D1 PA4D0
Base+19
Port B4 RD/WR
PB4D7 PB4D6 PB4D5 PB4D4 PB4D3 PB4D2 PB4D1 PB4D0
Base+1
A Port C4 RD/WR
PC4D7 PC4D6 PC4D5 PC4D4 PC4D3 PC4D2 PC4D1 PC4D0
Base+1
B Control
Word Port 4
WR CW4D7 00CW4D4 CW4D3 CW4D2 CW4D1 CW4D0
Base+1
C Interrupt
configuration
Port 4
RD/WR 00000IRQEN4 IRQC41 IRQC40

Technical Description
Sealevel Systems PIO-96.PCI Page 16
Control Words
I/O Configuration
Figure 10-I/O Configuration
CWnD0 Port C1 see below 1 on power up
CWnD1 Port B1 1 = input 0 = output 1 on power up
CWnD2 0 or 1 (no effect)
CWnD3 Port C1 see below 1 on power up
CWnD4 Port A1 1 = input 1 on power up
CWnD5 0 or 1 (no effect)
CWnD6 0 or 1 (no effect)
CWnD7 Always a 1
n = port number
CWnD3 CWnD0 Port C direction
00output
01input
10input
11input
Control Word (X = 0) Hex Value Port Setup
76543210ABC Upper C Lower
1XX00X0080 Out Out Out Out
1XX00X0181 Out Out In In
1XX00X1082 Out In Out Out
1XX00X1183 Out In In In
1XX01X0088 Out Out In In
1XX01X0189 Out Out In In
1XX01X108A Out In In In
1XX01X118B Out In In In
1XX10X0090 In Out Out Out
1XX10X0191 In Out In In
1XX10X1092 In In Out Out
1XX10X1193 In In In In
1XX11X0098 In Out In In
1XX11X0199 In Out In In
1XX11X109A In In In In
1XX11X119B In In In In

Technical Description
Sealevel Systems PIO-96.PCI Page 17
Interrupt Control
When enabled interrupts are generated on port bit D0 of each A port.
n = port number
IRQENn interrupt enable 1 = enabled 0 = disabled ( 0 on power up )
IRQCn0
IRQCn1 Interrupt mode select see table
Interrupt mode select see table
Figure 11-Interrupt Control
Interrupt mode select table
IRQCn1 IRQCn0 INT Type
00Low level
01High level
10Falling edge
11Rising edge
Figure 12-Interrupt Mode Select
Interrupt Read
(reading this port clears the interrupt)
IRQST1 (D0) Interrupt status 1 = interrupt pending, 0 = none
IRQST2 (D1) Interrupt status 1 = interrupt pending, 0 = none
IRQST3 (D2) Interrupt status 1 = interrupt pending, 0 = none
IRQST4 (D3) Interrupt status 1 = interrupt pending, 0 = none
Figure 13-Interrupt Read