Siemens 928B User guide

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5.4 CPU 928B
This section contains the hardware description and technical specifications of
the CPU 928B.
Details on programming the CPU 928B can be found in the
CPU 928B Programming Guide.
5.4.1 Technical Description
You can use the CPU 928B in single and multiprocessor operation in the
S5-135U/155U central controller (see Chapter 6). Up to four CPUs can be
used.
The CPU 928B is universally applicable, ensuring both very fast
bit processing and very fast word processing:
Cyclic
Time-controlled (9 different timebases)
Real-time controlled
Interrupt-driven (hardware interrupt)
Delayed (from Version 6ES5 928-3UB12)
The programming language is STEP 5.
The electronic circuitry of the CPU 928B is on two PCBs (basic and
expansion boards) in the double Eurocard format. Both PCBs are screwed
together, linked via connectors, and must not be separated. The basic board
provides the connection to the S5 bus via two backplane connectors.
The front plate width is 2 2/3 standard plug-in stations.
Application
Design
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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You require a user memory submodule (RAM or EPROM) for storage of your
program. You can store up to 64 x 210 bytes of code and data blocks here. For
data blocks, the CPU 928B additionally has an integrated DB RAM of
46 x 210 bytes.
A description of the memory submodules can be found in Sections 5.9 and
5.10; order numbers are given in the ordering information.
There are two independent interfaces on the front of the CPU 928B.
You can connect programmers and OPs to the first interface. This
PG interface SI1 is permanently installed on the CPU.
You can use PG interface SI1 either via the front connector of the CPU 928B
or via the front connector of the 923C coordinator module.
Note
Simultaneous operation of PG interface SI1 via the front connector of the
CPU 928B and of the coordinator is not possible. Electrically, it is merely a
PG interface which can be operated via two different terminals. Switching
the programmer online without a job request is already sufficient to operate
the interface. If you wish to utilize a second PG interface for connection of a
PG or OP, the connection must be made via the second PG interface with the
PG submodule.
Apart from PG interface SI1, the second interface SI2 can also be used as a
PG interface in parallel with the first one. You can only use the second
PG interface via the front connector of the PG submodule on the CPU 928B.
A detailed description of operations with the two PG interfaces can be found
in the CPU 928B Programming Guide.
The connection to the PG can be established with the CPU in any operational
state.
User Memory
PG Interface SI1
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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You can optionally use the second interface of the CPU 928B as:
A PG interface (for PG and operator panels)
Interface for the RK 512 computer link
Interface for data transmission with procedures 3964/3964R
Interface for data transmission with the “open driver”
Interface for data transmission via the SINEC L1 bus (from
Version 6ES5 928-3UB12).
To utilize the second interface as the PG interface, you need the
PG submodule.
You need one of the following interface submodules for the
RK 512 computer link, for data transmission with procedures 3964/3964R
and for data transmission with the “open driver”:
V.24 submodule (RS 232C)
TTY submodule
RS422 A/485 submodule (only in the RS422 A module).
To utilize the second interface for data transmission via the SINEC L1 bus,
you need the
SINEC L1 submodule (from Version 6ES5 928-3UB12).
The CPU 928B is delivered without an interface submodule. You can operate
the CPU 928B without an integral interface submodule. The opening to
accept a submodule in the front plate is closed by a cover. Only remove the
cover to fit an interface submodule.
A description of interface submodules can be found in Section 5.11, and the
order numbers in the ordering information.
A detailed description of the second interface can be found in the CPU 928B
Communication Manual.
There is an interrupt line in the PLC for each CPU. It can be used when the
reaction to an event must occur with higher priority than the reaction to other
events.
To process an interrupt, cyclic program processing is interrupted and the
program stored in OB 2 (OB for interrupt processing) is inserted.
(Refer to the CPU 928B Programming Guide for further details.)
This interrupt-driven program processing is only possible using an
interrupt-capable digital input module or a suitable operating CP/IP module.
No jumper setting on the CPU 928B is required. Please note, however, that
the usable interrupt line on the backplane bus depends on the CPU slot and
must be set accordingly on the I/O module (see Section 4.1).
Second Interface
SI2
Process Interrupt
Processing
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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5.4.2 Installation and Startup
Note
All jumpers on the CPU 928B are required by the manufacturer for quality
testing. You must not change the jumper settings.
!Caution
Switch off the power supply before removing or inserting the module. The
basic board and expansion board of the CPU 928B are one unit and must not
be separated.
Proceed as follows to insert the CPU in the central controller:
Step Action
1Release the upper locking bar of the central controller and ensure
that the locking pin for the module is correctly positioned with the
slot-head horizontal.
2Select the correct slot (based on the labelling of the locking bar).
Insert the CPUs in the S5-135U/155U from slot 11.
3Push the module evenly into the guide rail until the lever over the
locking pin is horizontal.
4Press the locking pin inwards on the bottom of the module and
rotate it 90o clockwise.
5Secure the upper locking bar.
Jumper Settings
Removing and
Inserting the
Module
Insertion
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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Proceed as follows to remove the CPU:
Step Action
1Release the upper locking bar of the central controller.
2Release the locking pin of the module.
3Press the release lever downwards and pull the module forwards
and out of the central controller.
Note
Only operate the CPU 928B with the submodule receptacle closed. You
close it either by fitting an interface submodule or with the cover supplied.
Removal
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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The controls and indicators are arranged on the front plate of the CPU
module:
SIEMENS
Receptaclefor
User Memory Submodule
Mode Switch
LED (green)
LED (red)
Momentary-Contact Mode Switch
Fault Indicator LEDs (red)
PG Interface, 15-Pin
Interface SI 1
Release Lever
Locking Pin
Interface Fault Indicator LEDs (red)
Interface 1
Interface 2
RUN
STOP
RUN
STOP
RÜCKSETZEN
RESET
URLÖSCHEN
OVERALL RESET
SI1
SI2
QVZ
ADF
ZYK
BASP
Order Number and Version
Receptacle for Interface Submodule
Interface SI 2
SI2
SI1
6ES5928-3UB12
CPU 928B
Figure 5-6 Front Plate of the CPU 928B
Controls and
Indicators
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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The mode switch has two settings:
In the RUN setting, the CPU 928B processes the user program when the
green RUN LED is lit.
The CPU 928B goes to the stop state when you switch from RUN to STOP.
The red STOP LED then lights up.
You can initiate the Overall Reset, Reset and Restart functions with the
momentary-contact mode switch:
Momentary-contact switch down
With an overall reset, all RAM areas are erased and initialized (both on the
CPU and on a RAM submodule).
Momentary-contact switch up
During a reset, all flags, timers, counters and the process image will be
erased. OB 20 will be invoked. Processing of the user program will start from
the beginning again.
Momentary-contact switch at midpoint
With a restart, processing of the user program will continue from the point of
interruption. The statuses of flags, timers, counters and the process image are
retained during stoppage of the CPU.
Mode Switch
RUN
STOP
Momentary-
Contact Mode
Switch
OVERALL RESET
RESET
Restart
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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RUN
LED STOP LED Status
on off The CPU is in the RUN state.
off on The CPU is in the STOP state. After a stop
request by switch or PG function, the STOP LED
is continuously lit because the transition to the
STOP state was requested by the user or, in
multiprocessor operation, by another CPU, and
was not caused by the CPU itself.
off off The CPU is in the INITIAL START or program
check state.
off slow
flashing The CPU is in the STOP state. The CPU has caused a transition to the STOP state (possibly
also for the other CPUs). If you set the mode
switch to STOP, the flashing LED becomes
continuously lit.
off rapid
flashing The CPU is in the STOP state. An overall reset has been requested. This request can be initiated
by the CPU itself or by operator action.
QVZ LED
on During direct access or process image update, a module
addressed by the program no longer acknowledges although
either it has acknowledged in single-processor operation
upon reset of the CPU 928B in the area of the process
image (IB 0 to 127, QB 0 to 127) and has been entered as
present in the “9th track” (see Programming Guide,
CPU 928B),
it h b t d i DB 1 ( dd li t) i
or it has been entered in DB 1 (address list) in
multiprocessor or single-processor operation and has been
recognized as present during the reset.
Possible causes
Module failure.
Module was pulled out during operation, in the
STOP state or in the Off state without a subsequent reset.
Status Indicators
LEDs for Fault
Indication and
Signaling
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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ADF LED
on The user program has referenced an I/O address in the
process image under which no module is inserted.
ZYK LED
on The maximum cycle monitoring time has been exceeded.
BASP LED
on Command output is inhibited and the digital outputs will be
directly switched to the safe state.
A detailed description of interrupt and error handling can be found in the
CPU 928B Programming Guide.
LED SI1 LED SI2 Cause
on on No communication possible at both interfaces.
Internal error.
on off SI1:
No communication possible. Internal error.
SI2:
If used, interface is initialized and ready.
off on SI1:
Interface is initialized and ready.
SI2:
No communication possible.
Wrong interface submodule inserted or wrong
parameters for interface or internal error.
off off First interface and, if used, second interface are
initialized and ready.
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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The modules must be inserted at the correct slots in the central controller.
The backup battery must be fitted and in order for the CPU to start.
Step Action Result
1Set the mode switch to STOP.
2Switch the system voltage on. The following LEDs must light
up on the CPU:
– Red STOP LED (flashing
rapidly)
– Red BASP2) LED
3Hold the MC1) switch in the
OVERALL RESET setting
and simultaneously set the
mode switch from STOP to
RUN.
The red STOP LED is now
permanently lit.
1) MC: Momentary-contact
2) BASP: Command output inhibit
Step Action Result
1Set the mode switch to STOP.
2Hold the MC switch in the
RESET setting and
simultaneously set the mode
switch from STOP to RUN.
– Red STOP LED goes off
– Green RUN LED lights up
– Red BASP LED goes off
The CPU is now in the RUN state
but still has no user program.
You can also carry out a manual restart of the CPU 928B with the mode
switch. The CPU 928B Programming Guide will indicate when a manual
restart is permissible.
Step Action Result
3Set the mode switch from
STOP to RUN. – Red STOP LED goes off – Green RUN LED lights up
– Red BASP LED goes off
For maintenance purposes or in the event of a fault, this startup without user
program in single-processor operation can serve to establish whether the CPU
is operating without errors.
Startup
Overall Reset
Reset
Restart
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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5.4.3 Technical Specifications
Important for the USA and Canada
The following approvals have been obtained:
UL Listing Mark
Underwriters Laboratories (UL) to Standard UL 508, Report E 85972
CSA Certification Mark
Canadian Standard Association (CSA) to Standard C 22.2 No. 142,
Report LR 63533
Degree of protection IP 00
Climatic ambient conditions See Technical Specifications of the S5-135U/155U CC
Mechanical ambient conditions See Technical Specifications of the S5-135U/155U CC
Noise immunity, electromagnetic
compatibility (EMC) See Technical Specifications of the S5-135U/155U CC
Supply voltage 5 V 5 %
24 V + 25 %/ -17 %
Current consumption at 5 V 5 A typical
Current consumption at 24 V 760 mA max.
Backup voltage 3.4 V
Backup current 20 A typical (at 25 C)
P area O area IM3 area IM4 area Total
Digital inputs with process image
Digital inputs without process image
or analog inputs
1024 max.
1024 max.
64 max.
–
2048 max.
128 max.
–
2048 max.
128 max.
–
2048 max.
128 max.
1024 max.
7168 max.
448 max.
Digital outputs with process image
Digital outputs without process image
or analog outputs
1024 max.
1024 max.
64 max.
–
2048 max.
128 max.
–
2048 max.
128 max.
–
2048 max.
128 max.
1024 max.
7168 max.
448 max.
Flags 2048
S flags 8192
Timers 256
Counters 256
Size of user memory 64 x 2 bytes max., EPROM or RAM
DB RAM 46 x 2 byte
Transmission rate of the serial PG interface 9600 bps
Program blocks PB 256
Sequence blocks SB 256
Function blocks FB 256
Function blocks FX 256
Data blocks DB 256, of which 253 are freely available
Data blocks DX 256, of which 253 are freely available
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules

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Organization blocks OB OB 1 to 39 (interfaces for operating system)
Integrated special function organization
blocks OB See Pocket Guide
Integrated serial interface PG interface
Optional serial interface Via interface submodules, optionally as V.24, TTY, RS 422A/485 or
PG interface
SINEC L1 interface from Version 6ES5 928-3UB12
Backplane bus S5 bus
Dimensions (w x h x d) 40.64 x 233.4 x 160 mm
Weight Approx. 1 kg
CPUs, Memor
y
Cards, Memor
y
Submodules, Interface Submodules