Siemens SAB 80515 Series User manual

User'sManual08.95
MicrocomputerComponents
SAB80515/SAB80C515
8-BitSingle-ChipMicrocontrollerFamily
*

Edition 08.95
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1995.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
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curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components
1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems
2
with the express
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SAB 80515 / SAB 80C515 Family
Revision History: 8.95
Previous Releases: 12.90/10.92
Page Subjects (changes since last revision)
30
39
80
105
106
109
137
152
243
301
Modified timing diagram (PSEN rising edge)
More detailed description of ACMOS port structure
Differential output impedance of analog reference supply voltage now: 1 kΩ
Second paragraph: additional description; WDT reset information added
SWDT reset information added
Figure 7-51 corrected
Encoding of ADD A, direct corrected
Encoding of CPL bit corrected
New release of SAB 80C515 / SAB 80C535 data sheet inserted
New release of SAB 80515 / SAB 80535 data sheet inserted
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Contents
Contents Page
Semiconductor Group 3
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Differences between MYMOS (SAB 80515/80535) and
ACMOS (SAB 80C515/80C535) Versions . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1.1 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1.2 Special Function Register PCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.1.3 Port Driver Circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1.4 The A/D Converter Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1.5 A/D Converter Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.1.6 The Oscillator and Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.1.7 The VBB Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.3 General Purpose Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.4 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5.2 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.3 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.4 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . .29
6 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1 Hardware Reset and Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1.1 Reset Function and Circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1.2 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
7 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1.1.1 Digital I/O Port Circuitry (MYMOS/ACMOS) . . . . . . . . . . . . . . . . . . . . . . . . .36
7.1.1.2 MYMOS Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.1.1.3 ACMOS Port Driver Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
7.1.2 Port 0 and Port 2 Used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . .41
7.1.3 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
7.1.4 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
7.1.4.1 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
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Contents
Contents Page
Semiconductor Group 4
7.1.4.2 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
7.1.4.3 Read-Modify-Write Feature of Ports 0 through 5 . . . . . . . . . . . . . . . . . . . . . .45
7.2 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.2.1 Operating Modes of Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
7.2.2 Multiprocessor Communication Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
7.2.3 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
7.2.4 Detailed Description of the Operating Modes . . . . . . . . . . . . . . . . . . . . . . . .54
7.2.4.1 Mode 0, Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
7.2.4.2 Mode 1, 8-Bit UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
7.2.4.3 Mode 2, 9-Bit UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.2.4.4 Mode 3, 9-Bit UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.3 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.3.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.3.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.3.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.3.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.4 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.4.1 Function and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.4.1.1 lnitialization and Input Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.4.1.2 Start of Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7.4.2 Reference Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.4.3 A/D Converter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.5 Timer 2 with Additional Compare/Capture/Reload . . . . . . . . . . . . . . . . . . . . .82
7.5.1 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.5.2 Compare Function of Registers CRC, CC1 to CC3 . . . . . . . . . . . . . . . . . . . .88
7.5.2.1 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7.5.2.2 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.5.2.3 Using Interrupts in Combination with the Compare Function . . . . . . . . . . . . .94
7.5.3 Capture Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
7.6 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.6.1 Power Saving Modes of the SAB 80515/80535 . . . . . . . . . . . . . . . . . . . . . . .99
7.6.1.1 Power-Down Mode of the SAB 80515/80535 . . . . . . . . . . . . . . . . . . . . . . . .99
7.6.2 Power Saving Modes of the SAB 80515/80535 . . . . . . . . . . . . . . . . . . . . . .100
7.6.2.1 Power-Down Mode of the SAB 80C515/80C535 . . . . . . . . . . . . . . . . . . . . .101
7.6.2.2 Idle Mode of the SAB 80C515/80C535 . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.7 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
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Contents
Contents Page
Semiconductor Group 5
7.8 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.8.1 Crystal Oscillator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.8.2 Driving for External Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
7.8.2.1 Driving the SAB 80515/80535 from External Source . . . . . . . . . . . . . . . . . .108
7.8.2.2 Driving the SAB 80C515/80C535 from External Source . . . . . . . . . . . . . . .109
7.9 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.1 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
8.2 Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
8.3 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
8.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.5 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.2 Introduction to the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.2.1 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
9.2.2 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
9.2.3 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.2.4 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
9.3 Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
10 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
*

Semiconductor Group 6
Introduction
1 Introduction
The SAB 80C515/80C535 is a new, powerful member of the Siemens SAB 8051 family of 8-bit
microcontrollers. lt is designed in Siemens ACMOS technology and is functionally compatible with
the SAB 80515/80535 devices designed in MYMOS technology.
The ACMOS and the MYMOS versions 1) 2) are stand-alone, high-performance single-chip
microcontrollers based on the SAB 8051/80C51 architecture. While maintaining all the
SAB 80(C)51 operating characteristics, the SAB 80(C)515/80(C)5353) incorporate several
enhancements which significantly increase design flexibility and overall system performance.
The low-power properties of Siemens ACMOS technology allow applications where power
consumption and dissipation are critical. Furthermore, the SAB 80C515/80C535 has two software-
selectable modes of reduced activity for further power reduction: idle and power-down mode.
The SAB 80(C)535 is identical to the SAB 80(C)515 except that it lacks the on-chip program
memory. The SAB 80(C)515/80(C)535 is supplied in a 68-pin plastic leaded chip carrier package
(P-LCC-68). In addition to the standard temperature range version (0 °to + 70 °C) there are also
versions for extended temperature ranges available (see data sheets).
Functional Description
The members of the SAB 80515 family of microcontrollers are:
– SAB 80C515: Microcontroller, designed in Siemens ACMOS technology, with 8-Kbyte
factory mask-programmable ROM
– SAB 80C535: ROM-less version, identical to the SAB 80C515
– SAB 80515: Microcontroller, designed in Siemens MYMOS technology, with 8-Kbyte
factory mask-programmable ROM
– SAB 80535: ROM-less version, identical to the SAB 80515
– SAB 80515K: Special ROM-less version of the SAB 80515 with an additional interface for
program memory accesses. An external ROM that is accessed via the
interface substitutes the SAB 80515’s internal ROM.
1In this User’s Manual the term "ACMOS versions" is used to refer to both the SAB 80C515 and
SAB 80C535.
2The term "MYMOS versions" stands for SAB 80535 and SAB 80515.
3The term "SAB 80(C)515" refers to the SAB 80515 and the SAB 80C515, unless otherwise
noted.
*

Semiconductor Group 7
Introduction
The SAB 80(C)515 features are:
– 8 Kbyte on-chip program memory
– 256 byte on-chip RAM
– Six 8-bit parallel I/O ports
– One input port for digital input 1)
– Full-duplex serial port, 4 modes of operation, fixed or variabie baud rates
– Three 16-bit timer/counters
– 16-bit reload, compare, capture capability
– A/D converter, 8 multiplexed analog inputs, programmable reference voltages
– 16-bit watchdog timer
– Power-down supply for 40 byte of RAM
– Boolean processor
– 256 directly addressable bits
– 12 interrupt sources (7 external, 5 internal), 4 priority levels
– Stack depth up to 256 byte
–1µs instruction cycle at 12-MHz operation
–4µs multiply and divide
– External program and data memory expandable up to 64 Kbyte each
– Compatible with standard SAB 8080/8085 peripherals and memories
– Space-saving P-LCC-68 package
For small-quantity applications and system development the SAB 80535 can be employed being
the equivalent of an SAB 80515 without on-chip ROM.
1Additional feature of the ACMOS versions
*

Semiconductor Group 8
Introduction
Figure 1-1 shows the logic symbol, figure 1-2 the block diagram of the SAB 80(C)515:
Figure 1-1
Logic Symbol
*

Semiconductor Group 9
Introduction
Figure 1-2
Block Diagram
*

Semiconductor Group 10
Fundamental Structure
2 Fundamental Structure
The SAB 80(C)515/80(C)535 is a totally 8051-compatible microcontroller while its peripheral
performance has been increased significantly.
Some of the various peripherals have been added to support the 8-bit core in case of stringent
embedded control requirements without loosing compatibility to the 8051 architecture.
Furthermore, the SAB 80(C)515/80(C)535 contains e. g. an additional 8-bit A/D converter, two
times as much ROM and RAM as the 80(C)51 and an additional timer with compare/capture/reload
facilities for all kinds of digital signal processing.
Figure 2.1 shows a block diagram of the SAB 80(C)515/80(C)535.
The SAB 80C515/80C535 combines the powerful architecture of the industry standard controller
SAB 80515/80535 with the advantages of the ACMOS technology (e. g. power-saving modes). The
differences between MYMOS and ACMOS components are explained in section 2.1.
Readers who are familiar with the SAB 8051 may concentrate on chapters 2.1, 6, 7 and 8 where
the differences between MYMOS and ACMOS components, the reset conditions, the peripherals
and the interrupt system are described.
For newcomers to the 8051 family of microcontrollers, the following section gives a general view of
the basic characteristics of the SAB 80515/80535. The details of operation are described later in
chapters 3 and 4.
*

Semiconductor Group 11
Fundamental Structure
Central Processing Unit
The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes,
are performed in one, two or four machine cycles. One machine cycle requires twelve oscillator
cycles. The instruction set hasextensive facilitiesfor data transfer, logicand arithmetic instructions.
The Boolean processor has itsown full-featured and bit-based instructions within the instruction set.
The SAB 80(C)515/80(C)535 uses five addressing modes: direct access, immediate, register,
register indirect access, and for accessing the external data or program memory portions a base
register plus index-register indirect addressing.
Memory Organization
The SAB 80C515, 80515 have an internal ROM of 8 Kbyte. The program memory can externally be
expanded up to 64 Kbyte (see bus expansion control). The internal RAM consists of 256 bytes.
Within this address space there are 128 bit-addressable locations and four register banks, each
with 8 general purpose registers. In addition to the internal RAM there is a further 128-byte address
space for the special function registers, which are described in sections to follow.
Because of its Harvard architecture, the SAB 80(C)515/80(C)535 distinguishes between an
external program memory portion (as mentioned above) and up to 64 Kbyte external data memory
accessed by a set of special instructions.
Bus Expansion Control
The external bus interface of the SAB 80(C)515/80(C)535 consists of an 8-bit data bus (port 0), a
16-bit address bus (port 0 and port 2) and five control lines. The address latch enable signal (ALE)
is used to demultiplex address and data of port 0. The program memory is accessed by the program
store enable signal (PSEN) twice a machine cycle. A separate external access line (EA) is used to
inform the controller while executing out of the lower 8 Kbyte of the program memory, whether to
operate out of the internal or external program memory. The read or write strobe (RD, WR) is used
for accessing the external data memory.
Peripheral Control
All on-chip peripheral components - I/O ports, serial interface, timers, compare/capture registers,
the interrupt controller and the A/D converter - are handled and controlled by the so-called special
function registers. These registers constitute the easy-to-handle interface with the peripherals. This
peripheral control concept, as implemented in the SAB 8051, provides the high flexibility for further
expansion as done in the SAB 80(C)515/80(C)535.
Moreover some of the special function registers, like accumulator, B-register, program status word
(PSW), stack pointer (SP) and the data pointer (DPTR) are used by the CPU and maintain the
machine status.
*

Semiconductor Group 12
Fundamental Structure
Figure 2-1
Detailed Block Diagram
*

Semiconductor Group 13
Fundamental Structure
2.1 Differences between MYMOS (SAB 80515/80535) and
ACMOS (SAB 80C515/80C535) Versions
There are some differences between MYMOS and ACMOS versions concerning:
– Power Saving Modes
– Special Function Register PCON
– Port Driver Circuitry
– A/D Converter Input Ports
– A/D Converter Conversion Time
– Oscillator and Clock Circuit
–VBB Pin
2.1.1 Power Saving Modes
The SAB 80515/80535 has just the power-down mode, which allows retention of the on-chip RAM
contents through a backup supply connected to the VPD pin.
The SAB 80C515/80C535 additionally has the following features:
– idle mode
– the same power supply pin VCC for active, power-down and idle mode
– an extra pin (PE) that allows enabling/disabling the power saving modes
– starting of the power-saving modes by software via special function register PCON (Power
Control Register)
– protection against unintentional starting of the power-saving modes
These items are described in detail in section 7.6.
2.1.2 Special Function Register PCON
In the MYMOS version SAB 80515/80535 the SFR PCON (address 87H) contains only bit 7
(SMOD).
In the ACMOS version SAB 80C515/80C535 there are additional bits used (see figure 2-2).
The bits PDE, PDS and IDLE, IDLS select the power-down mode or idle mode, respectively, when
the power saving modes are enabled by pin PE.
Furthermore, register PCON of the ACMOS version contains two general-purpose flags. For
example, the flag bits GF0 and GF1 can be used to indicate whether an interrupt has occurred
during normal operation or during idle. Then an instruction that activates idle can also set one or
both flag bits. When idle is terminated by an interrupt, the interrupt service routine can sample the
flag bits.
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Semiconductor Group 14
Fundamental Structure
2.1.3 Port Driver Circuitries
The port structures of the MYMOS andACMOS versionsare functionally compatible. For low power
consumption the pullup arrangement is realized differently in both versions.
Chapters 7.1.1.1, 7.1.1.2, 7.1.1.3 are dealing with the port structures in detail.
2.1.4 The A/D Converter Input Ports
The analog input ports (AN0 to AN7) of the SAB 80515/80535 can only be used as analog inputs
for the A/D converter.
The analog input ports (P6.0 to P6.7) of the SAB 80C515/80C535 can be used either as input
channels for the A/D converter or as digital inputs (see chapter 7.4)
Figure 2-2
Special Function Register PCON (Address 87H)
Symbol Position Function
SMOD
PDS
IDLS
–
GF1
GF0
PDE
IDLE
PCON.7
PCON.6
PCON.5
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
When set, the baud rate of the serial channel in mode 1, 2, 3 is doubled.
Power-down start bit. The instruction that sets the PDS flag bit is the last
instruction before entering the power-down mode.
Idle start bit.The instruction that sets theIDLS flag bit is the lastinstruction
before entering the idle mode.
Reserved
General purpose flag
General purpose flag
Power-down enable bit. When set, starting of the power-down mode is
enabled.
Idle mode enable bit. When set, starting of the idle mode is enabled.
These bits are available in the MYMOS version
SMOD PDS IDLS – GF1 GF0 PDE IDLE87HPCON
76543210
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Semiconductor Group 15
Fundamental Structure
2.1.5 A/D Converter Timings
See the corresponding data sheets for the specification of tL(load time), tS(sample time), tC
(conversion time).
2.1.6 The Oscillator and Clock Circuits
There is no difference between the MYMOS and ACMOS versions if they are driven from a crystal
or a ceramic resonator.
Please note that there is a difference between driving MYMOS and ACMOS components from
external source. How to drive each device is described in chapter 7.8.2 and in each data sheet.
2.1.7 The VBB Pin
The SAB 80515/80535 has an extra VBB pin connected to the device’s substrate. lt must be
connected to VSS through a capacitor for proper operation of the A/D converter.
The SAB 80C515/80C535 has no VBB pin. In ACMOS technology the substrate is directly connected
to VCC ; therefore, the corresponding pin is used as an additional VCC pin.
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Semiconductor Group 16
Central Processing Unit
3 Central Processing Unit
3.1 General Description
The CPU (Central Processing Unit) of the SAB 80(C)515 consists of the instruction decoder, the
arithmetic section and the program control section. Each program instruction is decoded by the
instruction decoder. This unit generates the internal signals controlling the functionsof theindividual
units within the CPU. They have an effect on the source and destination of data transfers, and
control the ALU processing.
The arithmetic section of the processor performs extensive data manipulation and is comprised of
the Arithmetic/Logic Unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit
data words from one or two sources and generates an 8-bit result under the control of the instruction
decoder. The ALU performs the arithmetic operations add, subtract, multiply, divide, increment,
decrement, BCD-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive
OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean
processor performing the bit operations of set, clear, complement, jump-if-not-set, jump-if-set-and-
clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag,
it can perform the bit operations of logical AND or logical OR with the result returned to the carry
flag. The A, B and PSW registers are described in section 4.4.
The program control section controls the sequence in which the instructions stored in program
memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to
be executed. The PC is manipulated by the control transfer instructions listed in the chapter
"Instruction Set". The conditional branch logic enables internal and external events to the processor
to cause a change in the program execution sequence.
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Semiconductor Group 17
Central Processing Unit
3.2 CPU Timing
A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a phase 1
half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is
active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (state 1, phase 1)
through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and
logical operations take place during phase 1 and internal register-to-register transfers take place
during phase 2.
The diagrams in figure 3-1 show the fetch/execute timing related to the internal states and phases.
Since these internal clock signalsare not user-accessible, the XTAL2 oscillator signals and the ALE
(address latch enable) signal are shown for external reference. ALE is normally activated twice
during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.
Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction
register. lf it is a two-byte instruction, the second is read during S4 of the same machine cycle. lf it
is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next op-
code) is ignored, and the program counter is not incremented. In any case, execution is completed
at the end of S6P2.
Figures 3-1 A) and B) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle
instruction.
Most SAB 80(C)515 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the
only instructions that take more than two cycles to complete; they take four cycles. Normally two
code bytes are fetched from the program memory during every machine cycle. The only exception
to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that
accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped
while the external data memory is being addressed and strobed. Figures 3-1 C) and D) show the
timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.
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Semiconductor Group 18
Central Processing Unit
Figure 3-1
Fetch/Execute Sequence
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Semiconductor Group 19
Memory Organization
4 Memory Organization
The SAB 80(C)515 CPU manipulates operands in the following four address spaces:
– up to 64 Kbyte of program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– a 128-byte special function register area
4.1 Program Memory
The program memory of the SAB 80(C)515 consists of an internal and an external memory portion
(see figure 4-1). 8 Kbyte of program memory may reside on-chip (SAB 80C515/80515 only), while
the SAB 80C535/80535 has no internal ROM. The program memory can be externally expanded
up to 64 Kbyte. If the EA pin is held high, the SAB 80(C)515 executes out of the internal program
memory unless the address exceeds 1FFFH. Locations 2000Hthrough 0FFFFHare then fetched
from the external memory. If the EA pin is held low, the SAB 80(C)515 fetches all instructions from
the external program memory. Since the SAB 80C535/80535 has no internal program memory, pin
EA must be tied low when using this device. In either case, the 16-bit program counter is the
addressing mechanism.
Locations 03Hthrough 93Hin the program memory are used by interrupt service routines.
4.2 Data Memory
The data memory address space consists of an internal and an external memory portion.
Internal Data Memory
The internal data memory address space is divided into three physically separate and distinct
blocks: the lower 128 bytes of RAM, the upper 128-byte RAM area, and the 128-byte special
function register (SFR) area (see figure 4-2). Since the latter SFR area and the upper RAM area
share the same address locations, they must be accessed through different addressing modes. The
map in figure 4-2 and the following table show the addressing modes used for the different RAM/
SFR spaces.
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Semiconductor Group 20
Memory Organization
For details about the addressing modes see chapter 9.1.
Figure 4-1
Program Memory Address Space
The lower 128 bytes of the internal RAM are again grouped in three address spaces
(see figure 4-3):
1) A general purpose register area occupies locations 0 through 1FH(see also section 4.3).
2) The next 16 bytes, location 20Hthrough 2FH, contain 128 directly addressable bits.
Programming information: These bits can be referred to in two ways, both of which are
acceptable for the ASM51. One way is to refer to their bit addresses, i.e. 0 to 7FH. The other
way is by referencing to bytes 20Hto 2FH. Thus bits 0 to 7 can also be referred to as bits 20.0
to 20.7, and bits 08Hand 0FHare the same as 21.0 to 21.7 and so on. Each of the 16 bytes in
this segment may also be addressed as a byte.)
3) Locations 30Hto 7FHcan be used as a scratch pad area.
Address Space Locations Addressing Mode
Lower 128 bytes of RAM 00Hto 7FHdirect/indirect
Upper 128 bytes of RAM 80Hto 0FFHindirect
Special function registers 80Hto 0FFHdirect
*