Siemens C541U User manual

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Semiconductor
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Edition 04.99
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1999.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
C541U User’s Manual
Revision History : 04.99
Previous Releases : 11.97(Original Version)
Page
(previous
version)
Page
(new
version)
Subjects (changes since last revision)
All chapters
All chapters
1-2
1-2
1-2
1-4
1-5
1-6 to 1-9
1-5
3-1
3-5
3-7
3-8
6-1
6-34
6-53
6-56
6-58
6-61
6-75
6-78
7-2
7-7
7-11
7-12
10-3
10-4 to 10-5
Chapter 11
All chapters
All chapters
1-2
1-2
1-2
1-4
1-5
1-5 to 1-8
1-5
3-1
3-5
3-7
3-8
6-1
6-34
6-53
6-56
6-58
6-61
6-75
6-88
7-2
7-7
7-12
7-13
10-3
10-3 to 10-4
-
All references to C540U is removed.
VCC is changed to VDD.
USB feature list; Compliant to USB Specification “Rev 1.0”.
Power supply voltage range changed to 4.25V to 5.5V.
Last line; “* P-SDIP-52 package ...” is added.
Figure 1-3; pin 2 is changed to ECAP.
Figure 1-4 is removed.
Table 1-1; column P-SDIP-52 is deleted and any references to P-SDIP-52 is
also removed, the definition of pin 2 is changed to ECAP.
Table 1-2; functionality of Port 1 and 3 is added with the sentence “The pins
with LED drive ... :
Correction in text: 8 KByte (only) on-chip OTP program memory.
Table 3-1; modified with addition of USB Low Speed registers.
Table 3-2; modified with addition of bit DRVI in GEPIR register and USB Low
Speed registers.
Table 3-3; modified with addition of bit DRVIE in DPWDR register.
The first sentence of 6.1 is modified, to remove reference to P-SDIP-52
package.
Seventh line “The following sections ...” is added.
Last paragraph of 6.4.6.1 is added.
Sentence “Sequence of two ...” is added.
The definition of GEPIR register is added with bit DRVI.
The definition of DPWDR register is added with bit DRVIE and XVREG.
Section 6.4.8 Low Speed Mode is added.
Figure 6-39 is removed, as well as any references to it.
Figure 7-2 is modified to include USB Low Speed interrupts.
Definition of DRVIE, SUSPIE and DADDIE are added.
End of first paragraph; “(and GEPIR ...” is added.
Definition of DRVI, SUSP and DADD flag are added.
Figure 10-3 is removed.
Table 10-1; column P-SDIP-52 is removed.
The whole chapter is moved to the C541U Data Sheet.

Critical components1of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2with the express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-
dangered.

Semiconductor Group 1-1 1999-04-01
Table of Contents Page
General Information
C541U
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.4 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.1.3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . .4-3
4.4 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.5 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
5 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5.3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
5.4 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.1.1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
6.1.1.1 Basic Port Circuirty of Port 1 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.1.1.2 SSC Port Pins of Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6
6.1.1.3 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
6.1.1.4 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9
6.1.2 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10
6.1.3 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12
6.1.3.1 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12
6.1.3.2 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13
6.1.3.3 Read-Modify-Write Feature of Ports 1,2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . .6-14
6.2 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15
6.2.1 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15
6.2.1.1 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-16
6.2.1.2 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19
6.2.1.3 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20
6.2.1.4 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21

Semiconductor Group 1-2 1999-04-01
Table of Contents Page
General Information
C541U
6.2.1.5 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22
6.3 SSC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23
6.3.1 General Operation of the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24
6.3.2 Enable/Disable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24
6.3.3 Baudrate Generation (Master Mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25
6.3.4 Write Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25
6.3.5 Master/Slave Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26
6.3.6 Data/Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27
6.3.6.1 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27
6.3.6.2 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28
6.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29
6.4 USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-34
6.4.1 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35
6.4.2 USB Memory Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-36
6.4.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-36
6.4.2.2 Single Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37
6.4.2.2.1 USB Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37
6.4.2.2.2 USB Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-39
6.4.2.3 Dual Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-42
6.4.3 USB Memory Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-49
6.4.4 USB Memory Buffer Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-50
6.4.5 Initialization of USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51
6.4.6 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.6.1 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.6.2 Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.6.3 Status Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.7 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54
6.4.7.1 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-55
6.4.7.2 Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59
6.4.7.3 Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-66
6.4.8 Low Speed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75
6.4.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75
6.4.8.2 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3.1 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3.2 Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3.3 Status Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.4 Interrupt Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-77
6.4.8.5 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-78
6.4.8.6 USB Low Speed Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-83
6.4.9 On-Chip USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-84
6.4.10 Detection of Connected Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-86
6.4.11 Detach / Attach Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87
6.4.11.1 Self-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87
6.4.11.2 Bus-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87

Semiconductor Group 1-3 1999-04-01
Table of Contents Page
General Information
C541U
7 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.1.1 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.1.2 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10
7.1.3 Interrupt Prioritiy Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16
7.2 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
7.3 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
7.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
7.5 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
8 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.1 Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.1.1 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
8.1.2 Watchdog Timer Control / Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
8.1.3 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.1.4 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.1.5 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.2 Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5
8.2.1 Functionality of the Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
8.2.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.1.1 Entering Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
9.1.2 Exit from Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
9.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.2.1 Entering Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.2.2 Exit from Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.2.2.1 Exit via Pin P3.2/INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.2.2.2 Exit via UBS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
10 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
10.3 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
10.4 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
10.4.1 Basic Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
10.4.2 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6
10.5 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7
10.6 Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9
10.7 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11
10.8 OTP Verify with Protection Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12
11 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1

Semiconductor Group 1-1 1997-10-01
Introduction
C541U
1 Introduction
The C541U is a member of the Siemens C500 family of 8-bit microcontrollers They are fully
compatible to the standard 80C51 architecture.
The C541U especially provides an on-chip USB module compliant to the USB specification, which
is capable to operate either in low or full speed mode. The five endpoints can be easily controlled
by the CPU via special function registers. Due to the on-chip USB transceiver circuits the C541U
can be directly connected to the USB bus.
Figure 1-1 shows the different functional units of the C541U and figure 1-2 shows the simplified
logic symbol of the C541U.
Figure 1-1
C541U Functional Units
T0
T1
CPU
Port 0
Port 1
Port 2
Port 3
I/O
I/O
OTP Prog. Memory
Watchdog
I/O
I/O
On-Chip Emulation Support Module
Module
RAM
256 × 8
Timer
Oscillator
Watchdog
Power
Saving
Modes
SSC
USB Transceiver
D+ D-
USB
8k×8

Semiconductor Group 1-2 1997-10-01
Introduction
C541U
Listed below is a summary of the main features of the C541U :
•Enhanced 8-bit C500 CPU
– Full software/toolset compatible to standard 80C51/80C52 microcontrollers
•12 MHz external operating frequency
– 500 ns instruction cycle
•Built-in PLL for USB synchronization
•On-chip OTP program memory
– 8K byte
– Alternatively up to 64K byte external program memory
– Optional memory protection
•Up to 64K byte external data memory
•256 byte on-chip RAM
•Four parallel I/O ports
– P-LCC-44 package : three 8-bit ports and one 6-bit port
– P-SDIP-52* package : four 8-bit ports
– LED current drive capability for 3 pins (10 mA)
•Two 16-bit timer/counters (C501 compatible)
•On-chip USB module
– Compliant to USB specification Rev1.0
– Full speed or low speed operation
– Five endpoints : one bidirectional control endpoint
four versatile programmable endpoints
– Registers are located in special function register area
– On-chip USB transceiver
•SSC synchronous serial interface (SPI compatible)
– Master and slave capable
– Programmable clock polarity / clock-edge to data phase relation
– LSB/MSB first selectable
– 1.5 MBaud transfer rate at 12 MHz operating frequency
•7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels
•Enhanced fail safe mechanisms
– Programmable watchdog timer
– Oscillator watchdog
•Power saving modes
– idle mode
– software power down mode with wake-up capability through INT0 pin or USB
•On-chip emulation support logic (Enhanced Hooks TechnologyTM)
•P-LCC-44 and P-SDIP-52* packages
•Power supply voltage range : 4.25V to 5.5V
•Temperature Range : SAB-C541U TA= 0 to 70 °C
* P-SDIP-52 package is available on specific request from customer

Semiconductor Group 1-3 1997-10-01
Introduction
C541U
Figure 1-2
Logic Symbol
Port 0
8-bit Digital I/O
RESET
EA
ALE
PSEN
XTAL2
XTAL1
Port 1
6-bit Digital I/O
Port 2
8-bit Digital I/O
Port 3
8-bit Digital I/O
VSS
VDD
D+
D-
C541U