Siemens C541U User manual

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Semiconductor
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Edition 04.99
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1999.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
C541U User’s Manual
Revision History : 04.99
Previous Releases : 11.97(Original Version)
Page
(previous
version)
Page
(new
version)
Subjects (changes since last revision)
All chapters
All chapters
1-2
1-2
1-2
1-4
1-5
1-6 to 1-9
1-5
3-1
3-5
3-7
3-8
6-1
6-34
6-53
6-56
6-58
6-61
6-75
6-78
7-2
7-7
7-11
7-12
10-3
10-4 to 10-5
Chapter 11
All chapters
All chapters
1-2
1-2
1-2
1-4
1-5
1-5 to 1-8
1-5
3-1
3-5
3-7
3-8
6-1
6-34
6-53
6-56
6-58
6-61
6-75
6-88
7-2
7-7
7-12
7-13
10-3
10-3 to 10-4
-
All references to C540U is removed.
VCC is changed to VDD.
USB feature list; Compliant to USB Specification “Rev 1.0”.
Power supply voltage range changed to 4.25V to 5.5V.
Last line; “* P-SDIP-52 package ...” is added.
Figure 1-3; pin 2 is changed to ECAP.
Figure 1-4 is removed.
Table 1-1; column P-SDIP-52 is deleted and any references to P-SDIP-52 is
also removed, the definition of pin 2 is changed to ECAP.
Table 1-2; functionality of Port 1 and 3 is added with the sentence “The pins
with LED drive ... :
Correction in text: 8 KByte (only) on-chip OTP program memory.
Table 3-1; modified with addition of USB Low Speed registers.
Table 3-2; modified with addition of bit DRVI in GEPIR register and USB Low
Speed registers.
Table 3-3; modified with addition of bit DRVIE in DPWDR register.
The first sentence of 6.1 is modified, to remove reference to P-SDIP-52
package.
Seventh line “The following sections ...” is added.
Last paragraph of 6.4.6.1 is added.
Sentence “Sequence of two ...” is added.
The definition of GEPIR register is added with bit DRVI.
The definition of DPWDR register is added with bit DRVIE and XVREG.
Section 6.4.8 Low Speed Mode is added.
Figure 6-39 is removed, as well as any references to it.
Figure 7-2 is modified to include USB Low Speed interrupts.
Definition of DRVIE, SUSPIE and DADDIE are added.
End of first paragraph; “(and GEPIR ...” is added.
Definition of DRVI, SUSP and DADD flag are added.
Figure 10-3 is removed.
Table 10-1; column P-SDIP-52 is removed.
The whole chapter is moved to the C541U Data Sheet.

Critical components1of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2with the express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-
dangered.

Semiconductor Group 1-1 1999-04-01
Table of Contents Page
General Information
C541U
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
1.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
2 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1 Program Memory, "Code Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.2 Data Memory, "Data Space" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.4 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
4 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.1 Role of P0 and P2 as Data/Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.1.3 External Program Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.2 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.3 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . . . . .4-3
4.4 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.5 Enhanced Hooks Emulation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
5 Reset and System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.1 Hardware Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5.3 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
5.4 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
6 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.1 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.1.1 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
6.1.1.1 Basic Port Circuirty of Port 1 to 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
6.1.1.2 SSC Port Pins of Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-6
6.1.1.3 Port 0 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
6.1.1.4 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9
6.1.2 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-10
6.1.3 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12
6.1.3.1 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-12
6.1.3.2 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-13
6.1.3.3 Read-Modify-Write Feature of Ports 1,2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . .6-14
6.2 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15
6.2.1 Timer/Counter 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-15
6.2.1.1 Timer/Counter 0 and 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-16
6.2.1.2 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-19
6.2.1.3 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20
6.2.1.4 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-21

Semiconductor Group 1-2 1999-04-01
Table of Contents Page
General Information
C541U
6.2.1.5 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-22
6.3 SSC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-23
6.3.1 General Operation of the SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24
6.3.2 Enable/Disable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-24
6.3.3 Baudrate Generation (Master Mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25
6.3.4 Write Collision Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-25
6.3.5 Master/Slave Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-26
6.3.6 Data/Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27
6.3.6.1 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-27
6.3.6.2 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-28
6.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-29
6.4 USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-34
6.4.1 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-35
6.4.2 USB Memory Buffer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-36
6.4.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-36
6.4.2.2 Single Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37
6.4.2.2.1 USB Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-37
6.4.2.2.2 USB Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-39
6.4.2.3 Dual Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-42
6.4.3 USB Memory Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-49
6.4.4 USB Memory Buffer Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-50
6.4.5 Initialization of USB Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-51
6.4.6 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.6.1 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.6.2 Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.6.3 Status Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-53
6.4.7 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-54
6.4.7.1 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-55
6.4.7.2 Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-59
6.4.7.3 Endpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-66
6.4.8 Low Speed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75
6.4.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-75
6.4.8.2 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3.1 Setup Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3.2 Data Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.3.3 Status Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-76
6.4.8.4 Interrupt Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-77
6.4.8.5 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-78
6.4.8.6 USB Low Speed Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-83
6.4.9 On-Chip USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-84
6.4.10 Detection of Connected Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-86
6.4.11 Detach / Attach Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87
6.4.11.1 Self-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87
6.4.11.2 Bus-Powered Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-87

Semiconductor Group 1-3 1999-04-01
Table of Contents Page
General Information
C541U
7 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.1 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.1.1 Interrupt Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4
7.1.2 Interrupt Request / Control Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10
7.1.3 Interrupt Prioritiy Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16
7.2 Interrupt Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
7.3 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
7.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
7.5 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
8 Fail Safe Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.1 Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.1.1 Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
8.1.2 Watchdog Timer Control / Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
8.1.3 Starting the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.1.4 Refreshing the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.1.5 Watchdog Reset and Watchdog Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
8.2 Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5
8.2.1 Functionality of the Oscillator Watchdog Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
8.2.2 Fast Internal Reset after Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
9 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.1.1 Entering Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
9.1.2 Exit from Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
9.2 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.2.1 Entering Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
9.2.2 Exit from Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
9.2.2.1 Exit via Pin P3.2/INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
9.2.2.2 Exit via UBS Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
10 OTP Memory Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.1 Programming Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
10.3 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
10.4 Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
10.4.1 Basic Programming Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
10.4.2 OTP Memory Access Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-6
10.5 Program / Read OTP Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7
10.6 Lock Bits Programming / Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9
10.7 Access of Version Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11
10.8 OTP Verify with Protection Level 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12
11 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1

Semiconductor Group 1-1 1997-10-01
Introduction
C541U
1 Introduction
The C541U is a member of the Siemens C500 family of 8-bit microcontrollers They are fully
compatible to the standard 80C51 architecture.
The C541U especially provides an on-chip USB module compliant to the USB specification, which
is capable to operate either in low or full speed mode. The five endpoints can be easily controlled
by the CPU via special function registers. Due to the on-chip USB transceiver circuits the C541U
can be directly connected to the USB bus.
Figure 1-1 shows the different functional units of the C541U and figure 1-2 shows the simplified
logic symbol of the C541U.
Figure 1-1
C541U Functional Units
T0
T1
CPU
Port 0
Port 1
Port 2
Port 3
I/O
I/O
OTP Prog. Memory
Watchdog
I/O
I/O
On-Chip Emulation Support Module
Module
RAM
256 × 8
Timer
Oscillator
Watchdog
Power
Saving
Modes
SSC
USB Transceiver
D+ D-
USB
8k×8

Semiconductor Group 1-2 1997-10-01
Introduction
C541U
Listed below is a summary of the main features of the C541U :
•Enhanced 8-bit C500 CPU
– Full software/toolset compatible to standard 80C51/80C52 microcontrollers
•12 MHz external operating frequency
– 500 ns instruction cycle
•Built-in PLL for USB synchronization
•On-chip OTP program memory
– 8K byte
– Alternatively up to 64K byte external program memory
– Optional memory protection
•Up to 64K byte external data memory
•256 byte on-chip RAM
•Four parallel I/O ports
– P-LCC-44 package : three 8-bit ports and one 6-bit port
– P-SDIP-52* package : four 8-bit ports
– LED current drive capability for 3 pins (10 mA)
•Two 16-bit timer/counters (C501 compatible)
•On-chip USB module
– Compliant to USB specification Rev1.0
– Full speed or low speed operation
– Five endpoints : one bidirectional control endpoint
four versatile programmable endpoints
– Registers are located in special function register area
– On-chip USB transceiver
•SSC synchronous serial interface (SPI compatible)
– Master and slave capable
– Programmable clock polarity / clock-edge to data phase relation
– LSB/MSB first selectable
– 1.5 MBaud transfer rate at 12 MHz operating frequency
•7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels
•Enhanced fail safe mechanisms
– Programmable watchdog timer
– Oscillator watchdog
•Power saving modes
– idle mode
– software power down mode with wake-up capability through INT0 pin or USB
•On-chip emulation support logic (Enhanced Hooks TechnologyTM)
•P-LCC-44 and P-SDIP-52* packages
•Power supply voltage range : 4.25V to 5.5V
•Temperature Range : SAB-C541U TA= 0 to 70 °C
* P-SDIP-52 package is available on specific request from customer

Semiconductor Group 1-3 1997-10-01
Introduction
C541U
Figure 1-2
Logic Symbol
Port 0
8-bit Digital I/O
RESET
EA
ALE
PSEN
XTAL2
XTAL1
Port 1
6-bit Digital I/O
Port 2
8-bit Digital I/O
Port 3
8-bit Digital I/O
VSS
VDD
D+
D-
C541U

Semiconductor Group 1-4 1997-10-01
Introduction
C541U
1.1 Pin Configuration
This section describes the pin configurations of the C541U in the P-LCC-44 package.
Figure 1-3
Pin Configuration(top view)
P1.5/SLS
P1.3/SRI
6
7
8
9
10
11
12
13
14
15
16
17
5 4 3 2 1 4443424140
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27
P1.1/LED1 P1.0/LED0 D- D+ ECAP VDDU
P1.2/SCLK
VDD
VSS
P3.0/LED2
P3.1/DADD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2 XTAL1
VSS
VDD
P2.0/A8 P2.1/A9
P2.2/A10 P2.3/A11 P2.4/A12
RESET
P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P1.4/STO
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
ALE
28
C541U

Semiconductor Group 1-5 1997-10-01
Introduction
C541U
1.2 Pin Definitions and Functions
This section describes all external signals of the C541U with its function.
Table 1-1
Pin Definitions and Functions
Symbol Pin
Numbers I/O*) Function
P-LCC-44
D+ 3 I/O USB D+ Data Line
The pin D+ can be directly connected to USB cable (transceiver
is integrated on-chip).
D- 4 I/O USB D- Data Line
The pin D- can be directly connected to USB cable(transceiver is
integrated on-chip).
P1.0 - P1.4 5 - 7,
12, 34, 44
5
6
7
12
34
44
I/O Port 1
is an 6-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1’s written to them are pulled high
by the internal pullup resistors, and in that state can be used as
inputs. As inputs, port 1 pins being externally pulled low will
source current (IIL, in the DC characteristics) because of the
internal pullup resistors.
Port 1 also contains two outputs with LED drive capability as well
as the fourpins of theSSC. The pinswith LED drive capability are
able to sink current up to 10 mA. The output latch corresponding
to a secondary function must be programmed to a one (1) for that
functiontooperate(exceptwhenusedforthecomparefunctions).
The secondary functions are assigned to the port 1 pins as
follows :
P1.0 / LED0 LED0 output
P1.1 / LED1 LED1 output
P1.2 / SCLK SSC Master Clock Output /
SSC Slave Clock Input
P1.3 / SRI SSC Receive Input
P1.4 / STO SSC Transmit Output
P1.5 / SLS SSC Slave Select Inp.
RESET 10 I RESET
A high level on this pin for the duration of two machine cycles
while the oscillator is running resets the C541U. A small internal
pulldown resistor permits power-on reset using only a capacitor
connected to VDD.
*) I = Input
O = Output

Semiconductor Group 1-6 1997-10-01
Introduction
C541U
P3.0 - P3.7 11, 13 - 19
11
13
14
15
16
17
18
19
I/O Port 3
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1’s written to them are pulled high
by the internal pullup resistors, and in that state can be used as
inputs. As inputs, port 3 pins being externally pulled low will
source current (IIL, in the DC characteristics) because of the
internal pullup resistors. Port 3 also contains the interrupt, timer,
serial port and external memory strobe pins that are used by
various options. The pin with LED drive capability is able to sink
current up to 10 mA. The output latch corresponding to a
secondary function must be programmed to a one (1) for that
function to operate. The secondary functions are assigned to the
pins of port 3, as follows:
P3.0 / LED2 LED2 output
P3.1 / DADD Device attached input
P3.2 / INT0 External interrupt 0 input /
timer 0 gate control input
P3.3 / INT1 External interrupt 1 input /
timer 1 gate control input
P3.4 / T0 Timer 0 counter input
P3.5 / T1 Timer 1 counter input
P3.6 / WR WR control output; latches the
data byte from port 0 into the
external data memory
P3.7 / RD RD control output; enables the
external data memory
XTAL2 20 –XTAL2
is the output of the inverting oscillator amplifier. This pin is used
for the oscillator operation with crystal or ceramic resonator.
XTAL1 21 – XTAL1
is the input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. Minimum and
maximum high and low times as well as rise/fall times specified in
the AC characteristics must be observed.
*) I = Input
O = Output
Table 1-1
Pin Definitions and Functions (cont’d)
Symbol Pin
Numbers I/O*) Function
P-LCC-44

Semiconductor Group 1-7 1997-10-01
Introduction
C541U
P2.0 - P2.7 24 - 31 I/O Port 2
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1’s written to them are pulled high
by the internal pullup resistors, and in that state can be used as
inputs. As inputs, port 2 pins being externally pulled low will
source current (IIL, in the DC characteristics) because of the
internal pullup resistors.
Port 2 emits the high-order address byte during fetches from
external program memory and during accesses to external data
memory that use 16-bit addresses (MOVX @DPTR). In this
application it uses strong internal pullup resistors when issuing
1’s. During accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of the P2
special function register.
PSEN 32 O The Program Store Enable
output is a control signal that enables the external program
memory to the busduring external fetch operations.It is activated
everythreeoscillatorperiodsexceptduringexternaldatamemory
accesses. The signal remains high during internal program
execution.
ALE 33 O The Address Latch enable
output is used for latching the address into external memory
during normal operation. It is activated every three oscillator
periods except during an external data memory access.
EA 35 I External Access Enable
When held high, the C541U executes instructions from the
internal OTP program memory as long as the PC is less than
2000Hfor the C541U. When held low, the C541U fetches all
instructionsfrom externalprogrammemory.Forthe C541U-L this
pin must be tied low.
P0.0 - P0.7 43 - 36 I/O Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have
1’s written to them float, and in that state can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application it uses strong internal pullup
resistors when issuing 1’s.
*) I = Input
O = Output
Table 1-1
Pin Definitions and Functions (cont’d)
Symbol Pin
Numbers I/O*) Function
P-LCC-44

Semiconductor Group 1-8 1997-10-01
Introduction
C541U
ECAP 2 –External Capacitor
This pin is required to be connected to an external capacitor
which is connected to VSS. The value of the capacitor is 6 nF.
VDDU 1–Supply voltage
for the on-chip USB transceiver circuitry.
VDD 8, 23 – Supply voltage
for ports and internallogic circuitry during normal, idle, and power
down mode.
VSS 9, 22 – Ground (0V)
during normal, idle, and power down mode.
*) I = Input
O = Output
Table 1-1
Pin Definitions and Functions (cont’d)
Symbol Pin
Numbers I/O*) Function
P-LCC-44
C541U
2
VSS
C

Semiconductor Group 2-1 1997-10-01
Fundamental Structure
C541U
2 Fundamental Structure
The C541U is fully compatible to the architecture of the standard 8051/C501 microcontroller family.
While maintaining the typical architectural characteristics of the C501, the C541U incorporates a
SSC synchronous serial interface, a versatile USB module as well as some enhancements in the
Fail Save Mechanism Unit.
Figure 2-1 shows a block diagram of the C541U.
Figure 2-1
Block Diagram of the C541U
Port 0
8-bit digit. I/O
Port 2
8-bit digit. I/O
Port 3
8-bit digit. I/O
Port 0
Port 1
Port 2
Port 3
OSC & Timing
CPU
Timer 0
Interrupt Unit
XTAL2
XTAL1
RESET
ALE
PSEN
EA
Port 1
6-bit digit. I/O
256 x 8
RAM
Timer
Progr. Watchdog
Emulation
Support
Logic
Oscillator Watchdog OTP
Timer 1
SSC (SPI) Interface
USB
Module
Memory
D+
D-
C541U
8k x 8
PLL
Transceiver

Semiconductor Group 2-2 1997-10-01
Fundamental Structure
C541U
2.1 CPU
The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes,
are performed in one, two or four machine cycles. One machine cycle requires six oscillator cycles
(this number of oscillator cycles differs from other members of the C500 microcontroller family). The
instruction set has extensive facilities for data transfer, logic and arithmetic instructions. The
Boolean processor has its own full-featured and bit-based instructions within the instruction set. The
C541U uses five addressing modes: direct access, immediate, register, register indirect access,
and for accessing the external data or program memory portions a base register plus index-register
indirect addressing. Efficient use of program memory results from an instruction set consisting of
44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz clock, 58% of the
instructions execute in 500 ns.
The CPU (Central Processing Unit) of the C541U consists of the instruction decoder, the arithmetic
section and the program control section. Each program instruction is decoded by the instruction
decoder. This unit generates the internal signals controlling the functions of the individual units
within the CPU. They have an effect on the source and destination of data transfers and control the
ALU processing.
The arithmetic section of the processor performs extensive data manipulation and is comprised of
the arithmetic/logic unit (ALU), an A register, B register and PSW register.
The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the
control of the instruction decoder. The ALU performs the arithmetic operations add, substract,
multiply, divide, increment, decrement, BDC-decimal-add-adjust and compare, and the logic
operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)).
Also included is a Boolean processor performing the bit operations as set, clear, complement, jump-
if-not-set, jump-if-set-and-clear and move to/from carry. Between any addressable bit (or its
complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with
the result returned to the carry flag.
The program control section controls the sequence in which the instructions stored in program
memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to
be executed. The conditional branch logic enables internal and external events to the processor to
cause a change in the program execution sequence.
Accumulator
ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific
instructions, however, refer to the accumulator simply as A.
Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the current state of the
CPU.

Semiconductor Group 2-3 1997-10-01
Fundamental Structure
C541U
Special Function Register PSW (Address D0H) Reset Value : 00H
B Register
The B register is used during multiply and divide and serves as both source and destination. For
other instructions it can be treated as another scratch pad register.
Stack Pointer
The stack pointer (SP) register is 8 bits wide. It is incremented before data is stored during PUSH
and CALL executions and decremented after data is popped during a POP and RET (RETI)
execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in
the on-chip RAM, the stack pointer is initialized to 07Hafter a reset. This causes the stack to begin
a location = 08Habove register bank zero. The SP can be read or written under software control.
Bit Function
CY Carry Flag
Used by arithmetic instruction.
AC Auxiliary Carry Flag
Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1
RS0 Register Bank select control bits These bits are used to select one of the four register banks.
OV Overflow Flag
Used by arithmetic instruction.
F1 General Purpose Flag
PParity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
CY AC F0 RS1 RS0 OV F1 PD0HPSW
D7HD6HD5HD4HD3HD2HD1HD0H
Bit No. MSB LSB
RS1 RS0 Function
0 0 Bank 0 selected, data address 00H-07H
0 1 Bank 1 selected, data address 08H-0FH
1 0 Bank 2 selected, data address 10H-17H
1 1 Bank 3 selected, data address 18H-1FH

Semiconductor Group 2-4 1997-10-01
Fundamental Structure
C541U
2.2 CPU Timing
The C541U has no clock prescaler. Therefore, a machine cycle of the C541U consists of 6 states
(6 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine
cycle consists of 6 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6,
phase 2). Each state lasts one oscillator period. Typically, arithmetic and logic operations take place
during phase 1 and internal register-to-register transfers take place during phase 2.
The diagrams in figure 2-2 show the fetch/execute timing related to the internal states and phases.
Since these internal clock signalsare not user-accessible, the XTAL2 oscillator signals andthe ALE
(address latch enable) signal are shown for external reference. ALE is normally activated twice
during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1.
Executing of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction
register. If it is a two-byte instruction, the second reading takes place during S4 of the same
machine cycle. If itis a one-byte instruction, there isstilla fetch atS4, but thebyte read (which would
be the next op-code) is ignored (discarded fetch), and the program counter is not incremented. In
any case, execution is completed at the end of S6P2.
Figures 2-2 (a) and (b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle
instruction.

Semiconductor Group 2-5 1997-10-01
Fundamental Structure
C541U
Figure 2-2
Fetch Execute Sequence
S1
P1 P2 P1 P2
S2 P1 P2 P1 P2 S3 S4 P1 P2 P1 P2 S5 S6 P1 P2 P1 P2 S1 S2 P1 P2 P1 P2 S3 S4 P1 P2 P1 P2 S5 S6
OSC
(XTAL2)
ALE
Read
Opcode Read Next Opcode (Discard)
S1 S2 S3 S4 S5 S6
(a) 1-Byte, 1-Cycle Instruction, e. g. INC A
Opcode Again
Read Next
(b) 2-Byte, 1-Cycle Instruction, e. g. ADD A #DATA
Read
Opcode
S1 S2
Byte
Read 2nd
S4
S3 S5 S6
Opcode
Read Next
S6S5
S3 S4S2S1
Opcode
Read Read Next Opcode (Discard)
S1 S2 S4S3 S5 S6
Read Next
Opcode Again
(c) 1-Byte, 2-Cycle Instruction, e. g. INC DPTR
(d) MOVX (1-Byte, 2-Cycle)
S4S1 S2 S3 S5 S6 S1 S3S2 S4 S5 S6
Read
Opcode
(MOVX) (Discard)
Opcode
Read Next No Fetch
No ALE No Fetch
Read Next Opcode Again
ADDR DATA
Access of External Memory MCD03287