Silicon Laboratories Si8410 User manual

Rev. 1.5 9/13 Copyright © 2013 by Silicon Laboratories Si8410/20/21
Not Recommended
for NewDesigns
Si8410/20/21
LOW-POWER SINGLE AND DUAL-CHANNEL
DIGITAL ISOLATORS
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices
offering substantial data rate, propagation delay, power, size, reliability,
and external BOM advantages when compared to legacy isolation
technologies. The operating parameters of these products remain stable
across wide temperature ranges throughout their service life. For ease of
design, only VDD bypass capacitors are required.
Data rates up to 150 Mbps are supported, and all devices achieve worst-
case propagation delays of less than 10 ns. All products are safety
certified by UL, CSA, and VDE and support withstand voltages of up to
2.5 kVrms. These devices are available in an 8-pin narrow-body SOIC
package.
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.70–5.5 V
Ultra low power (typical)
5 V Operation:
< 2.1 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Operation:
< 1.8 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
Up to 2500 VRMS isolation
60-year life at rated working
voltage
Precise timing (typical)
<10 ns worst case
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
SOIC-8 narrow body
Industrial automation systems
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communications systems
UL 1577 recognized
Up to 2500 VRMS for 1 minute
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
Ordering Information:
See page 25.

Si8410/20/21
2 Rev. 1.5
Not Recommended
for NewDesigns

Si8410/20/21
Rev. 1.5 3
Not Recommended
for NewDesigns
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . .23
3.2. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Top Marking: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.1. 8-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Si8410/20/21
4 Rev. 1.5
Not Recommended
for NewDesigns
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 °C
Supply Voltage VDD1 2.70 — 5.5 V
VDD2 2.70 — 5.5 V
*Note: The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating
channels, and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 °C
Operating Temperature TA–40 — 125 °C
Supply Voltage (Revision C)3VDD1, VDD2 –0.5 — 5.75 V
Supply Voltage (Revision D)3VDD1, VDD2 –0.5 — 6.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive Channel IO——10mA
Lead Solder Temperature (10 s) — — 260 °C
Maximum Isolation Voltage (1 s) — — 3600 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "5. Ordering Guide" on page 25 for more information.

Si8410/20/21
Rev. 1.5 5
Not Recommended
for NewDesigns
Table 3. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—85—
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—1.3 0.9 2.0 1.4 mA
Si8420Ax, Bx
VDD1
VDD2
—
—2.0 1.6 3.0 2.4 mA
Si8421Ax, Bx
VDD1
VDD2
—
—1.9 1.9 2.9 2.9 mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
6 Rev. 1.5
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—1.3 1.2 2.0 1.8 mA
Si8420Bx
VDD1
VDD2
—
—2.0 2.1 3.0 3.2 mA
Si8421Bx
VDD1
VDD2
—
—2.2 2.2 3.3 3.3 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—1.4 4.6 2.1 5.8 mA
Si8420Bx
VDD1
VDD2
—
—2.2 9.2 3.3 11.5 mA
Si8421Bx
VDD1
VDD2
—
—5.8 5.8 7.3 7.3 mA
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
Rev. 1.5 7
Not Recommended
for NewDesigns
Figure 1. Propagation Delay Timing
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL= 15 pF — 3.8 5.0 ns
Output Fall Time tfCL= 15 pF — 2.8 3.7 ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Start-up Time3tSU —1540µs
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40to125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V

Si8410/20/21
8 Rev. 1.5
Not Recommended
for NewDesigns
Table 4. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—85—
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—1.3 0.9 2.0 1.4 mA
Si8420Ax, Bx
VDD1
VDD2
—
—2.0 1.6 3.0 2.4 mA
Si8421Ax, Bx
VDD1
VDD2
—
—1.9 1.9 2.9 2.9 mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
Rev. 1.5 9
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—1.3 1.2 2.0 1.8 mA
Si8420Bx
VDD1
VDD2
—
—2.0 2.1 3.0 3.2 mA
Si8421Bx
VDD1
VDD2
—
—2.2 2.2 3.3 3.3 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—1.3 3.3 2.0 4.9 mA
Si8420Bx
VDD1
VDD2
—
—2.0 6.5 3.0 8.1 mA
Si8421Bx
VDD1
VDD2
—
—4.4 4.4 5.5 5.5 mA
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate 0—1.0Mbps
Minimum Pulse Width ——250ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
10 Rev. 1.5
Not Recommended
for NewDesigns
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate 0—150Mbps
Minimum Pulse Width ——6.0ns
Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL= 15 pF — 4.3 6.1 ns
Output Fall Time tfCL= 15 pF — 3.0 4.3 ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Start-up Time3tSU —1540µs
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
Rev. 1.5 11
Not Recommended
for NewDesigns
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 2.3 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance2ZO—85—
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
0.8
0.8
1.8
0.8
1.2
1.2
2.7
1.2
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.3
3.0
1.4
1.5
2.0
4.5
2.1
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.3
2.3
2.3
2.0
2.0
3.5
3.5
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—1.3 0.9 2.0 1.4 mA
Si8420Ax, Bx
VDD1
VDD2
—
—2.0 1.6 3.0 2.4 mA
Si8421Ax, Bx
VDD1
VDD2
—
—1.9 1.9 2.9 2.9 mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
12 Rev. 1.5
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—1.3 1.2 2.0 1.8 mA
Si8420Bx
VDD1
VDD2
—
—2.0 2.1 3.0 3.2 mA
Si8421Bx
VDD1
VDD2
—
—2.2 2.2 3.3 3.3 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—1.3 2.7 2.0 4.0 mA
Si8420Bx
VDD1
VDD2
—
—2.0 5.2 3.0 6.5 mA
Si8421Bx
VDD1
VDD2
—
—3.7 3.7 4.6 4.6 mA
Timing Characteristics
Si8410Ax, Si8420Ax, Si8421Ax
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew3tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 5. Electrical Characteristics1(Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
Rev. 1.5 13
Not Recommended
for NewDesigns
Si8410Bx, Si8420Bx, Si8421Bx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 1 — 1.5 2.5 ns
Propagation Delay Skew3tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL= 15 pF — 4.8 6.5 ns
Output Fall Time tfCL= 15 pF — 3.2 4.6 ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Start-up Time4tSU —1540µs
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 130 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 Vpeak for basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 25.
Table 5. Electrical Characteristics1(Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8410/20/21
14 Rev. 1.5
Not Recommended
for NewDesigns
Table 7. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
Nominal Air Gap (Clearance)1L(IO1) 4.9 mm
Nominal External Tracking (Creepage)1L(IO2) 4.01 mm
Minimum Internal Gap (Internal Clearance) 0.008 mm
Tracking Resistance
(Proof Tracking Index) PTI IEC60112 600 VRMS
Erosion Depth ED 0.040 mm
Resistance (Input-Output)2RIO 1012 
Capacitance (Input-Output)2CIO f=1MHz 1.0 pF
Input Capacitance3CI4.0 pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in "6. Package Outline:
8-Pin Narrow Body SOIC" on page 26. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB
SOIC-8 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-8 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–4 are shorted
together to form the first terminal and pins 5–8 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Test Condition Specification
Basic Isolation Group Material Group I
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV
Rated Mains Voltages < 300 VRMS I-III
Rated Mains Voltages < 400 VRMS I-II
Rated Mains Voltages < 600 VRMS I-II

Si8410/20/21
Rev. 1.5 15
Not Recommended
for NewDesigns
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter Symbol Test Condition Characteristic Unit
Maximum Working Insulation Voltage VIORM 560 V peak
Input to Output Test Voltage VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm=1sec,
Partial Discharge < 5 pC) 1050
V peak
Transient Overvoltage VIOTM t = 60 sec 4000 V peak
Pollution Degree (DIN VDE 0110, Table 1) 2
Insulation Resistance at TS, VIO =500V RS>109
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter Symbol Test Condition Min Typ Max Unit
Case Temperature TS——150 °C
Safety input, output, or supply current IS
JA = 140 °C/W,
VI=5.5V,
TJ=150°C,
TA=25°C ——160mA
Device Power Dissipation2PD——150mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
2. The Si841x/2x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.

Si8410/20/21
16 Rev. 1.5
Not Recommended
for NewDesigns
Figure 2. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 11. Thermal Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
IC Junction-to-Air Thermal Resistance JA —140—°C/W
0 20015010050
400
200
100
0
Case Temperature (ºC)
Safety-Limiting Values (mA)
320
300 VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.3 V
VDD1, VDD2 = 5.5 V
270
160

Si8410/20/21
Rev. 1.5 17
Not Recommended
for NewDesigns
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 3.
Figure 3. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 4 for more details.
Figure 4. Modulation Scheme
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Input Signal
Output Signal
Modulation Signal

Si8410/20/21
18 Rev. 1.5
Not Recommended
for NewDesigns
2.2. Eye Diagram
Figure 5 illustrates an eye-diagram taken on an Si8410. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8410 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 5. Eye Diagram

Si8410/20/21
Rev. 1.5 19
Not Recommended
for NewDesigns
2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12.
Table 12. Si84xx Logic Operation Table
VIInput1,4 VDDI State1,2,3 VDDO State1,2,3 VOOutput1,4 Comments
HP P H
Normal operation.
LP P L
X5UP P L Upon transition of VDDI from unpowered to pow-
ered, VOreturns to the same state as VIin less
than 1 µs.
X5P UP Undetermined Upon transition of VDDO from unpowered to pow-
ered, VOreturns to the same state as VIwithin
1µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VIand VOare the respective input and output terminals.
2. Powered (P) state is defined as 2.70 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.

Si8410/20/21
20 Rev. 1.5
Not Recommended
for NewDesigns
2.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 13 and Table 7 on page 14 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.)
requirements before starting any design that uses a digital isolator.
The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
2.4.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100 resistors in series with the VDD supply voltage source and 50 to
300 resistors in series with the digital inputs/outputs (see Figure 6). For more details, see "3. Errata and Design
Migration Guidelines" on page 23.
All components upstream or downstream of the isolator should be properly decoupled as well. If these components
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300 resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended
Operating Conditions,” on page 4.
2.4.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
2.4.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in
mind the recommendations described in “2.4.1. Supply Bypass” above.
Figure 6. Recommended Bypass Components for the Si84xx Digital Isolator Family
VDD1 VDD2
GND1 GND2
50 – 300 50 – 300 
Input/OutputInput/Output
C2 C3
1 F1 F
R1 (50 – 100 )
V Source 1
A1 B1
50 – 300 
50 – 300 
Ax Bx
C1
R2 (50 – 100 )
V Source 2
C4
0.1 F0.1 F