Silicon Laboratories EFR32 G1 Series User manual

EFR32xG1 Wireless Gecko
Reference Manual
The Wireless Gecko portfolio of SoCs (EFR32) include the
EFR32MG1, EFR32BG1, and EFR32FG1 families. With support
for Bluetooth Low Energy (BLE), Zigbee®, Thread and proprietary
protocols, the Wireless Gecko portfolio is ideal for enabling ener-
gy-friendly wireless networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable high-power amplifier, an integrated balun and no-compromise MCU
features.
KEY FEATURES
• 32-bit ARM® Cortex-M4 core with 40 MHz
maximum operating frequency
• Scalable Memory and Radio configuration
options available in several footprint
compatible QFN packages
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
• Integrated balun for 2.4 GHz and
integrated PA with up to 19.5 dBm
transmit power for 2.4 GHz and 20 dBm
transmit power for Sub-GHz radios
• Integrated dc-dc with RF noise mitigation
Lowest power mode with peripheral operational:
EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active
32-bit bus
Peripheral Reflex System
Timers and Triggers
Real Time
Counter and
Calendar
Cryotimer
Timer/Counter
Low Energy
Timer
Pulse Counter
Watchdog Timer
Protocol Timer
Serial
Interfaces
I/O Ports Analog
Interfaces
USART
Low Energy
UARTTM
I2C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
ADC
IDAC
Analog
Comparator
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
MOD
FRC
RAC
Frequency
Synthesizer
PGA
I
Q
RF Frontend
I
Q
RF Frontend
To 2.4 GHz receive
I/Q mixers and PA
To Sub GHz
receive I/Q
mixers and PA
To Sub GHz
and 2.4 GHz PA
Sub GHz
2.4 GHz
Core / Memory
Flash Program
Memory RAM Memory
ARM CortexTM M4 processor
with DSP extensions and FPU
Memory
Protection Unit
Debug Interface DMA Controlller
Other
CRYPTO
CRC
Clock Management
High Frequency
Crystal Oscillator
High Frequency
RC Oscillator
Low Frequency
Crystal Oscillator
Low Frequency
RC Oscillator
Auxiliary High
Frequency RC
Oscillator
Energy Management
Voltage Monitor
Brown-Out
Detector
Power-On ResetDC/DC Regulator
Voltage
Regulators
Ultra Low
Frequency RC
Oscillator
LNA
PA
PA
LNA
BALUN
silabs.com | Building a more connected world. Copyright © 2022 by Silicon Laboratories Rev. 1.3

Table of Contents
1. About This Document ...........................23
1.1 Introduction ...............................23
1.2 Conventions ...............................23
1.3 Related Documentation ...........................24
2. System Overview .............................25
2.1 Introduction ...............................25
2.2 Block Diagrams..............................26
2.3 MCU Features Overview ..........................27
2.4 Oscillators and Clocks ...........................28
2.5 RF Frequency Synthesizer ..........................29
2.6 Modulation Modes .............................29
2.7 Transmit Mode ..............................29
2.8 Receive Mode ..............................29
2.9 Data Buffering ..............................30
2.10 Unbuffered Data Transfer ..........................30
2.11 Frame Format Support ...........................30
2.12 Hardware CRC Support ..........................30
2.13 Convolutional Encoding / Decoding ......................31
2.14 Binary Block Encoding / Decoding .......................31
2.15 Data Encryption and Authentication ......................31
2.16 Timers ................................32
2.17 RF Test Modes .............................32
3. System Processor ............................33
3.1 Introduction ...............................33
3.2 Features ................................34
3.3 Functional Description ...........................34
3.3.1 Interrupt Operation ...........................35
3.3.2 Interrupt Request Lines (IRQ) .......................36
4. Memory and Bus System ..........................37
4.1 Introduction ...............................38
4.2 Functional Description ...........................39
4.2.1 Peripheral Non-Word Access Behavior ....................41
4.2.2 Bit-banding ..............................41
4.2.3 Peripheral Bit Set and Clear ........................42
4.2.4 Peripherals ..............................43
4.2.5 Bus Matrix ..............................43
4.3 Access to Low Energy Peripherals (Asynchronous Registers) ..............46
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4.3.1 Writing ...............................46
4.3.2 Reading ...............................48
4.3.3 FREEZE Register ...........................48
4.4 Flash .................................48
4.5 SRAM .................................49
4.6 DI Page Entry Map ............................50
4.7 DI Page Entry Description ..........................51
4.7.1 CAL - CRC of DI-page and calibration temperature ................51
4.7.2 MODULEINFO - Module trace information ...................52
4.7.3 MODXOCAL - Module Crystal Oscillator Calibration ...............53
4.7.4 EXTINFO - External Component description ..................54
4.7.5 EUI48L - EUI48 OUI and Unique identifier ...................55
4.7.6 EUI48H - OUI ............................55
4.7.7 CUSTOMINFO - Custom information ....................55
4.7.8 MEMINFO - Flash page size and misc. chip information ..............56
4.7.9 UNIQUEL - Low 32 bits of device unique number ................57
4.7.10 UNIQUEH - High 32 bits of device unique number ................57
4.7.11 MSIZE - Flash and SRAM Memory size in kB .................57
4.7.12 PART - Part description .........................58
4.7.13 DEVINFOREV - Device information page revision ................60
4.7.14 EMUTEMP - EMU Temperature Calibration Information ..............60
4.7.15 ADC0CAL0 - ADC0 calibration register 0 ...................61
4.7.16 ADC0CAL1 - ADC0 calibration register 1 ...................62
4.7.17 ADC0CAL2 - ADC0 calibration register 2 ...................63
4.7.18 ADC0CAL3 - ADC0 calibration register 3 ...................63
4.7.19 HFRCOCAL0 - HFRCO Calibration Register (4 MHz) ...............64
4.7.20 HFRCOCAL3 - HFRCO Calibration Register (7 MHz) ...............65
4.7.21 HFRCOCAL6 - HFRCO Calibration Register (13 MHz) ..............66
4.7.22 HFRCOCAL7 - HFRCO Calibration Register (16 MHz) ..............67
4.7.23 HFRCOCAL8 - HFRCO Calibration Register (19 MHz) ..............68
4.7.24 HFRCOCAL10 - HFRCO Calibration Register (26 MHz) ..............69
4.7.25 HFRCOCAL11 - HFRCO Calibration Register (32 MHz) ..............70
4.7.26 HFRCOCAL12 - HFRCO Calibration Register (38 MHz) ..............71
4.7.27 AUXHFRCOCAL0 - AUXHFRCO Calibration Register (4 MHz) ...........72
4.7.28 AUXHFRCOCAL3 - AUXHFRCO Calibration Register (7 MHz) ...........73
4.7.29 AUXHFRCOCAL6 - AUXHFRCO Calibration Register (13 MHz) ...........74
4.7.30 AUXHFRCOCAL7 - AUXHFRCO Calibration Register (16 MHz) ...........75
4.7.31 AUXHFRCOCAL8 - AUXHFRCO Calibration Register (19 MHz) ...........76
4.7.32 AUXHFRCOCAL10 - AUXHFRCO Calibration Register (26 MHz) ..........77
4.7.33 AUXHFRCOCAL11 - AUXHFRCO Calibration Register (32 MHz) ..........78
4.7.34 AUXHFRCOCAL12 - AUXHFRCO Calibration Register (38 MHz) ..........79
4.7.35 VMONCAL0 - VMON Calibration Register 0 ..................80
4.7.36 VMONCAL1 - VMON Calibration Register 1 ..................81
4.7.37 VMONCAL2 - VMON Calibration Register 2 ..................82
4.7.38 IDAC0CAL0 - IDAC0 Calibration Register 0 ..................83
4.7.39 IDAC0CAL1 - IDAC0 Calibration Register 1 ..................84
4.7.40 DCDCLNVCTRL0 - DCDC Low-noise VREF Trim Register 0 ............84
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4.7.41 DCDCLPVCTRL0 - DCDC Low-power VREF Trim Register 0 ............85
4.7.42 DCDCLPVCTRL1 - DCDC Low-power VREF Trim Register 1 ............86
4.7.43 DCDCLPVCTRL2 - DCDC Low-power VREF Trim Register 2 ............87
4.7.44 DCDCLPVCTRL3 - DCDC Low-power VREF Trim Register 3 ............88
4.7.45 DCDCLPCMPHYSSEL0 - DCDC LPCMPHYSSEL Trim Register 0 ..........88
4.7.46 DCDCLPCMPHYSSEL1 - DCDC LPCMPHYSSEL Trim Register 1 ..........89
5. Serial Flash ...............................90
5.1 Introduction ...............................90
5.2 Features ................................90
5.3 Functional Description ...........................91
5.3.1 Memory Organization ..........................92
5.3.2 Serial Interface ............................93
5.3.3 Instruction Set.............................97
5.3.4 Registers ..............................97
5.3.5 Reading Memory ...........................101
5.3.6 Programming and Erasing Memory.....................102
5.3.7 Write Protection ...........................107
5.3.8 Security Information Row and Unique ID ...................108
5.3.9 Power Down ............................111
5.3.10 Software Reset ...........................111
6. Radio Transceiver ............................113
6.1 Introduction ..............................114
7. DBG - Debug Interface ...........................115
7.1 Introduction ..............................115
7.2 Features ...............................115
7.3 Functional Description ..........................115
7.3.1 Debug Pins.............................116
7.3.2 Debug and EM2 DeepSleep/EM3 Stop ...................116
7.3.3 Authentication Access Point .......................116
7.3.4 Debug Lock ............................117
7.3.5 AAP Lock .............................117
7.3.6 Debugger Reads of Actionable Registers ..................118
7.3.7 Debug Recovery ...........................118
7.4 Register Map .............................118
7.5 Register Description ...........................119
7.5.1 AAP_CMD - Command Register .....................119
7.5.2 AAP_CMDKEY - Command Key Register ..................119
7.5.3 AAP_STATUS - Status Register .....................120
7.5.4 AAP_CTRL - Control Register ......................120
7.5.5 AAP_CRCCMD - CRC Command Register .................121
7.5.6 AAP_CRCSTATUS - CRC Status Register .................121
7.5.7 AAP_CRCADDR - CRC Address Register ..................122
7.5.8 AAP_CRCRESULT - CRC Result Register .................122
7.5.9 AAP_IDR - AAP Identification Register ...................123
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8. MSC - Memory System Controller ......................124
8.1 Introduction ..............................124
8.2 Features ...............................125
8.3 Functional Description ..........................126
8.3.1 User Data (UD) Page Description .....................126
8.3.2 Lock Bits (LB) Page Description ......................127
8.3.3 Device Information (DI) Page ......................127
8.3.4 Bootloader .............................128
8.3.5 Post-reset Behavior ..........................128
8.3.6 Flash Startup ............................128
8.3.7 Wait-states .............................128
8.3.8 Suppressed Conditional Branch Target Prefetch (SCBTP) .............129
8.3.9 Cortex-M4 If-Then Block Folding .....................129
8.3.10 Instruction Cache ..........................130
8.3.11 Erase and Write Operations.......................131
8.4 Register Map .............................132
8.5 Register Description ...........................133
8.5.1 MSC_CTRL - Memory System Control Register ................133
8.5.2 MSC_READCTRL - Read Control Register .................134
8.5.3 MSC_WRITECTRL - Write Control Register .................135
8.5.4 MSC_WRITECMD - Write Command Register ................136
8.5.5 MSC_ADDRB - Page Erase/Write Address Buffer ...............137
8.5.6 MSC_WDATA - Write Data Register ....................137
8.5.7 MSC_STATUS - Status Register .....................138
8.5.8 MSC_IF - Interrupt Flag Register .....................139
8.5.9 MSC_IFS - Interrupt Flag Set Register ...................140
8.5.10 MSC_IFC - Interrupt Flag Clear Register ..................141
8.5.11 MSC_IEN - Interrupt Enable Register ...................142
8.5.12 MSC_LOCK - Configuration Lock Register .................143
8.5.13 MSC_CACHECMD - Flash Cache Command Register .............144
8.5.14 MSC_CACHEHITS - Cache Hits Performance Counter .............144
8.5.15 MSC_CACHEMISSES - Cache Misses Performance Counter ...........145
8.5.16 MSC_MASSLOCK - Mass Erase Lock Register ...............146
8.5.17 MSC_STARTUP - Startup Control ....................147
8.5.18 MSC_CMD - Command Register ....................148
9. LDMA - Linked DMA Controller........................149
9.1 Introduction ..............................149
9.1.1 Features .............................150
9.2 Block Diagram .............................151
9.3 Functional Description ..........................152
9.3.1 Channel Descriptor ..........................152
9.3.2 Channel Configuration .........................157
9.3.3 Channel Select Configuration ......................157
9.3.4 Starting a Transfer ..........................157
9.3.5 Managing Transfer Errors ........................158
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9.3.6 Arbitration .............................158
9.3.7 Channel Descriptor Data Structure .....................160
9.3.8 Interaction With the EMU ........................164
9.3.9 Interrupts .............................164
9.3.10 Debugging ............................164
9.4 Examples ...............................164
9.4.1 Single Direct Register DMA Transfer ....................165
9.4.2 Descriptor Linked List .........................166
9.4.3 Single Descriptor Looped Transfer .....................168
9.4.4 Descriptor List With Looping .......................169
9.4.5 Simple Inter-Channel Synchronization....................170
9.4.6 2D Copy..............................172
9.4.7 Ping-Pong .............................174
9.4.8 Scatter-Gather ...........................175
9.5 Register Map .............................176
9.6 Register Description ...........................177
9.6.1 LDMA_CTRL - DMA Control Register ...................177
9.6.2 LDMA_STATUS - DMA Status Register ...................178
9.6.3 LDMA_SYNC - DMA Synchronization Trigger Register (Single-Cycle RMW) ......179
9.6.4 LDMA_CHEN - DMA Channel Enable Register (Single-Cycle RMW) .........179
9.6.5 LDMA_CHBUSY - DMA Channel Busy Register ................180
9.6.6 LDMA_CHDONE - DMA Channel Linking Done Register (Single-Cycle RMW) ......180
9.6.7 LDMA_DBGHALT - DMA Channel Debug Halt Register .............181
9.6.8 LDMA_SWREQ - DMA Channel Software Transfer Request Register ........181
9.6.9 LDMA_REQDIS - DMA Channel Request Disable Register ............182
9.6.10 LDMA_REQPEND - DMA Channel Requests Pending Register ..........182
9.6.11 LDMA_LINKLOAD - DMA Channel Link Load Register .............183
9.6.12 LDMA_REQCLEAR - DMA Channel Request Clear Register ...........183
9.6.13 LDMA_IF - Interrupt Flag Register ....................184
9.6.14 LDMA_IFS - Interrupt Flag Set Register ..................184
9.6.15 LDMA_IFC - Interrupt Flag Clear Register .................185
9.6.16 LDMA_IEN - Interrupt Enable Register ..................185
9.6.17 LDMA_CHx_REQSEL - Channel Peripheral Request Select Register ........186
9.6.18 LDMA_CHx_CFG - Channel Configuration Register ..............188
9.6.19 LDMA_CHx_LOOP - Channel Loop Counter Register .............189
9.6.20 LDMA_CHx_CTRL - Channel Descriptor Control Word Register ..........190
9.6.21 LDMA_CHx_SRC - Channel Descriptor Source Data Address Register .......193
9.6.22 LDMA_CHx_DST - Channel Descriptor Destination Data Address Register ......193
9.6.23 LDMA_CHx_LINK - Channel Descriptor Link Structure Address Register .......194
10. RMU - Reset Management Unit .......................195
10.1 Introduction..............................195
10.2 Features ..............................195
10.3 Functional Description ..........................196
10.3.1 Reset Levels ............................197
10.3.2 RMU_RSTCAUSE Register .......................198
10.3.3 Power-On Reset (POR) ........................199
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10.3.4 Brown-Out Detector (BOD) .......................199
10.3.5 RESETn Pin Reset..........................200
10.3.6 Watchdog Reset ..........................200
10.3.7 Lockup Reset ...........................200
10.3.8 System Reset Request ........................200
10.3.9 Reset State ............................200
10.3.10 Register Reset Signals ........................200
10.4 Register Map .............................202
10.5 Register Description ...........................203
10.5.1 RMU_CTRL - Control Register .....................203
10.5.2 RMU_RSTCAUSE - Reset Cause Register .................205
10.5.3 RMU_CMD - Command Register ....................206
10.5.4 RMU_RST - Reset Control Register ...................206
10.5.5 RMU_LOCK - Configuration Lock Register .................207
11. EMU - Energy Management Unit .......................208
11.1 Introduction..............................208
11.2 Features ..............................208
11.3 Functional Description ..........................209
11.3.1 Energy Modes ...........................210
11.3.2 Entering Low Energy Modes ......................214
11.3.3 Exiting a Low Energy Mode ......................216
11.3.4 Power Configurations .........................217
11.3.5 DC-to-DC Interface .........................221
11.3.6 Analog Peripheral Power Selection ....................223
11.3.7 IOVDD Connection..........................223
11.3.8 Brown Out Detector (BOD) .......................223
11.3.9 Voltage Monitor (VMON) ........................225
11.3.10 Powering Off SRAM Blocks ......................226
11.3.11 Temperature Sensor .........................226
11.3.12 Registers latched in EM4 .......................227
11.3.13 Register Resets ..........................227
11.4 Register Map .............................228
11.5 Register Description ...........................229
11.5.1 EMU_CTRL - Control Register .....................229
11.5.2 EMU_STATUS - Status Register ....................230
11.5.3 EMU_LOCK - Configuration Lock Register .................231
11.5.4 EMU_RAM0CTRL - Memory Control Register ................232
11.5.5 EMU_CMD - Command Register ....................233
11.5.6 EMU_EM4CTRL - EM4 Control Register ..................234
11.5.7 EMU_TEMPLIMITS - Temperature Limits for Interrupt Generation .........235
11.5.8 EMU_TEMP - Value of Last Temperature Measurement .............235
11.5.9 EMU_IF - Interrupt Flag Register ....................236
11.5.10 EMU_IFS - Interrupt Flag Set Register ..................238
11.5.11 EMU_IFC - Interrupt Flag Clear Register .................240
11.5.12 EMU_IEN - Interrupt Enable Register ..................242
11.5.13 EMU_PWRLOCK - Regulator and Supply Lock Register ............244
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11.5.14 EMU_PWRCFG - Power Configuration Register ...............245
11.5.15 EMU_PWRCTRL - Power Control Register .................245
11.5.16 EMU_DCDCCTRL - DCDC Control ...................246
11.5.17 EMU_DCDCMISCCTRL - DCDC Miscellaneous Control Register .........247
11.5.18 EMU_DCDCZDETCTRL - DCDC Power Train NFET Zero Current Detector Control
Register .............................248
11.5.19 EMU_DCDCCLIMCTRL - DCDC Power Train PFET Current Limiter Control Register ..249
11.5.20 EMU_DCDCLNCOMPCTRL - DCDC Low Noise Compensator Control Register ....250
11.5.21 EMU_DCDCLNVCTRL - DCDC Low Noise Voltage Register ...........251
11.5.22 EMU_DCDCTIMING - DCDC Controller Timing Value Register ..........252
11.5.23 EMU_DCDCLPVCTRL - DCDC Low Power Voltage Register ..........253
11.5.24 EMU_DCDCLPCTRL - DCDC Low Power Control Register ...........254
11.5.25 EMU_DCDCLNFREQCTRL - DCDC Low Noise Controller Frequency Control .....255
11.5.26 EMU_DCDCSYNC - DCDC Read Status Register ..............255
11.5.27 EMU_VMONAVDDCTRL - VMON AVDD Channel Control ...........256
11.5.28 EMU_VMONALTAVDDCTRL - Alternate VMON AVDD Channel Control .......257
11.5.29 EMU_VMONDVDDCTRL - VMON DVDD Channel Control ...........258
11.5.30 EMU_VMONIO0CTRL - VMON IOVDD0 Channel Control ............259
11.5.31 EMU_VMONPAVDDCTRL - VMON PAVDD Channel Control ..........260
11.5.32 EMU_BIASCONF - Configurations Related to the Bias .............261
11.5.33 EMU_TESTLOCK - Test Lock Register ..................262
11.5.34 EMU_BIASTESTCTRL - Test Control Register for Regulator and BIAS .......263
12. CMU - Clock Management Unit .......................264
12.1 Introduction..............................264
12.2 Features ..............................264
12.3 Functional Description ..........................265
12.3.1 System Clocks ...........................266
12.3.2 Oscillators ............................268
12.3.3 Configuration for Operating Frequencies ..................286
12.3.4 Energy Modes ...........................287
12.3.5 Clock Output on a Pin .........................288
12.3.6 Clock Output on PRS .........................288
12.3.7 Error Handling ...........................288
12.3.8 Interrupts .............................288
12.3.9 Wake-up .............................288
12.3.10 Protection ............................289
12.4 Register Map .............................290
12.5 Register Description ...........................292
12.5.1 CMU_CTRL - CMU Control Register ...................292
12.5.2 CMU_HFRCOCTRL - HFRCO Control Register ...............294
12.5.3 CMU_AUXHFRCOCTRL - AUXHFRCO Control Register ............296
12.5.4 CMU_LFRCOCTRL - LFRCO Control Register ................297
12.5.5 CMU_HFXOCTRL - HFXO Control Register .................298
12.5.6 CMU_HFXOCTRL1 - HFXO Control 1 ...................300
12.5.7 CMU_HFXOSTARTUPCTRL - HFXO Startup Control .............301
12.5.8 CMU_HFXOSTEADYSTATECTRL - HFXO Steady State Control .........302
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12.5.9 CMU_HFXOTIMEOUTCTRL - HFXO Timeout Control .............303
12.5.10 CMU_LFXOCTRL - LFXO Control Register ................306
12.5.11 CMU_ULFRCOCTRL - ULFRCO Control Register ..............308
12.5.12 CMU_CALCTRL - Calibration Control Register ...............309
12.5.13 CMU_CALCNT - Calibration Counter Register ...............311
12.5.14 CMU_OSCENCMD - Oscillator Enable/Disable Command Register ........312
12.5.15 CMU_CMD - Command Register ....................313
12.5.16 CMU_DBGCLKSEL - Debug Trace Clock Select ...............314
12.5.17 CMU_HFCLKSEL - High Frequency Clock Select Command Register .......314
12.5.18 CMU_LFACLKSEL - Low Frequency A Clock Select Register ..........315
12.5.19 CMU_LFBCLKSEL - Low Frequency B Clock Select Register ..........315
12.5.20 CMU_LFECLKSEL - Low Frequency E Clock Select Register ..........316
12.5.21 CMU_STATUS - Status Register ....................317
12.5.22 CMU_HFCLKSTATUS - HFCLK Status Register ...............318
12.5.23 CMU_HFXOTRIMSTATUS - HFXO Trim Status ...............319
12.5.24 CMU_IF - Interrupt Flag Register ....................320
12.5.25 CMU_IFS - Interrupt Flag Set Register ..................322
12.5.26 CMU_IFC - Interrupt Flag Clear Register .................324
12.5.27 CMU_IEN - Interrupt Enable Register ..................326
12.5.28 CMU_HFBUSCLKEN0 - High Frequency Bus Clock Enable Register 0 .......327
12.5.29 CMU_HFPERCLKEN0 - High Frequency Peripheral Clock Enable Register 0 .....328
12.5.30 CMU_LFACLKEN0 - Low Frequency a Clock Enable Register 0 (Async Reg) .....329
12.5.31 CMU_LFBCLKEN0 - Low Frequency B Clock Enable Register 0 (Async Reg) .....329
12.5.32 CMU_LFECLKEN0 - Low Frequency E Clock Enable Register 0 (Async Reg) .....330
12.5.33 CMU_HFPRESC - High Frequency Clock Prescaler Register ..........331
12.5.34 CMU_HFCOREPRESC - High Frequency Core Clock Prescaler Register ......332
12.5.35 CMU_HFPERPRESC - High Frequency Peripheral Clock Prescaler Register .....332
12.5.36 CMU_HFRADIOPRESC - High Frequency Radio Peripheral Clock Prescaler Register ..333
12.5.37 CMU_HFEXPPRESC - High Frequency Export Clock Prescaler Register ......333
12.5.38 CMU_LFAPRESC0 - Low Frequency a Prescaler Register 0 (Async Reg) ......334
12.5.39 CMU_LFBPRESC0 - Low Frequency B Prescaler Register 0 (Async Reg) ......335
12.5.40 CMU_LFEPRESC0 - Low Frequency E Prescaler Register 0 (Async Reg) ......335
12.5.41 CMU_SYNCBUSY - Synchronization Busy Register ..............336
12.5.42 CMU_FREEZE - Freeze Register ....................339
12.5.43 CMU_PCNTCTRL - PCNT Control Register ................340
12.5.44 CMU_ADCCTRL - ADC Control Register .................341
12.5.45 CMU_ROUTEPEN - I/O Routing Pin Enable Register .............342
12.5.46 CMU_ROUTELOC0 - I/O Routing Location Register .............343
12.5.47 CMU_LOCK - Configuration Lock Register .................344
13. RTCC - Real Time Counter and Calendar ...................345
13.1 Introduction..............................345
13.2 Features ..............................345
13.3 Functional Description ..........................346
13.3.1 Counter .............................347
13.3.2 Capture/Compare Channels ......................351
13.3.3 Interrupts and PRS Output .......................353
13.3.4 Energy Mode Availability ........................354
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13.3.5 Register Lock ...........................354
13.3.6 Oscillator Failure Detection .......................354
13.3.7 Retention Registers .........................354
13.3.8 Frame Controller Interface .......................354
13.3.9 Debug Session ...........................354
13.4 Register Map .............................355
13.5 Register Description ...........................356
13.5.1 RTCC_CTRL - Control Register (Async Reg) ................356
13.5.2 RTCC_PRECNT - Pre-Counter Value Register (Async Reg) ...........358
13.5.3 RTCC_CNT - Counter Value Register (Async Reg) ..............358
13.5.4 RTCC_COMBCNT - Combined Pre-Counter and Counter Value Register .......359
13.5.5 RTCC_TIME - Time of Day Register (Async Reg) ...............360
13.5.6 RTCC_DATE - Date Register (Async Reg) .................361
13.5.7 RTCC_IF - RTCC Interrupt Flags ....................362
13.5.8 RTCC_IFS - Interrupt Flag Set Register ..................363
13.5.9 RTCC_IFC - Interrupt Flag Clear Register .................364
13.5.10 RTCC_IEN - Interrupt Enable Register ..................365
13.5.11 RTCC_STATUS - Status Register ....................366
13.5.12 RTCC_CMD - Command Register (Async Reg) ...............366
13.5.13 RTCC_SYNCBUSY - Synchronization Busy Register .............367
13.5.14 RTCC_POWERDOWN - Retention RAM Power-down Register (Async Reg) .....367
13.5.15 RTCC_LOCK - Configuration Lock Register (Async Reg) ............368
13.5.16 RTCC_EM4WUEN - Wake Up Enable ..................368
13.5.17 RTCC_CCx_CTRL - CC Channel Control Register (Async Reg) .........369
13.5.18 RTCC_CCx_CCV - Capture/Compare Value Register (Async Reg) ........371
13.5.19 RTCC_CCx_TIME - Capture/Compare Time Register (Async Reg) ........372
13.5.20 RTCC_CCx_DATE - Capture/Compare Date Register (Async Reg) ........373
13.5.21 RTCC_RETx_REG - Retention Register .................373
14. WDOG - Watchdog Timer .........................374
14.1 Introduction..............................374
14.2 Features ..............................374
14.3 Functional Description ..........................374
14.3.1 Clock Source ...........................375
14.3.2 Debug Functionality .........................375
14.3.3 Energy Mode Handling ........................375
14.3.4 Register Access...........................375
14.3.5 Warning Interrupt ..........................375
14.3.6 Window Interrupt ..........................376
14.3.7 PRS as Watchdog Clear ........................377
14.3.8 PRS Rising Edge Monitoring ......................377
14.4 Register Map .............................378
14.5 Register Description ...........................379
14.5.1 WDOG_CTRL - Control Register (Async Reg) ................379
14.5.2 WDOG_CMD - Command Register (Async Reg) ...............382
14.5.3 WDOG_SYNCBUSY - Synchronization Busy Register .............383
14.5.4 WDOGn_PCHx_PRSCTRL - PRS Control Register (Async Reg) ..........384
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14.5.5 WDOG_IF - Watchdog Interrupt Flags ...................385
14.5.6 WDOG_IFS - Interrupt Flag Set Register ..................386
14.5.7 WDOG_IFC - Interrupt Flag Clear Register .................387
14.5.8 WDOG_IEN - Interrupt Enable Register ..................388
15. PRS - Peripheral Reflex System .......................389
15.1 Introduction..............................389
15.2 Features ..............................389
15.3 Functional Description ..........................390
15.3.1 Channel Functions ..........................390
15.3.2 Producers .............................391
15.3.3 Consumers ............................392
15.3.4 Event on PRS ...........................393
15.3.5 DMA Request on PRS ........................393
15.3.6 Example .............................393
15.4 Register Map .............................394
15.5 Register Description ...........................395
15.5.1 PRS_SWPULSE - Software Pulse Register .................395
15.5.2 PRS_SWLEVEL - Software Level Register .................396
15.5.3 PRS_ROUTEPEN - I/O Routing Pin Enable Register ..............397
15.5.4 PRS_ROUTELOC0 - I/O Routing Location Register ..............398
15.5.5 PRS_ROUTELOC1 - I/O Routing Location Register ..............401
15.5.6 PRS_ROUTELOC2 - I/O Routing Location Register ..............403
15.5.7 PRS_CTRL - Control Register .....................405
15.5.8 PRS_DMAREQ0 - DMA Request 0 Register .................406
15.5.9 PRS_DMAREQ1 - DMA Request 1 Register .................407
15.5.10 PRS_PEEK - PRS Channel Values ...................408
15.5.11 PRS_CHx_CTRL - Channel Control Register ................409
16. PCNT - Pulse Counter ..........................414
16.1 Introduction..............................414
16.2 Features ..............................414
16.3 Functional Description ..........................415
16.3.1 Pulse Counter Modes .........................415
16.3.2 Hysteresis ............................422
16.3.3 Auxiliary Counter ..........................423
16.3.4 Triggered Compare and Clear ......................424
16.3.5 Register Access...........................425
16.3.6 Clock Sources ...........................425
16.3.7 Input Filter ............................425
16.3.8 Edge Polarity ...........................425
16.3.9 PRS and PCNTn_S0IN,PCNTn_S1IN Inputs .................426
16.3.10 Interrupts ............................426
16.3.11 Cascading Pulse Counters ......................428
16.4 Register Map .............................429
16.5 Register Description ...........................430
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16.5.1 PCNTn_CTRL - Control Register (Async Reg) ................430
16.5.2 PCNTn_CMD - Command Register (Async Reg) ...............434
16.5.3 PCNTn_STATUS - Status Register ....................434
16.5.4 PCNTn_CNT - Counter Value Register ..................435
16.5.5 PCNTn_TOP - Top Value Register ....................435
16.5.6 PCNTn_TOPB - Top Value Buffer Register (Async Reg) ............436
16.5.7 PCNTn_IF - Interrupt Flag Register ....................436
16.5.8 PCNTn_IFS - Interrupt Flag Set Register ..................437
16.5.9 PCNTn_IFC - Interrupt Flag Clear Register .................438
16.5.10 PCNTn_IEN - Interrupt Enable Register ..................439
16.5.11 PCNTn_ROUTELOC0 - I/O Routing Location Register .............440
16.5.12 PCNTn_FREEZE - Freeze Register ...................442
16.5.13 PCNTn_SYNCBUSY - Synchronization Busy Register .............443
16.5.14 PCNTn_AUXCNT - Auxiliary Counter Value Register .............443
16.5.15 PCNTn_INPUT - PCNT Input Register ..................444
16.5.16 PCNTn_OVSCFG - Oversampling Config Register (Async Reg) .........445
17. I2C - Inter-Integrated Circuit Interface .....................446
17.1 Introduction..............................446
17.2 Features ..............................446
17.3 Functional Description ..........................447
17.3.1 I2C-Bus Overview ..........................448
17.3.2 Enable and Reset ..........................452
17.3.3 Safely Disabling and Changing Slave Configuration...............452
17.3.4 Clock Generation ..........................452
17.3.5 Arbitration .............................453
17.3.6 Buffers ..............................453
17.3.7 Master Operation ..........................455
17.3.8 Bus States ............................463
17.3.9 Slave Operation ..........................463
17.3.10 Transfer Automation .........................467
17.3.11 Using 10-bit Addresses ........................468
17.3.12 Error Handling ...........................468
17.3.13 DMA Support ...........................470
17.3.14 Interrupts ............................470
17.3.15 Wake-up .............................470
17.4 Register Map .............................471
17.5 Register Description ...........................472
17.5.1 I2Cn_CTRL - Control Register .....................472
17.5.2 I2Cn_CMD - Command Register ....................475
17.5.3 I2Cn_STATE - State Register ......................476
17.5.4 I2Cn_STATUS - Status Register .....................477
17.5.5 I2Cn_CLKDIV - Clock Division Register ..................478
17.5.6 I2Cn_SADDR - Slave Address Register ..................478
17.5.7 I2Cn_SADDRMASK - Slave Address Mask Register ..............479
17.5.8 I2Cn_RXDATA - Receive Buffer Data Register (Actionable Reads) .........479
17.5.9 I2Cn_RXDOUBLE - Receive Buffer Double Data Register (Actionable Reads) .....480
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17.5.10 I2Cn_RXDATAP - Receive Buffer Data Peek Register .............480
17.5.11 I2Cn_RXDOUBLEP - Receive Buffer Double Data Peek Register .........481
17.5.12 I2Cn_TXDATA - Transmit Buffer Data Register ...............481
17.5.13 I2Cn_TXDOUBLE - Transmit Buffer Double Data Register ...........482
17.5.14 I2Cn_IF - Interrupt Flag Register ....................483
17.5.15 I2Cn_IFS - Interrupt Flag Set Register ..................485
17.5.16 I2Cn_IFC - Interrupt Flag Clear Register .................487
17.5.17 I2Cn_IEN - Interrupt Enable Register ...................489
17.5.18 I2Cn_ROUTEPEN - I/O Routing Pin Enable Register .............490
17.5.19 I2Cn_ROUTELOC0 - I/O Routing Location Register ..............491
18. USART - Universal Synchronous Asynchronous Receiver/Transmitter ........494
18.1 Introduction..............................494
18.2 Features ..............................495
18.3 Functional Description ..........................496
18.3.1 Modes of Operation .........................497
18.3.2 Asynchronous Operation ........................497
18.3.3 Synchronous Operation ........................514
18.3.4 Hardware Flow Control ........................520
18.3.5 Debug Halt ............................520
18.3.6 PRS-triggered Transmissions ......................520
18.3.7 PRS RX Input ...........................520
18.3.8 PRS CLK Input ...........................521
18.3.9 DMA Support ...........................521
18.3.10 Timer ..............................522
18.3.11 Interrupts ............................527
18.3.12 IrDA Modulator/ Demodulator ......................528
18.4 Register Map .............................529
18.5 Register Description ...........................530
18.5.1 USARTn_CTRL - Control Register ....................530
18.5.2 USARTn_FRAME - USART Frame Format Register ..............535
18.5.3 USARTn_TRIGCTRL - USART Trigger Control Register ............537
18.5.4 USARTn_CMD - Command Register ...................539
18.5.5 USARTn_STATUS - USART Status Register ................540
18.5.6 USARTn_CLKDIV - Clock Control Register .................541
18.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register (Actionable Reads) .....542
18.5.8 USARTn_RXDATA - RX Buffer Data Register (Actionable Reads) .........542
18.5.9 USARTn_RXDOUBLEX - RX Buffer Double Data Extended Register (Actionable Reads) .543
18.5.10 USARTn_RXDOUBLE - RX FIFO Double Data Register (Actionable Reads) .....544
18.5.11 USARTn_RXDATAXP - RX Buffer Data Extended Peek Register .........544
18.5.12 USARTn_RXDOUBLEXP - RX Buffer Double Data Extended Peek Register .....545
18.5.13 USARTn_TXDATAX - TX Buffer Data Extended Register ............546
18.5.14 USARTn_TXDATA - TX Buffer Data Register ................547
18.5.15 USARTn_TXDOUBLEX - TX Buffer Double Data Extended Register ........548
18.5.16 USARTn_TXDOUBLE - TX Buffer Double Data Register ............549
18.5.17 USARTn_IF - Interrupt Flag Register ...................550
18.5.18 USARTn_IFS - Interrupt Flag Set Register .................552
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18.5.19 USARTn_IFC - Interrupt Flag Clear Register ................554
18.5.20 USARTn_IEN - Interrupt Enable Register .................556
18.5.21 USARTn_IRCTRL - IrDA Control Register .................558
18.5.22 USARTn_INPUT - USART Input Register .................560
18.5.23 USARTn_I2SCTRL - I2S Control Register .................562
18.5.24 USARTn_TIMING - Timing Register ...................564
18.5.25 USARTn_CTRLX - Control Register Extended ...............566
18.5.26 USARTn_TIMECMP0 - Used to Generate Interrupts and Various Delays ......567
18.5.27 USARTn_TIMECMP1 - Used to Generate Interrupts and Various Delays ......569
18.5.28 USARTn_TIMECMP2 - Used to Generate Interrupts and Various Delays ......571
18.5.29 USARTn_ROUTEPEN - I/O Routing Pin Enable Register ............573
18.5.30 USARTn_ROUTELOC0 - I/O Routing Location Register ............575
18.5.31 USARTn_ROUTELOC1 - I/O Routing Location Register ............580
19. LEUART - Low Energy Universal Asynchronous Receiver/Transmitter ........583
19.1 Introduction..............................583
19.2 Features ..............................584
19.3 Functional Description ..........................585
19.3.1 Frame Format ...........................586
19.3.2 Clock Source ...........................586
19.3.3 Clock Generation ..........................587
19.3.4 Data Transmission ..........................587
19.3.5 Data Reception ...........................589
19.3.6 Loopback .............................592
19.3.7 Half Duplex Communication ......................592
19.3.8 Transmission Delay .........................593
19.3.9 PRS RX Input ...........................593
19.3.10 DMA Support ...........................594
19.3.11 Pulse Generator/ Pulse Extender ....................594
19.3.12 Register Access ..........................595
19.4 Register Map .............................595
19.5 Register Description ...........................596
19.5.1 LEUARTn_CTRL - Control Register (Async Reg) ...............596
19.5.2 LEUARTn_CMD - Command Register (Async Reg) ..............599
19.5.3 LEUARTn_STATUS - Status Register ...................600
19.5.4 LEUARTn_CLKDIV - Clock Control Register (Async Reg) ............601
19.5.5 LEUARTn_STARTFRAME - Start Frame Register (Async Reg) ..........601
19.5.6 LEUARTn_SIGFRAME - Signal Frame Register (Async Reg) ...........602
19.5.7 LEUARTn_RXDATAX - Receive Buffer Data Extended Register (Actionable Reads) ...602
19.5.8 LEUARTn_RXDATA - Receive Buffer Data Register (Actionable Reads) .......603
19.5.9 LEUARTn_RXDATAXP - Receive Buffer Data Extended Peek Register .......603
19.5.10 LEUARTn_TXDATAX - Transmit Buffer Data Extended Register (Async Reg) .....604
19.5.11 LEUARTn_TXDATA - Transmit Buffer Data Register (Async Reg) .........605
19.5.12 LEUARTn_IF - Interrupt Flag Register ..................606
19.5.13 LEUARTn_IFS - Interrupt Flag Set Register ................607
19.5.14 LEUARTn_IFC - Interrupt Flag Clear Register ................608
19.5.15 LEUARTn_IEN - Interrupt Enable Register .................609
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19.5.16 LEUARTn_PULSECTRL - Pulse Control Register (Async Reg) ..........610
19.5.17 LEUARTn_FREEZE - Freeze Register ..................611
19.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register ............612
19.5.19 LEUARTn_ROUTEPEN - I/O Routing Pin Enable Register ...........613
19.5.20 LEUARTn_ROUTELOC0 - I/O Routing Location Register ............614
19.5.21 LEUARTn_INPUT - LEUART Input Register ................617
20. TIMER - Timer/Counter ..........................618
20.1 Introduction..............................618
20.2 Features ..............................619
20.3 Functional Description ..........................620
20.3.1 Counter Modes ...........................621
20.3.2 Compare/Capture Channels ......................627
20.3.3 Dead-Time Insertion Unit .......................637
20.3.4 Debug Mode ............................641
20.3.5 Interrupts, DMA and PRS Output .....................641
20.3.6 GPIO Input/Output ..........................641
20.4 Register Map .............................642
20.5 Register Description ...........................643
20.5.1 TIMERn_CTRL - Control Register ....................643
20.5.2 TIMERn_CMD - Command Register ...................645
20.5.3 TIMERn_STATUS - Status Register ...................646
20.5.4 TIMERn_IF - Interrupt Flag Register ...................649
20.5.5 TIMERn_IFS - Interrupt Flag Set Register .................650
20.5.6 TIMERn_IFC - Interrupt Flag Clear Register .................651
20.5.7 TIMERn_IEN - Interrupt Enable Register ..................653
20.5.8 TIMERn_TOP - Counter Top Value Register ................654
20.5.9 TIMERn_TOPB - Counter Top Value Buffer Register ..............654
20.5.10 TIMERn_CNT - Counter Value Register ..................655
20.5.11 TIMERn_LOCK - TIMER Configuration Lock Register .............656
20.5.12 TIMERn_ROUTEPEN - I/O Routing Pin Enable Register ............657
20.5.13 TIMERn_ROUTELOC0 - I/O Routing Location Register ............658
20.5.14 TIMERn_ROUTELOC2 - I/O Routing Location Register ............663
20.5.15 TIMERn_CCx_CTRL - CC Channel Control Register .............667
20.5.16 TIMERn_CCx_CCV - CC Channel Value Register (Actionable Reads) .......670
20.5.17 TIMERn_CCx_CCVP - CC Channel Value Peek Register ............670
20.5.18 TIMERn_CCx_CCVB - CC Channel Buffer Register ..............671
20.5.19 TIMERn_DTCTRL - DTI Control Register .................672
20.5.20 TIMERn_DTTIME - DTI Time Control Register ...............674
20.5.21 TIMERn_DTFC - DTI Fault Configuration Register ..............676
20.5.22 TIMERn_DTOGEN - DTI Output Generation Enable Register ..........678
20.5.23 TIMERn_DTFAULT - DTI Fault Register .................679
20.5.24 TIMERn_DTFAULTC - DTI Fault Clear Register ...............680
20.5.25 TIMERn_DTLOCK - DTI Configuration Lock Register .............681
21. LETIMER - Low Energy Timer ........................682
21.1 Introduction..............................682
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21.2 Features ..............................682
21.3 Functional Description ..........................683
21.3.1 Timer ..............................683
21.3.2 Compare Registers .........................683
21.3.3 Top Value .............................684
21.3.4 Underflow Output Action ........................690
21.3.5 PRS Output ............................692
21.3.6 Examples .............................692
21.3.7 Register Access...........................695
21.4 Register Map .............................696
21.5 Register Description ...........................697
21.5.1 LETIMERn_CTRL - Control Register (Async Reg) ...............697
21.5.2 LETIMERn_CMD - Command Register (Async Reg) ..............699
21.5.3 LETIMERn_STATUS - Status Register ..................699
21.5.4 LETIMERn_CNT - Counter Value Register .................700
21.5.5 LETIMERn_COMP0 - Compare Value Register 0 (Async Reg) ..........700
21.5.6 LETIMERn_COMP1 - Compare Value Register 1 (Async Reg) ..........701
21.5.7 LETIMERn_REP0 - Repeat Counter Register 0 (Async Reg) ...........701
21.5.8 LETIMERn_REP1 - Repeat Counter Register 1 (Async Reg) ...........702
21.5.9 LETIMERn_IF - Interrupt Flag Register ..................702
21.5.10 LETIMERn_IFS - Interrupt Flag Set Register ................703
21.5.11 LETIMERn_IFC - Interrupt Flag Clear Register ...............704
21.5.12 LETIMERn_IEN - Interrupt Enable Register ................705
21.5.13 LETIMERn_SYNCBUSY - Synchronization Busy Register ...........705
21.5.14 LETIMERn_ROUTEPEN - I/O Routing Pin Enable Register ...........706
21.5.15 LETIMERn_ROUTELOC0 - I/O Routing Location Register ...........707
21.5.16 LETIMERn_PRSSEL - PRS Input Select Register ..............710
22. CRYOTIMER - Ultra Low Energy Timer/Counter .................713
22.1 Introduction..............................713
22.2 Features ..............................713
22.3 Functional Description ..........................713
22.3.1 Block Diagram ...........................714
22.3.2 Operation .............................715
22.3.3 Debug Mode ............................715
22.3.4 Energy Mode Availability ........................715
22.4 Register Map .............................716
22.5 Register Description ...........................717
22.5.1 CRYOTIMER_CTRL - Control Register ..................717
22.5.2 CRYOTIMER_PERIODSEL - Interrupt Duration ...............718
22.5.3 CRYOTIMER_CNT - Counter Value ...................719
22.5.4 CRYOTIMER_EM4WUEN - Wake Up Enable ................719
22.5.5 CRYOTIMER_IF - Interrupt Flag Register .................720
22.5.6 CRYOTIMER_IFS - Interrupt Flag Set Register ................720
22.5.7 CRYOTIMER_IFC - Interrupt Flag Clear Register ...............721
22.5.8 CRYOTIMER_IEN - Interrupt Enable Register ................721
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23. ACMP - Analog Comparator ........................722
23.1 Introduction .............................722
23.2 Features ..............................722
23.3 Functional Description ..........................723
23.3.1 Power Supply ...........................723
23.3.2 Warm-up Time ...........................724
23.3.3 Response Time ..........................724
23.3.4 Hysteresis ............................725
23.3.5 Input Pin Considerations ........................726
23.3.6 Input Selection ...........................726
23.3.7 Capacitive Sense Mode .......................727
23.3.8 Interrupts and PRS Output .......................729
23.3.9 Output to GPIO ..........................729
23.3.10 APORT Conflicts .........................729
23.3.11 Supply Voltage Monitoring ......................729
23.4 Register Map .............................730
23.5 Register Description ...........................731
23.5.1 ACMPn_CTRL - Control Register ....................731
23.5.2 ACMPn_INPUTSEL - Input Selection Register ................734
23.5.3 ACMPn_STATUS - Status Register ....................739
23.5.4 ACMPn_IF - Interrupt Flag Register ...................739
23.5.5 ACMPn_IFS - Interrupt Flag Set Register ..................740
23.5.6 ACMPn_IFC - Interrupt Flag Clear Register .................741
23.5.7 ACMPn_IEN - Interrupt Enable Register ..................742
23.5.8 ACMPn_APORTREQ - APORT Request Status Register ............743
23.5.9 ACMPn_APORTCONFLICT - APORT Conflict Status Register ..........744
23.5.10 ACMPn_HYSTERESIS0 - Hysteresis 0 Register ...............746
23.5.11 ACMPn_HYSTERESIS1 - Hysteresis 1 Register ...............747
23.5.12 ACMPn_ROUTEPEN - I/O Routing Pine Enable Register ............748
23.5.13 ACMPn_ROUTELOC0 - I/O Routing Location Register .............749
24. ADC - Analog to Digital Converter ......................751
24.1 Introduction..............................751
24.2 Features ..............................752
24.3 Functional Description ..........................753
24.3.1 Clock Selection ...........................754
24.3.2 Conversions ............................754
24.3.3 ADC Modes ............................755
24.3.4 Warm-up Time ...........................756
24.3.5 Power Supply ...........................757
24.3.6 Input Pin Considerations ........................757
24.3.7 Input Selection ...........................758
24.3.8 Reference Selection and Input Range Definition ................762
24.3.9 Programming of Bias Current ......................765
24.3.10 Feature Set ............................766
24.3.11 Interrupts, PRS Output ........................771
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24.3.12 DMA Request ...........................771
24.3.13 Calibration ............................771
24.3.14 EM2 DeepSleep or EM3 Stop Operation ..................772
24.3.15 ASYNC ADC_CLK Usage Restrictions and Benefits ..............773
24.3.16 Window Compare Function ......................773
24.3.17 ADC Programming Model .......................774
24.4 Register Map .............................775
24.5 Register Description ...........................776
24.5.1 ADCn_CTRL - Control Register .....................776
24.5.2 ADCn_CMD - Command Register ....................779
24.5.3 ADCn_STATUS - Status Register ....................780
24.5.4 ADCn_SINGLECTRL - Single Channel Control Register .............781
24.5.5 ADCn_SINGLECTRLX - Single Channel Control Register Continued ........786
24.5.6 ADCn_SCANCTRL - Scan Control Register .................789
24.5.7 ADCn_SCANCTRLX - Scan Control Register Continued ............792
24.5.8 ADCn_SCANMASK - Scan Sequence Input Mask Register ............795
24.5.9 ADCn_SCANINPUTSEL - Input Selection Register for Scan Mode .........797
24.5.10 ADCn_SCANNEGSEL - Negative Input Select Register for Scan .........800
24.5.11 ADCn_CMPTHR - Compare Threshold Register ...............802
24.5.12 ADCn_BIASPROG - Bias Programming Register for Various Analog Blocks Used in ADC
Operation .............................803
24.5.13 ADCn_CAL - Calibration Register ....................804
24.5.14 ADCn_IF - Interrupt Flag Register ....................806
24.5.15 ADCn_IFS - Interrupt Flag Set Register ..................807
24.5.16 ADCn_IFC - Interrupt Flag Clear Register .................808
24.5.17 ADCn_IEN - Interrupt Enable Register ..................809
24.5.18 ADCn_SINGLEDATA - Single Conversion Result Data (Actionable Reads) ......810
24.5.19 ADCn_SCANDATA - Scan Conversion Result Data (Actionable Reads) .......810
24.5.20 ADCn_SINGLEDATAP - Single Conversion Result Data Peek Register .......811
24.5.21 ADCn_SCANDATAP - Scan Sequence Result Data Peek Register ........811
24.5.22 ADCn_SCANDATAX - Scan Sequence Result Data + Data Source Register (Actionable
Reads) ..............................812
24.5.23 ADCn_SCANDATAXP - Scan Sequence Result Data + Data Source Peek Register ...812
24.5.24 ADCn_APORTREQ - APORT Request Status Register ............813
24.5.25 ADCn_APORTCONFLICT - APORT Conflict Status Register ...........814
24.5.26 ADCn_SINGLEFIFOCOUNT - Single FIFO Count Register ...........815
24.5.27 ADCn_SCANFIFOCOUNT - Scan FIFO Count Register ............815
24.5.28 ADCn_SINGLEFIFOCLEAR - Single FIFO Clear Register ............816
24.5.29 ADCn_SCANFIFOCLEAR - Scan FIFO Clear Register .............816
25. IDAC - Current Digital to Analog Converter ...................817
25.1 Introduction..............................817
25.2 Features ..............................817
25.3 Functional Description ..........................818
25.3.1 Current Programming ........................818
25.3.2 IDAC Enable and Warm-up ......................818
25.3.3 Output Control ...........................818
25.3.4 APORT Configuration .........................819
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25.3.5 Interrupts .............................819
25.3.6 Minimizing Output Transition ......................819
25.3.7 Duty Cycle Configuration........................819
25.3.8 Calibration ............................819
25.3.9 PRS Triggered Charge Injection .....................820
25.4 Register Map .............................820
25.5 Register Description ...........................821
25.5.1 IDAC_CTRL - Control Register .....................821
25.5.2 IDAC_CURPROG - Current Programming Register ..............823
25.5.3 IDAC_DUTYCONFIG - Duty Cycle Configuration Register ............824
25.5.4 IDAC_STATUS - Status Register ....................824
25.5.5 IDAC_IF - Interrupt Flag Register ....................825
25.5.6 IDAC_IFS - Interrupt Flag Set Register ..................825
25.5.7 IDAC_IFC - Interrupt Flag Clear Register ..................826
25.5.8 IDAC_IEN - Interrupt Enable Register ...................826
25.5.9 IDAC_APORTREQ - APORT Request Status Register .............827
25.5.10 IDAC_APORTCONFLICT - APORT Request Status Register ..........827
26. GPCRC - General Purpose Cyclic Redundancy Check ..............828
26.1 Introduction..............................828
26.2 Features ..............................828
26.3 Functional Description ..........................829
26.3.1 Polynomial Specification ........................830
26.3.2 Input and Output Specification ......................830
26.3.3 Initialization ............................830
26.3.4 DMA Usage ............................830
26.3.5 Byte-Level Bit Reversal and Byte Reordering .................831
26.4 Register Map .............................833
26.5 Register Description ...........................834
26.5.1 GPCRC_CTRL - Control Register ....................834
26.5.2 GPCRC_CMD - Command Register ...................835
26.5.3 GPCRC_INIT - CRC Init Value .....................835
26.5.4 GPCRC_POLY - CRC Polynomial Value ..................836
26.5.5 GPCRC_INPUTDATA - Input 32-bit Data Register ...............836
26.5.6 GPCRC_INPUTDATAHWORD - Input 16-bit Data Register ...........837
26.5.7 GPCRC_INPUTDATABYTE - Input 8-bit Data Register .............837
26.5.8 GPCRC_DATA - CRC Data Register ...................838
26.5.9 GPCRC_DATAREV - CRC Data Reverse Register ..............838
26.5.10 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register ..........839
27. CRYPTO - Crypto Accelerator........................840
27.1 Introduction..............................840
27.2 Features ..............................841
27.3 Usage and Programming Interface ......................841
27.4 Functional Description ..........................842
27.4.1 Data and Key Registers ........................843
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27.4.2 Instructions and Execution .......................845
27.4.3 Repeated Sequence .........................850
27.4.4 AES ...............................851
27.4.5 SHA...............................853
27.4.6 ECC ..............................853
27.4.7 GCM and GMAC ..........................854
27.4.8 DMA ..............................854
27.4.9 BUFC Data Transfer .........................856
27.4.10 Debugging ............................857
27.4.11 Example: Cipher Block Chaining (CBC) ..................857
27.5 Register Map .............................860
27.6 Register Description ...........................862
27.6.1 CRYPTO_CTRL - Control Register ....................862
27.6.2 CRYPTO_WAC - Wide Arithmetic Configuration ...............865
27.6.3 CRYPTO_CMD - Command Register ...................867
27.6.4 CRYPTO_STATUS - Status Register ...................872
27.6.5 CRYPTO_DSTATUS - Data Status Register .................873
27.6.6 CRYPTO_CSTATUS - Control Status Register ................874
27.6.7 CRYPTO_KEY - KEY Register Access (No Bit Access) (Actionable Reads) ......875
27.6.8 CRYPTO_KEYBUF - KEY Buffer Register Access (No Bit Access) (Actionable Reads) ..876
27.6.9 CRYPTO_SEQCTRL - Sequence Control .................877
27.6.10 CRYPTO_SEQCTRLB - Sequence Control B ................878
27.6.11 CRYPTO_IF - AES Interrupt Flags ...................879
27.6.12 CRYPTO_IFS - Interrupt Flag Set Register .................880
27.6.13 CRYPTO_IFC - Interrupt Flag Clear Register ................881
27.6.14 CRYPTO_IEN - Interrupt Enable Register .................882
27.6.15 CRYPTO_SEQ0 - Sequence Register 0 ..................882
27.6.16 CRYPTO_SEQ1 - Sequence Register 1 ..................883
27.6.17 CRYPTO_SEQ2 - Sequence Register 2 ..................883
27.6.18 CRYPTO_SEQ3 - Sequence Register 3 ..................884
27.6.19 CRYPTO_SEQ4 - Sequence Register 4 ..................884
27.6.20 CRYPTO_DATA0 - DATA0 Register Access (No Bit Access) (Actionable Reads) ....885
27.6.21 CRYPTO_DATA1 - DATA1 Register Access (No Bit Access) (Actionable Reads) ....885
27.6.22 CRYPTO_DATA2 - DATA2 Register Access (No Bit Access) (Actionable Reads) ....886
27.6.23 CRYPTO_DATA3 - DATA3 Register Access (No Bit Access) (Actionable Reads) ....886
27.6.24 CRYPTO_DATA0XOR - DATA0XOR Register Access (No Bit Access) (Actionable Reads) 887
27.6.25 CRYPTO_DATA0BYTE - DATA0 Register Byte Access (No Bit Access) (Actionable Reads)
.................................887
27.6.26 CRYPTO_DATA1BYTE - DATA1 Register Byte Access (No Bit Access) (Actionable Reads)
.................................888
27.6.27 CRYPTO_DATA0XORBYTE - DATA0 Register Byte XOR Access (No Bit Access)
(Actionable Reads) ..........................888
27.6.28 CRYPTO_DATA0BYTE12 - DATA0 Register Byte 12 Access (No Bit Access) .....889
27.6.29 CRYPTO_DATA0BYTE13 - DATA0 Register Byte 13 Access (No Bit Access) .....889
27.6.30 CRYPTO_DATA0BYTE14 - DATA0 Register Byte 14 Access (No Bit Access) .....890
27.6.31 CRYPTO_DATA0BYTE15 - DATA0 Register Byte 15 Access (No Bit Access) .....890
27.6.32 CRYPTO_DDATA0 - DDATA0 Register Access (No Bit Access) (Actionable Reads) ...891
27.6.33 CRYPTO_DDATA1 - DDATA1 Register Access (No Bit Access) (Actionable Reads) ...891
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