Silicon Laboratories Si8451 User manual

Not Recommended
for NewDesigns
Rev. 1.6 4/18 Copyright © 2018 by Silicon Laboratories Si8450/51/52/55
Si8450/51/52/55
LOW POWER FIVE-CHANNEL DIGITAL ISOLATOR
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrow-
body SOIC package.
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.70–5.5 V
Ultra-low-power (typical)
5 V Operation:
< 1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Operation:
< 1.4 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
Up to 2500 VRMS isolation
60-year life at rated working
voltage
Precise timing (typical)
<10 ns worst case
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
SOIC-16 narrow body
Industrial automation systems
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communications systems
UL 1577 recognized
Up to 2500 VRMS for 1 minute
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
Ordering Information:
See page 28.

Si8450/51/52/55
Rev. 1.6 2
Not Recommended
for NewDesigns
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) . . . . . . . . . . . . . . . . . . . .25
3.2. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . .25
3.3. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Si8450/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Pin Descriptions (Si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Si8450/51/52/55
Rev. 1.6 3
Not Recommended
for NewDesigns
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 °C
Supply Voltage VDD1 2.70 — 5.5 V
VDD2 2.70 — 5.5 V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 °C
Ambient Temperature Under Bias TA–40 — 125 °C
Supply Voltage (Revision A)3VDD1, VDD2 –0.5 — 5.75 V
Supply Voltage (Revision B)3VDD1, VDD2 –0.5 — 6.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive Channel IO——10mA
Lead Solder Temperature (10 s) — — 260 °C
Maximum Isolation Voltage (1 s) — — 3600 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "6. Ordering Guide" on page 28 for more information.

Si8450/51/52/55
4 Rev. 1.6
Not Recommended
for NewDesigns
Table 3. Electrical Characteristics
(VDD1 =5V±10%,V
DD2 =5V±10%,T A= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—85—
Enable Input High Current IENH VENx =V
IH —2.0—µA
Enable Input Low Current IENL VENx =V
IL —2.0—µA
DC Supply Current (All inputs 0 V or at Supply)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
mA
Si8451Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
mA
Si8452Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
—
—4.3 3.5 6.5 5.3 mA
Si8451Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Si8452Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
Rev. 1.6 5
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.3 4.8 6.5 6.7 mA
Si8451Bx
VDD1
VDD2
—
—4.4 5.0 6.2 7.0 mA
Si8452Bx
VDD1
VDD2
—
—4.6 4.8 6.4 6.7 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.6 24 6.9 30 mA
Si8451Bx
VDD1
VDD2
—
—8.6 20.4 10.8 25.5 mA
Si8452Bx
VDD1
VDD2
—
—12.6 16.5 15.8 20.6 mA
Timing Characteristics
Si845xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 3. Electrical Characteristics (Continued)
(VDD1 =5V±10%,V
DD2 =5V±10%,T A= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
6 Rev. 1.6
Not Recommended
for NewDesigns
Si845xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL=15pF
See Figure 2 —3.85.0ns
Output Fall Time tfCL=15pF
See Figure 2 —2.83.7ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Enable to Data Valid3ten1 See Figure 1 — 5.0 8.0 ns
Enable to Data Tri-State3ten2 See Figure 1 — 7.0 9.2 ns
Start-up Time3,4 tSU —1540µs
Table 3. Electrical Characteristics (Continued)
(VDD1 =5V±10%,V
DD2 =5V±10%,T A= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
Rev. 1.6 7
Not Recommended
for NewDesigns
Figure 1. ENABLE Timing Diagram
Figure 2. Propagation Delay Timing
ENABLE
OUTPUTS
ten1 ten2
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V

Si8450/51/52/55
8 Rev. 1.6
Not Recommended
for NewDesigns
Table 4. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—85—
Enable Input High Current IENH VENx = VIH —2.0—µA
Enable Input Low Current IENL VENx = VIL —2.0—µA
DC Supply Current (All inputs 0 V or at supply)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
mA
Si8451Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
mA
Si8452Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
—
—4.3 3.5 6.5 5.3 mA
Si8451Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Si8452Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
Rev. 1.6 9
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.3 4.8 6.5 6.7 mA
Si8451Bx
VDD1
VDD2
—
—4.4 5.0 6.2 7.0 mA
Si8452Bx
VDD1
VDD2
—
—4.6 4.8 6.4 6.7 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.4 16.8 6.6 21 mA
Si8451Bx
VDD1
VDD2
—
—6.9 14.5 8.6 18.1 mA
Si8452Bx
VDD1
VDD2
—
—9.5 12 11.9 15 mA
Timing Characteristics
Si845xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL,tPLH See Figure 2 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
10 Rev. 1.6
Not Recommended
for NewDesigns
Si845xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL=15pF
See Figure 2 —4.36.1ns
Output Fall Time tfCL=15pF
See Figure 2 —3.04.3ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Enable to Data Valid3ten1 See Figure 1 — 5.0 8.0 ns
Enable to Data Tri-State3ten2 See Figure 1 — 7.0 9.2 ns
Start-up Time3,4 tSU —1540µs
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
Rev. 1.6 11
Not Recommended
for NewDesigns
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH lOH = –4mA V
DD1,VDD2 –0.4 2.3 — V
Low Level Output Voltage VOL IOL =4mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance2ZO—85—
Enable Input High Current IENH VENx =V
IH —2.0—µA
Enable Input Low Current IENL VENx =V
IL —2.0—µA
DC Supply Current (All inputs 0 V or at supply)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
mA
Si8451Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
mA
Si8452Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
—
—4.3 3.5 6.5 5.3 mA
Si8451Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Si8452Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
12 Rev. 1.6
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.3 4.8 6.5 6.7 mA
Si8451Bx
VDD1
VDD2
—
—4.4 5.0 6.2 7.0 mA
Si8452Bx
VDD1
VDD2
—
—4.6 4.8 6.4 6.7 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.3 13.3 6.5 16.6 mA
Si8451Bx
VDD1
VDD2
—
—6.2 11.7 7.8 14.6 mA
Si8452Bx
VDD1
VDD2
—
—8.0 9.9 10 12.4 mA
Timing Characteristics
Si845xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL,tPLH See Figure 2 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — — 25 ns
Propagation Delay Skew3tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 5. Electrical Characteristics1(Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.

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Si845xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — 1.5 2.5 ns
Propagation Delay Skew3tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL=15pF
See Figure 2 —4.86.5ns
Output Fall Time tfCL=15pF
See Figure 2 —3.24.6ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Enable to Data Valid4ten1 See Figure 1 — 5.0 8.0 ns
Enable to Data Tri-State4ten2 See Figure 1 — 7.0 9.2 ns
Start-up Time4,5 tSU —1540µs
Table 5. Electrical Characteristics1(Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
5. Start-up time is the time period from the application of power to valid data at the output.

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Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 130 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 Vpeak for basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 28.
Table 7. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
NB SOIC-16
Nominal Air Gap (Clearance)1L(IO1) 4.9 mm
Nominal External Tracking (Creepage)1L(IO2) 4.01 mm
Minimum Internal Gap (Internal Clearance) 0.008 mm
Tracking Resistance
(Proof Tracking Index) PTI IEC60112 600 VRMS
Erosion Depth ED 0.019 mm
Resistance (Input-Output)2RIO 1012 
Capacitance (Input-Output)2CIO f=1MHz 2.0 pF
Input Capacitance3CI4.0 pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in "7. Package Outline:
16-Pin Narrow Body SOIC" on page 30. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the
NB SOIC-16 package. UL does not impose a clearance and creepage minimum for component level certifications. CSA
certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.

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Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Test Condition Specification
Basic Isolation Group Material Group I
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV
Rated Mains Voltages < 300 VRMS I-III
Rated Mains Voltages < 400 VRMS I-II
Rated Mains Voltages < 600 VRMS I-II
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter Symbol Test Condition Characteristic Unit
Maximum Working Insulation Voltage VIORM 560 V peak
Input to Output Test Voltage VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm=1sec,
Partial Discharge < 5 pC) 1050
V peak
Transient Overvoltage VIOTM t = 60 sec 4000 V peak
Pollution Degree (DIN VDE 0110, Table 1) 2
Insulation Resistance at TS, VIO =500V RS>109
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter Symbol Test Condition Min Typ Max Unit
NB SOIC-16
Case Temperature TS—— 150 °C
Safety input, output, or
supply current ISJA = 105 °C/W (NB SOIC-16),
VI=5.5V,T
J=150°C,T A=25°C —— 215 mA
Device Power Dissipa-
tion2PD—— 415 mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 3.
2. The Si845x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.

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Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 11. Thermal Characteristics
Parameter Symbol Typ Unit
NB SOIC-16
IC Junction-to-Air Thermal Resistance JA 105 °C/W
0 20015010050
500
400
200
100
0
Temperature (ºC)
Safety-Limiting Current (mA)
430
300
360
215
VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.6 V
VDD1, VDD2 = 5.5 V

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2. Functional Description
2.1. Theory of Operation
The operation of an Si845x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si845x channel is shown in
Figure 4.
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Figure 5. Modulation Scheme
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Input Signal
Output Signal
Modulation Signal

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2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8450. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8450 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 6. Eye Diagram

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2.3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Table 12. Table 13 provides an
overview of the output states when the Enable pins are active.
Table 12. Si845x Logic Operation Table
VI
Input1,2 EN
Input1,2,3,4 VDDI State1,5,6 VDDO State1,5,6 VOOutput1,2 Comments
H H or NC P P H Enabled, normal operation.
LHorNC P P L
X7L P P Hi-Z or L8Disabled.
X7H or NC UP P L Upon transition of VDDI from unpowered to pow-
ered, VOreturns to the same state as VIin less
than 1 µs.
X7L UP P Hi-Z or L8Disabled.
X7X7P UP Undetermined Upon transition of VDDO from unpowered to pow-
ered, VOreturns to the same state as VIwithin
1 µs, if EN is in either the H or NC state. Upon tran-
sition of VDDO from unpowered to powered, VO
returns to Hi-Z within 1 µs if EN is L.
Notes:
1. VDDI and VDDO are the input and output power supplies. VIand VOare the respective input and output terminals. EN
is the enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si845x is
operating in noisy environments.
4. No Connect (NC) replaces EN1 on Si8450. No Connects are not internally connected and can be left floating, tied to
VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 25 for more details.

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Table 13. Enable Input Truth Table1
P/N EN11,2 EN21,2 Operation
Si8450 — H Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
— L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance
state.3
Si8451 H X Output A5 enabled and follow input state.
L X Output A5 disabled and Logic Low or in high impedance state.3
X H Outputs B1, B2, B3, B4 are enabled and follow input state.
X L Outputs B1, B2, B3, B4 are disabled and Logic Low or in high impedance state.3
Si8452 H X Outputs A4 and A5 are enabled and follow input state.
L X Outputs A4 and A5 are disabled and Logic Low or in high impedance state.3
X H Outputs B1, B2, B3 are enabled and follow input state.
X L Outputs B1, B2, B3 are disabled and Logic Low or in high impedance state.3
Si8455 — — Outputs B1, B2, B3, B4, B5 are enabled and follow input state.
Notes:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are
internally pulled-up to local VDD by a 3 µA current source allowing them to be connected to an external logic level (high
or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If
EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si845x is
operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven to a logic low state when the EN pin is disabled
(EN = 0) in Revision A. Revision B outputs go into a high-impedance state when the EN pin is disabled (EN = 0). See
"3. Errata and Design Migration Guidelines" on page 25 for more details.