Silicon Laboratories Si8451 User manual

Not Recommended
for NewDesigns
Rev. 1.6 4/18 Copyright © 2018 by Silicon Laboratories Si8450/51/52/55
Si8450/51/52/55
LOW POWER FIVE-CHANNEL DIGITAL ISOLATOR
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrow-
body SOIC package.
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.70–5.5 V
Ultra-low-power (typical)
5 V Operation:
< 1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps
2.70 V Operation:
< 1.4 mA per channel at 1 Mbps
< 4 mA per channel at 100 Mbps
High electromagnetic immunity
Up to 2500 VRMS isolation
60-year life at rated working
voltage
Precise timing (typical)
<10 ns worst case
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
Transient Immunity 25 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS-compliant packages
SOIC-16 narrow body
Industrial automation systems
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communications systems
UL 1577 recognized
Up to 2500 VRMS for 1 minute
CSA component notice 5A
approval
IEC 60950-1, 61010-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
Ordering Information:
See page 28.

Si8450/51/52/55
Rev. 1.6 2
Not Recommended
for NewDesigns
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.1. Enable Pin Causes Outputs to Go Low (Revision A Only) . . . . . . . . . . . . . . . . . . . .25
3.2. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . .25
3.3. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Si8450/51/52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5. Pin Descriptions (Si8455) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Si8450/51/52/55
Rev. 1.6 3
Not Recommended
for NewDesigns
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 °C
Supply Voltage VDD1 2.70 — 5.5 V
VDD2 2.70 — 5.5 V
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 °C
Ambient Temperature Under Bias TA–40 — 125 °C
Supply Voltage (Revision A)3VDD1, VDD2 –0.5 — 5.75 V
Supply Voltage (Revision B)3VDD1, VDD2 –0.5 — 6.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive Channel IO——10mA
Lead Solder Temperature (10 s) — — 260 °C
Maximum Isolation Voltage (1 s) — — 3600 VRMS
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "6. Ordering Guide" on page 28 for more information.

Si8450/51/52/55
4 Rev. 1.6
Not Recommended
for NewDesigns
Table 3. Electrical Characteristics
(VDD1 =5V±10%,V
DD2 =5V±10%,T A= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—85—
Enable Input High Current IENH VENx =V
IH —2.0—µA
Enable Input Low Current IENL VENx =V
IL —2.0—µA
DC Supply Current (All inputs 0 V or at Supply)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
mA
Si8451Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
mA
Si8452Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
—
—4.3 3.5 6.5 5.3 mA
Si8451Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Si8452Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
Rev. 1.6 5
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.3 4.8 6.5 6.7 mA
Si8451Bx
VDD1
VDD2
—
—4.4 5.0 6.2 7.0 mA
Si8452Bx
VDD1
VDD2
—
—4.6 4.8 6.4 6.7 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.6 24 6.9 30 mA
Si8451Bx
VDD1
VDD2
—
—8.6 20.4 10.8 25.5 mA
Si8452Bx
VDD1
VDD2
—
—12.6 16.5 15.8 20.6 mA
Timing Characteristics
Si845xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 3. Electrical Characteristics (Continued)
(VDD1 =5V±10%,V
DD2 =5V±10%,T A= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
6 Rev. 1.6
Not Recommended
for NewDesigns
Si845xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL=15pF
See Figure 2 —3.85.0ns
Output Fall Time tfCL=15pF
See Figure 2 —2.83.7ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Enable to Data Valid3ten1 See Figure 1 — 5.0 8.0 ns
Enable to Data Tri-State3ten2 See Figure 1 — 7.0 9.2 ns
Start-up Time3,4 tSU —1540µs
Table 3. Electrical Characteristics (Continued)
(VDD1 =5V±10%,V
DD2 =5V±10%,T A= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
Rev. 1.6 7
Not Recommended
for NewDesigns
Figure 1. ENABLE Timing Diagram
Figure 2. Propagation Delay Timing
ENABLE
OUTPUTS
ten1 ten2
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V

Si8450/51/52/55
8 Rev. 1.6
Not Recommended
for NewDesigns
Table 4. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance1ZO—85—
Enable Input High Current IENH VENx = VIH —2.0—µA
Enable Input Low Current IENL VENx = VIL —2.0—µA
DC Supply Current (All inputs 0 V or at supply)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
—
—
—
—
1.6
2.9
7.0
3.1
2.4
4.4
10.5
4.7
mA
Si8451Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 dc
All inputs 0 dc
All inputs 1 dc
All inputs 1 dc
—
—
—
—
2.0
3.0
6.0
4.1
3.0
4.5
9.0
6.2
mA
Si8452Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.3
2.7
5.4
4.7
3.5
4.1
8.1
7.1
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8450Ax, Bx, Si8455Bx
VDD1
VDD2
—
—4.3 3.5 6.5 5.3 mA
Si8451Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Si8452Ax, Bx
VDD1
VDD2
—
—4.1 4.0 6.2 6.0 mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
Rev. 1.6 9
Not Recommended
for NewDesigns
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.3 4.8 6.5 6.7 mA
Si8451Bx
VDD1
VDD2
—
—4.4 5.0 6.2 7.0 mA
Si8452Bx
VDD1
VDD2
—
—4.6 4.8 6.4 6.7 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8450Bx, Si8455Bx
VDD1
VDD2
—
—4.4 16.8 6.6 21 mA
Si8451Bx
VDD1
VDD2
—
—6.9 14.5 8.6 18.1 mA
Si8452Bx
VDD1
VDD2
—
—9.5 12 11.9 15 mA
Timing Characteristics
Si845xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL,tPLH See Figure 2 — — 35 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.

Si8450/51/52/55
10 Rev. 1.6
Not Recommended
for NewDesigns
Si845xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns
Pulse Width Distortion
|tPLH -tPHL|PWD See Figure 2 — 1.5 2.5 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.8ns
All Models
Output Rise Time trCL=15pF
See Figure 2 —4.36.1ns
Output Fall Time tfCL=15pF
See Figure 2 —3.04.3ns
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V — 25 — kV/µs
Enable to Data Valid3ten1 See Figure 1 — 5.0 8.0 ns
Enable to Data Tri-State3ten2 See Figure 1 — 7.0 9.2 ns
Start-up Time3,4 tSU —1540µs
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. See "3. Errata and Design Migration Guidelines" on page 25 for more details.
4. Start-up time is the time period from the application of power to valid data at the output.