Silicon Laboratories EFM32G User manual

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EFM32G Reference Manual
Gecko Series
• 32-bit ARM Cortex-M3 processor running at up to 32 MHz
• Up to 128 kB Flash and 16 kB RAM memory
• Energy efficient and autonomous peripherals
• Ultra low power Energy Modes with sub-µA operation
• Fast wake-up time of only 2 µs
The EFM32G microcontroller series revolutionizes the 8- to 32-bit market with a
combination of unmatched performance and ultra low power consumption in both
active- and sleep modes. EFM32G devices consume as little as 180 µA/MHz in run
mode, and as little as 900 nA with a Real Time Counter running, Brown-out and full
RAM and register retention.
EFM32G's low energy consumption outperforms any other available 8-, 16-, and 32-
bit solution. The EFM32G includes autonomous and energy efficient peripherals,
high overall chip- and analog integration, and the performance of the industry
standard 32-bit ARM Cortex-M3 processor.

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1 Energy Friendly Microcontrollers
1.1 Typical Applications
The EFM32G Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
These devices are developed to minimize the energy consumption by lowering both the power and the
active time, over all phases of MCU operation. This unique combination of ultra low energy consumption
and the performance of the 32-bit ARM Cortex-M3 processor, help designers get more out of the
available energy in a variety of applications.
Ultra low energy EFM32G microcontrollers are perfect for:
• Gas metering
• Energy metering
• Water metering
• Smart metering
• Alarm and security systems
• Health and fitness applications
• Industrial and home automation
01 2 3 4
1.2 EFM32G Development
Because EFM32G use the Cortex-M3 CPU, embedded designers benefit from the largest development
ecosystem in the industry, the ARM ecosystem. The development suite spans the whole design
process and includes powerful debug tools, and some of the world’s top brand compilers. Libraries with
documentation and user examples shorten time from idea to market.
The range of EFM32G devices ensure easy migration and feature upgrade possibilities.

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2 About This Document
This document contains reference material for the EFM32G series of microcontrollers. All modules and
peripherals in the EFM32G series devices are described in general terms. Not all modules are present
in all devices, and the feature set for each device might vary. Such differences, including pin-out, are
covered in the device-specific datasheets.
2.1 Conventions
Register Names
Register names are given as a module name prefix followed by the short register name:
TIMERn_CTRL - Control Register
The "n" denotes the numeric instance for modules that might have more than one instance.
Some registers are grouped which leads to a group name following the module prefix:
GPIO_Px_DOUT - Port Data Out Register,
where xdenotes the port instance (A,B,...).
Bit Fields
Registers contain one or more bit fields which can be 1 to 32 bits wide. Multi-bit fields are denoted with
(x:y), where xis the start bit and yis the end bit.
Address
The address for each register can be found by adding the base address of the module (found in the
Memory Map), and the offset address for the register (found in module Register Map).
Access Type
The register access types used in the register descriptions are explained in Table 2.1 (p. 3) .
Table 2.1. Register Access Types
Access Type Description
R Read only. Writes are ignored.
RW Readable and writable.
RW1 Readable and writable. Only writes to 1 have effect.
RW1H Readable, writable and updated by hardware. Only writes to
1 have effect.
W1 Read value undefined. Only writes to 1 have effect.
W Write only. Read value undefined.
RWH Readable, writable and updated by hardware.
Number format
0x prefix is used for hexadecimal numbers.
0b prefix is used for binary numbers.
Numbers without prefix are in decimal representation.

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Reserved
Registers and bit fields marked with reserved are reserved for future use. These should be written to 0
unless otherwise stated in the Register Description. Reserved bits might be read as 1 in future devices.
Reset Value
The reset value denotes the value after reset.
Registers denoted with X have an unknown reset value and need to be initialized before use. Note
that, before these registers are initialized, read-modify-write operations might result in undefined register
values.
Pin Connections
Pin connections are given as a module prefix followed by a short pin name:
USn_TX (USARTn TX pin)
The pin locations referenced in this document are given in the device-specific datasheet.
2.2 Related Documentation
Further documentation on the EFM32G family and the ARM Cortex-M3 can be found at the Silicon
Laboratories and ARM web pages:
www.silabs.com
www.arm.com

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3 System Overview
3.1 Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination
of the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from
energy saving modes, and a wide selection of peripherals, the EFM32G microcontroller is well suited for
any battery operated application, as well as other systems requiring high performance and low-energy
consumption, see Figure 3.1 (p. 7) .
3.2 Features
•ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 32 MHz
• Memory Protection Unit
• Wake-up Interrupt Controller
•Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on
Reset, Brown-out Detector, RAM and CPU retention
• 45 µA/MHz @ 3 V Sleep Mode
• 180 µA/MHz @ 3 V Run Mode, with code executed from flash
•128/64/32/16 KB Flash
•16/8 KB RAM
•Up to 90 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
•8 Channel DMA Controller
• Alternate/primary descriptors with scatter-gather/ping-pong operation
•8 Channel Peripheral Reflex System
• Autonomous inter-peripheral signaling enables smart operation in low energy modes
•External Bus Interface (EBI)
• Up to 4x64 MB of external memory mapped space
•Integrated LCD Controller for up to 4×40 Segments
• Voltage boost, adjustable contrast adjustment and autonomous animation feature
•Hardware AES with 128/256-bit Keys in 54/75 cycles
•Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA
• Triple buffered full/half-duplex operation
• 4-16 data bits
• 1× Universal Asynchronous Receiver/Transmitter
• Triple buffered full/half-duplex operation
• 8-9 data bits
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
• 1× I2C Interface with SMBus support
• Address recognition in Stop Mode
•Timers/Counters

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• 3× 16-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 24-bit Real-Time Counter
• 3× 8-bit Pulse Counter
• Asynchronous pulse counting/quadrature decoding
• Watchdog Timer with dedicated RC oscillator @ 50 nA
•Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 input channels and on-chip temperature sensor
• Single ended or differential operation
• Conversion tailgating for predictable latency
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• 2× Analog Comparator
• Programmable speed/current
• Capacitive sensing with up to 8 inputs
• Supply Voltage Comparator
•Ultra efficient Power-on Reset and Brown-Out Detector
•2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
•Temperature range -40 - 85°C
•Single power supply 1.98 - 3.8 V
•Packages
• QFN32
• QFN64
• TQFP48
• TQFP64
• LQFP100
• LFBGA112
3.3 Block Diagram
Figure 3.1 (p. 7) shows the block diagram of EFM32G. The color indicates peripheral availability in
the different energy modes, described in Section 3.4 (p. 7) .

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Figure 3.1. Block Diagram of EFM32G
Clock Management Energy Management
Serial Interfaces
I/O Ports
Core andMemory
Timers andTriggers Analog Interfaces Security
ARM Cortex™- M3 processor
Flash
Program
Memory
Peripheral
Reflex
System
High Frequency
RC
Oscillator
High Frequency
Crystal
Oscillator
Timer/
Counter
Low Energy
Timer™
Pulse
Counter
Real Time
Counter
Low Frequency
Crystal
Oscillator
Low Frequency
RC
Oscillator
LCD
Controller
Voltage
Regulator
Watchdog
Timer
RAM
Memory
Voltage
Comparator
Power-on
Reset Brown-out Detector
Analog
Comparator
External
Bus
Interface
General
Purpose
I/ O
Low
Energy
UART™
Watchdog
Oscillator
Memory
Protection
Unit
ADC DAC
DMA
Controller
Debug
Interface
External
Interrupts Pin Reset
USART
I
2
C
UART AES
Gecko
32-bit bus
Peripheral Reflex System
Figure 3.2. Energy Mode Indicator
01 2 3 4
Note In the energy mode indicator, the numbers indicates Energy Mode, i.e EM0-EM4.
3.4 Energy Modes
There are five different Energy Modes (EM0-EM4) in the EFM32G, see Table 3.1 (p. 8). The
EFM32G is designed to achieve a high degree of autonomous operation in low energy modes. The
intelligent combination of peripherals, RAM with data retention, DMA, low-power oscillators, and short
wake-up time, makes it attractive to remain in low energy modes for long periods and thus saving energy
consumption.
Tip
Throughout this document, the first figure in every module description contains an Energy Mode
Indicator showing which energy mode(s) the module can operate (see Table 3.1 (p. 8) ).

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Table 3.1. Energy Mode Description
Energy Mode Name Description
01 2 3 4 EM0 – Energy Mode 0
(Run mode)
In EM0, the CPU is running and consuming as little as 180 µA/MHz, when
running code from flash. All peripherals can be active.
01 2 3 4 EM1 – Energy Mode 1
(Sleep Mode) In EM1, the CPU is sleeping and the power consumption is only 45 µA/MHz. All peripherals, including DMA, PRS and memory system, are still available.
01 2 3 4 EM2 – Energy Mode 2
(Deep Sleep Mode)
In EM2 the high frequency oscillator is turned off, but with the 32.768 kHz
oscillator running, selected low energy peripherals (LCD, RTC, LETIMER,
PCNT, LEUART, I2C, WDOG and ACMP) are still available. This gives a high
degree of autonomous operation with a current consumption as low as 0.9 µA
with RTC enabled. Power-on Reset, Brown-out Detection and full RAM and
CPU retention is also included.
01 2 3 4 EM3 - Energy Mode 3
(Stop Mode)
In EM3, the low-frequency oscillator is disabled, but there is still full CPU
and RAM retention, as well as Power-on Reset, Pin reset and Brown-
out Detection, with a consumption of only 0.6 µA. The low-power ACMP,
asynchronous external interrupt, PCNT, and I2C can wake-up the device.
Even in this mode, the wake-up time is a few microseconds.
01 2 3 4 EM4 – Energy Mode 4
(Shutoff Mode)
In EM4, the current is down to 20 nA and all chip functionality is turned off
except the pin reset and the Power-On Reset. All pins are put into their reset
state.
3.5 Product Overview
Table 3.2(p. 8) shows a device overview of the EFM32G Microcontroller Series, including peripheral
functionality. For more information, the reader is referred to the device specific datasheets.
Table 3.2. EFM32G Microcontroller Series
EFM32G Part # Flash RAM GPIO(pins) LCD USART+UART LEUART I2C Timer(PWM) LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) ACMP(pins) AES EBI Package
200F16 16 8 24 - 2 1 1 2
(6) 111 11 (4) 1 (1) 2 (5) - - QFN32
200F32 32 8 24 - 2 1 1 2
(6) 111 11 (4) 1 (1) 2 (5) - - QFN32
200F64 64 16 24 - 2 1 1 2
(6) 111 11 (4) 1 (1) 2 (5) - - QFN32
210F128 128 16 24 - 2 1 1 2
(6) 111 11 (4) 1 (1) 2 (5) Y - QFN32

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EFM32G Part # Flash RAM GPIO(pins) LCD USART+UART LEUART I2C Timer(PWM) LETIMER RTC PCNT Watchdog ADC(pins) DAC(pins) ACMP(pins) AES EBI Package
230F32 32 8 56 - 3 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y - QFN64
230F64 64 16 56 - 3 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y - QFN64
230F128 128 16 56 - 3 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y - QFN64
280F32 32 8 85 - 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y LQFP100
280F64 64 16 85 - 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y LQFP100
280F128 128 16 85 - 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y LQFP100
290F32 32 8 90 - 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y LFBGA112
290F64 64 16 90 - 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y LFBGA112
290F128 128 16 90 - 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y LFBGA112
840F32 32 8 56 4x24 3 2 1 3
(9) 113 11 (8) 2 (2) 2 (8) Y - QFN64
840F64 64 16 56 4x24 3 2 1 3
(9) 113 11 (8) 2 (2) 2 (8) Y - QFN64
840F128 128 16 56 4x24 3 2 1 3
(9) 113 11 (8) 2 (2) 2 (8) Y - QFN64
880F32 32 8 85 4x40 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y 1LQFP100
880F64 64 16 85 4x40 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y1LQFP100
880F128 128 16 85 4x40 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y1LQFP100
890F32 32 8 90 4x40 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y1LFBGA112
890F64 64 16 90 4x40 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y1LFBGA112
890F128 128 16 90 4x40 3+1 2 1 3
(9) 113 11 (8) 2 (2) 2 (16) Y Y1LFBGA112
1EBI and LCD share pins in the part. Only a reduced pin count LCD driver can be used simultaneously with the EBI.
3.6 Device Revision
The device revision number is read from the ROM Table. The major revision number and the chip family
number is read from PID0 and PID1 registers. The minor revision number is extracted from the PID2 and
PID3 registers, as illustrated in Figure 3.3 (p. 10). The Fam[5:2] and Fam[1:0] must be combined
to complete the chip family number, while the Minor Rev[7:4] and Minor Rev[3:0] must be combined to
form the complete revision number.

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Figure 3.3. Revision Number Extraction
PID1 (0xE00FFFE4)
31:4 3:0
PID0 (0xE00FFFE0)
31:7 6:5 5:0
Major Rev[5:0]
PID3 (0xE00FFFEC)
31:8 7:4 3:0
Minor Rev[3:0]
Fam[1:0] Fam[5:2]
PID2 (0xE00FFFE8)
31:8 7:4 3:0
Minor Rev[7:4]
For the latest revision of the Gecko family, the chip family number is 0x00 and the major revision number
is 0x01. The minor revision number is to be interpreted according to Table 3.3 (p. 10) .
Table 3.3. Minor Revision Number Interpretation
Minor Rev[7:0] Revision
0x00 A
0x01 B
0x02 C
0x03 D

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4 System Processor
01 2 3 4
CM3 Core
32- bit ALU
Control Logic Thumb & Thumb- 2
Decode
Instruction Interface Data Interface
NVIC Interface
Single cycle
32- bit multiplier
Hardware divider
Memory Protection Unit
Quick Facts
What?
The industry leading Cortex-M3 processor
from ARM is the CPU in the EFM32G
microcontrollers.
Why?
The ARM Cortex-M3 is designed for
exceptional short response time, high
code density, and high 32-bit throughput
while maintaining a strict cost and power
consumption budget.
How?
Combined with the ultra low energy
peripherals available, the Cortex-M3 makes
the EFM32G devices perfect for 8- to 32-bit
applications. The processor is featuring a
Harvard architecture, 3 stage pipeline, single
cycle instructions, Thumb-2 instruction set
support, and fast interrupt handling.
4.1 Introduction
The ARM Cortex-M3 32-bit RISC processor provides outstanding computational performance and
exceptional system response to interrupts while meeting low cost requirements and low power
consumption.
The ARM Cortex-M3 implemented is revision r2p0.
4.2 Features
• Harvard Architecture
• Separate data and program memory buses (No memory bottleneck as for a single-bus system)
• 3-stage pipeline
• Thumb-2 instruction set
• Enhanced levels of performance, energy efficiency, and code density
• Single-cycle multiply and efficient divide instructions
• 32-bit multiplication in a single cycle
• Signed and unsigned divide operations between 2 and 12 cycles
• Atomic bit manipulation with bit banding
• Direct access to single bits of data
• Two 1MB bit banding regions for memory and peripherals mapping to 32MB alias regions
• Atomic operation which cannot be interrupted by other bus activities
• 1.25 DMIPS/MHz
• Memory Protection Unit
• Up to 8 protected memory regions
• 24-bit System Tick Timer for Real-Time Operating System (RTOS)
• Excellent 32-bit migration choice for 8/16 bit architecture based designs
• Simplified stack-based programmer's model is compatible with traditional ARM architecture and
retains the programming simplicity of legacy 8- and 16-bit architectures

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• Unaligned data storage and access
• Continuous storage of data requiring different byte lengths
• Data access in a single core clock cycle
• Integrated power modes
• Sleep Now mode for immediate transfer to low power state
• Sleep on Exit mode for entry into low power state after the servicing of an interrupt
• Ability to extend power savings to other system components
• Optimized for low latency, nested interrupts
4.3 Functional Description
For a full functional description of the ARM Cortex-M3 (r2p0) implementation in the EFM32G family, the
reader is referred to the EFM32G Cortex-M3 Reference Manual.
4.3.1 Interrupt Operation
Figure 4.1. Interrupt Operation
Module Cortex- M3 NVIC
IEN[n]
IF[n]
set clear
IFS[n] IFC[n]
Interrupt
condition IRQ
SETENA[n]/ CLRENA[n]
Interrupt
request
SETPEND[n]/ CLRPEND[n]
set clear
Active interrupt
Software generated interrupt
The EFM32G devices have up to 30 interrupt request lines (IRQ) which are connected to the Cortex-M3.
Each of these lines (shown in Table 4.1 (p. 12)) are connected to one or more interrupt flags in one
or more modules. The interrupt flags are set by hardware on an interrupt condition. It is also possible
to set/clear the interrupt flags through the IFS/IFC registers. Each interrupt flag is then qualified with its
own interrupt enable bit (IEN register), before being OR'ed with the other interrupt flags to generate the
IRQ. A high IRQ line will set the corresponding pending bit (can also be set/cleared with the SETPEND/
CLRPEND bits in ISPR0/ICPR0) in the Cortex-M3 NVIC. The pending bit is then qualified with an enable
bit (set/cleared with SETENA/CLRENA bits in ISER0/ICER0) before generating an interrupt request to
the core. Figure 4.1(p. 12) illustrates the interrupt system. For more information on how the interrupts
are handled inside the Cortex-M3, the reader is referred to the EFM32G Cortex-M3 Reference Manual.
Table 4.1. Interrupt Request Lines (IRQ)
IRQ # Source
0 DMA
1 GPIO_EVEN
2 TIMER0
3 USART0_RX
4 USART0_TX
5 ACMP0/ACMP1
6 ADC0
7 DAC0
8 I2C0
9 GPIO_ODD

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IRQ # Source
10 TIMER1
11 TIMER2
12 USART1_RX
13 USART1_TX
14 USART2_RX
15 USART2_TX
16 UART0_RX
17 UART0_TX
18 LEUART0
19 LEUART1
20 LETIMER0
21 PCNT0
22 PCNT1
23 PCNT2
24 RTC
25 CMU
26 VCMP
27 LCD
28 MSC
29 AES

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5 Memory and Bus System
01 2 3 4
ARM Cortex- M3
DMA Controller
RAM
Peripherals
Flash
EBI
Quick Facts
What?
A low latency memory system, including low
energy flash and RAM with data retention,
makes extended use of low-power energy-
modes possible.
Why?
RAM retention reduces the need for storing
data in flash and enables frequent use of the
ultra low energy modes EM2 and EM3 with
as little as 0.6 µA current consumption.
How?
Low energy and non-volatile flash memory
stores program and application data
in all energy modes and can easily be
reprogrammed in system. Low leakage RAM,
with data retention in EM0 to EM3, removes
the data restore time penalty, and the DMA
ensures fast autonomous transfers with
predictable response time.
5.1 Introduction
The EFM32G contains an AMBA AHB Bus system allowing bus masters to access the memory mapped
address space. A multilayer AHB bus matrix, using a Round-robin arbitration scheme, connects the
master bus interfaces to the AHB slaves (Figure 5.1 (p. 15)). The bus matrix allows several AHB
slaves to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are
accessed through an AHB-to-APB bridge connected to the AHB bus matrix. The AHB bus masters are:
•Cortex-M3 ICode: Used for instruction fetches from Code memory (0x00000000 - 0x1FFFFFFF).
•Cortex-M3 DCode: Used for debug and data access to Code memory (0x00000000 - 0x1FFFFFFF).
•Cortex-M3 System: Used for instruction fetches, data and debug access to system space
(0x20000000 - 0xDFFFFFFF).
•DMA: Can access EBI, SRAM, Flash and peripherals (0x00000000 - 0xDFFFFFFF).

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Figure 5.1. EFM32G Bus System
Cortex AHB Multilayer
Bus Matrix
DCode
System
DMA
Flash
RAM
EBI
AHB/ APB
Bridge
ICode
AES
Peripheral 0
Peripheral n
5.2 Functional Description
Thememory segments are mapped together withtheinternalsegments of the Cortex-M3 intothesystem
memory map shown by Figure 5.2 (p. 16)

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Figure 5.2. System Address Space
The embedded SRAM is located at address 0x20000000 in the memory map of the EFM32G. When
running code located in SRAM starting at this address, the Cortex-M3 uses the System bus to fetch
instructions. This results in reduced performance as the Cortex-M3 accesses stack, other data in SRAM
and peripherals using the System bus. To be able to run code from SRAM efficiently, the SRAM is also
mapped in the code space at address 0x10000000. When running code from this space, the Cortex-M3
fetches instructions through the I/D-Code bus interface, leaving the System bus for data access. The
SRAM mapped into the code space can however only be accessed by the CPU, i.e. not the DMA.
5.2.1 Bit-banding
The SRAM bit-band alias and peripheral bit-band alias regions are located at 0x22000000 and
0x42000000 respectively. Read and write operations to these regions are converted into masked single-
bit reads and atomic single-bit writes to the embedded SRAM and peripherals of the EFM32G.
The standard approach to modify a single register or SRAM bit in the aliased regions, requires software
to read the value of the byte, half-word or word containing the bit, modify the bit, and then write the byte,
half-word or word back to the register or SRAM address. Using bit-banding, this read-modify-write can
be done in a single atomic operation. As read-writeback, bit-masking and bit-shift operations are not
necessary in software, code size is reduced and execution speed improved.
The bit-band regions allows addressing each individual bit in the SRAM and peripheral areas of the
memory map. To set or clear a bit in the embedded SRAM, write a 1 or a 0 to the following address:
Memory SRAM Area Set/Clear Bit

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bit_address = 0x22000000 + (address – 0x20000000) × 32 + bit × 4, (5.1)
where address is the address of the 32-bit word containing the bit to modify, and bit is the index of the
bit in the 32-bit word.
To modify a bit in the Peripheral area, use the following address:
Memory Peripheral Area Bit Modification
bit_address = 0x42000000 + (address – 0x40000000) × 32 + bit × 4, (5.2)
where address and bit are defined as above.
Note that the AHB-peripheral AES does not support bit-banding.
5.2.2 Peripherals
The peripherals are mapped into the peripheral memory segment, each with a fixed size address range
according to Table 5.1 (p. 17) , Table 5.2 (p. 18) and Table 5.3 (p. 19) .
Table 5.1. Memory System Core Peripherals
Core peripherals
Address range Peripheral
0x400E0400 – 0x41FFFFFF Reserved
0x400E0000 – 0x400E03FF AES
0x400CC400 – 0x400FFFFF Reserved
0x400CC000 – 0x400CC3FF PRS
0x400CA400 – 0x400CBFFF Reserved
0x400CA000 – 0x400CA3FF RMU
0x400C8400 – 0x400C9FFF Reserved
0x400C8000 – 0x400C83FF CMU
0x400C6400 – 0x400C7FFF Reserved
0x400C6000 – 0x400C63FF EMU
0x400C4000 – 0x400C5FFF Reserved
0x400C2000 – 0x400C3FFF DMA
0x400C0400 – 0x400C1FFF Reserved
0x400C0000 – 0x400C03FF MSC

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Table 5.2. Memory System Low Energy Peripherals
Low energy peripherals
Address range Peripheral
0x4008A400 – 0x400BFFFF Reserved
0x4008A000 – 0x4008A3FF LCD
0x40088400 – 0x40089FFF Reserved
0x40088000 – 0x400883FF WDOG
0x40086C00 – 0x40087FFF Reserved
0x40086800 – 0x40086BFF PCNT2
0x40086400 – 0x400867FF PCNT1
0x40086000 – 0x400863FF PCNT0
0x40084800 – 0x40085FFF Reserved
0x40084400 – 0x400847FF LEUART1
0x40084000 – 0x400843FF LEUART0
0x40082400 – 0x40083FFF Reserved
0x40082000 – 0x400823FF LETIMER0
0x40080400 – 0x40081FFF Reserved
0x40080000 – 0x400803FF RTC

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Table 5.3. Memory System Peripherals
Peripherals
Address range Peripheral
0x40010C00 – 0x4007FFFF Reserved
0x40010800 – 0x40010BFF TIMER2
0x40010400 – 0x400107FF TIMER1
0x40010000 – 0x400103FF TIMER0
0x4000E400 – 0x4000FFFF Reserved
0x4000E000 – 0x4000E3FF UART0
0x4000CC00 – 0x4000DFFF Reserved
0x4000C800 – 0x4000CBFF USART2
0x4000C400 – 0x4000C7FF USART1
0x4000C000 – 0x4000C3FF USART0
0x4000A400 – 0x4000BFFF Reserved
0x4000A000 – 0x4000A3FF I2C0
0x40008400 – 0x40009FFF Reserved
0x40008000 – 0x400083FF EBI
0x40007000 – 0x40007FFF Reserved
0x40006000 – 0x40006FFF GPIO
0x40004400 – 0x40005FFF Reserved
0x40004000 – 0x400043FF DAC0
0x40002400 – 0x40003FFF Reserved
0x40002000 – 0x400023FF ADC0
0x40001800 – 0x40001FFF Reserved
0x40001400 – 0x400017FF ACMP1
0x40001000 – 0x400013FF ACMP0
0x40000400 – 0x40000FFF Reserved
0x40000000 - 0x400003FF VCMP
5.2.3 Bus Matrix
The Bus Matrix connects the memory segments to the bus masters:
• Code: CPU instruction or data fetches from the code space
• System: CPU read and write to the SRAM, EBI and peripherals
• DMA: Access to EBI, SRAM, Flash and peripherals
5.2.3.1 Arbitration
The Bus Matrix uses a round-robin arbitration algorithm which enables high throughput and low latency
while starvation of simultaneous accesses to the same bus slave are eliminated. Round-robin does not
assign a fixed priority to each bus master. The arbiter does not insert any bus wait-states.

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5.2.3.2 Access Performance
The Bus Matrix is a multi-layer energy optimized AMBA AHB compliant bus with an internal bandwidth
equal to 4 times a single AHB-bus.
The Bus Matrix accepts new transfers initiated by each master in every clock cycle without inserting
any wait-states. The slaves, however, may insert wait-states depending on their internal throughput and
the clock frequency.
The Cortex-M3, the DMA Controller, and the peripherals run on clocks that can be prescaled separately.
When accessing a peripheral which runs on a frequency equal to or faster than the HFCORECLK, the
number of wait cycles per access, in addition to master arbitration, is given by:
Memory Wait Cycles with Clock Equal or Faster than HFCORECLK
Ncycles = 2 + Nslave cycles, (5.3)
where Nslave cycles is the wait cycles introduced by the slave.
When accessing a peripheral running on a clock slower than the HFCORECLK, wait-cycles are
introduced to allow the transfer to complete on the peripheral clock. The number of wait cycles per
access, in addition to master arbitration, is given by:
Memory Wait Cycles with Clock Slower than CPU
Ncycles = (2 + Nslave cycles) x fHFCORECLK/fHFPERCLK, (5.4)
where Nslave cycles is the number of wait cycles introduced by the slave.
For general register access, Nslave cycles = 1.
More details on clocks and prescaling can be found in Chapter 11 (p. 95) .
5.3 Access to Low Energy Peripherals (Asynchronous Registers)
5.3.1 Introduction
The Low Energy Peripherals are capable of running when the high frequency oscillator and core system
is powered off, i.e. in energy mode EM2 and in some cases also EM3. This enables the peripherals to
perform tasks while the system energy consumption is minimal.
The Low Energy Peripherals are:
• Liquid Crystal Display driver - LCD
• Low Energy Timer - LETIMER
• Low Energy UART - LEUART
• Pulse Counter - PCNT
• Real Time Counter - RTC
• Watchdog - WDOG
All Low Energy Peripherals are memory mapped, with automatic data synchronization. Because the Low
Energy Peripherals are running on clocks asynchronous to the core clock, there are some constraints
on how register accesses can be done, as described in the following sections.