Silicon Laboratories Si5365-EVB User manual

Rev. 0.6 1/12 Copyright © 2012 by Silicon Laboratories Si536x-EVB
Si5365/66-EVB
Si5367/68-EVB
Si5369-EVB
Si5365/66/67/68/69 EVALUATION BOARD USER’SGUIDE
1. Introduction
The Si5365/66-EVB,Si5367/68-EVB, and Si5369-EVB provide platforms for evaluating Silicon Laboratories'
Si5365/Si5366, Si5367/Si5368, and Si5369 Any-Frequency Precision Clocks. The Si5365 and Si5366 are
controlled directly using configuration pins on the devices, while the Si5367, Si5368, and Si5369 are controlled by
a microprocessor or MCU (microcontroller unit) via an I2C or SPI interface. The Si5365 and Si5367 are low jitter
clock multipliers with a loop bandwidth ranging from 30 kHz to 1.3 MHz. The Si5366 and Si5368 are jitter-
attenuating clock multipliers, with a loop bandwidth ranging from 60 Hz to 8.4 kHz. The Si5369 is similar to the
Si5368, with a much lower loop BW of from 4 to 525 Hz. The Si5366 device can optionally be configured to operate
as a Si5365, so a single evaluation board is available to evaluate both devices. Likewise, the Si5368 can be
configured to operate as a Si5367, so the two devices share a single evaluation board.
The Si5365/66/67/68/69 Any-Frequency Precision Clocks are based on Silicon Laboratories' 3rd-generation
DSPLL®technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The devices have excellent phase noise and jitter
performance. The Si5366, Si5368, and Si5369 jitter attenuating clock multipliers support jitter generation of 0.3 ps
RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. The Si5365 and SI5367 support
jitter generation of 0.6 ps RMS (typ) across the 12 kHz–20 MHz and 50 kHz–80 MHz jitter filter bandwidths. For all
devices, the DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the
application level. These devices are ideal for providing clock multiplication/clock division, jitter attenuation, and
clock distribution in mid-range and high performance timing applications.
Figure 1. Si536x TQFP EVB
Top Bottom

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
2 Rev. 0.6
2. Applications
The Si536x Any-Frequency Precision Clocks have a comprehensive feature set, including any-frequency
synthesis, multiple clock inputs, multiple clock outputs, alarm and status outputs, hitless switching between input
clocks, programmable output clock signal format (LVPECL, LVDS, CML, CMOS), output phase adjustment
between output clocks, and output phase adjustment between all output clocks and the selected reference input
clock (phase increment/decrement). For more details, consult the Silicon Laboratories timing products website at
www.silabs.com/timing.
Both evaluation boards (EVBs) have a Silicon Laboratories MCU (C8051F340) that supports USB communications
with a PC host. For the pin controlled parts (Si5365 and Si5366), the pin settings of the devices are determined by
the MCU and the PC resident software that is provided with the EVB. For the MCU controlled parts (Si5367,
Si5368, and Si5369), the devices are controlled and monitored through the serial port (either SPI or I2C). A CPLD
sits between the MCU and the Precision Clock device that performs voltage level translation and stores the pin
configuration data for the pin controlled devices. Jumper plugs are provided so that the user can bypass the MCU/
CPLD to manually control the pin controlled devices. Ribbon headers and SMA connectors are included so that
external clock in, clock out and status pins can be easily accessed by the user. For the MCU controlled devices
(Si5367, Si5368, and Si5369)), the user also has the option of bypassing the MCU and controlling the parts from an
external serial device. On-board termination is included so that the user can evaluate either single-ended or
differential as well as ac or dc coupled clock inputs and outputs. A separate DUT (device under test) power supply
connector is included so that the Precision Clocks can be run at either 1.8, 2.5, or 3.3 V, while the USB MCU
remains at 3.3 V. LEDs are provided for convenient monitoring of key status signals.
For more detailed information about these devices, refer to the Any-Frequency Precision Clock Family Reference
Manual.
Table 1. Features by Part Number
Device PN # Clock Inputs # Clock Outputs Control Input Freq (MHz) Output Freq (MHz) Jitter Generation (12 kHz–20 MHz) Prog. Loop BW Clock Mult. Hitless Switching Alarms Package
Precision Clock Multipliers
Si5365 4 5 Pin 15 to
707 19 to 1050 0.6 ps rms typ 30 kHz–1.3 MHz Y N LOS, FOS 14 x 14 100-TQFP
Si5367 4 5 I2C or
SPI 10 to 710 10 to 1400 0.6 ps rms typ 30 kHz–1.3 MHz Y N LOS, FOS 14 x 14 100-TQFP
Any-Frequency Precision Clock Multipliers with Jitter Attenuation
Si5366 4 5 Pin .008 to
707 .008 to 1050 0.3 ps rms typ 60 Hz–8.4 kHz Y Y LOL, LOS, FOS 14 x 14 100-TQFP
Si5368 4 5 I2C or
SPI .002 to 710 .002 to 1400 0.3 ps rms typ 60 Hz–8.4 kHz Y Y LOL, LOS, FOS 14 x 14 100-TQFP
Si5369 4 5 I2C or
SPI .002 to 710 .002 to 1400 0.3 ps rms typ 4 Hz–525 Hz Y Y LOL, LOS, FOS 14 x 14 100-TQFP

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 3
3. Features
The Si5365/66-EVB, Si5367/68-EVB, and Si5369-EVBs each include the following:
CD with documentation and EVB software including the DSPLLsim configuration software utility
USB cable
EVB circuit board including a Si5366 (Si5365/66-EVB), a Si5368 (Si5367/68-EVB), or a Si5369 (Si5369-EVB)
User's Guide (this document)
4. Si5365/66-EVB, Si5367/68-EVB, and Si5369-EVB Quick Start
1. Install the Precision Clock EVB Driver. (This must be installed before the EVB is connected to the PC via the
USB cable.) For details, see Section "7.EVB Software Installation" on page 12.
2. Install the Precision Clock EVB Software. (Assumes that Microsoft .NET Framework 3.1 is already installed.)
3. Connect the two power supplies to the EVB. One is 3.3 V and the other is either 1.8, 2.5, or 3.3 V. The DUT is
powered by the 1.8/2.5/3.3 V supply.
4. Turn on the power supplies.
5. Connect a USB cable from the EVB to the PC where the software was installed.
6. Install USB driver.
7. Launch software by clicking on StartProgramsSilicon LaboratoriesPrecision Clock EVB Software
and selecting one of the programs.

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
4 Rev. 0.6
5. Functional Description
The Si5365/66-EVB, Si5367/68-EVB, Si5369-EVB, and DSPLLsim software allow for a complete and simple
evaluation of the functions, features, and performance of the Si536x Any-Frequency Precision Clocks.
5.1. Narrowband versus Wideband Operation
This document describes three evaluation boards: one for the Si5365 and Si5366, another for the Si5367 and
Si5368, and a third for the Si5369. The first evaluation board is for pin controlled clock parts, the second is for clock
parts that are to be controlled by an MCU over a serial port, and the third is for a very low loop bandwidth device
that is also controlled by an MCU. Two of the boards supports two parts: one that is wideband (the Si5365 and the
Si5367) and the one that is narrowband (the Si5366 and the Si5368). The third board only supports the low loop
bandwidth narrowband Si5369. The narrowband parts other than the Si5369 are both capable of operating in the
wideband mode, so evaluation of the wideband parts can be done by using a narrowband part in wideband mode.
As such, these evaluation boards are only populated with narrowband parts.
To evaluate Si5365 device operation using the Si5365/66-EVB, the RATE[1:0] pins must be set to HH using the
jumper provided. To evaluate Si5367 device operation using the Si5367/68-EVB, the Precision Clock EVB
Software should be configured for wideband mode. For details, see the Precision Clock EVB Software
documentation that can be found on the enclosed distribution CD.
5.2. Block Diagram
Figure 2 is a block diagram of the evaluation board. The MCU communicates to the host PC over a USB
connection. The MCU controls and monitors the Si536x through the CPLD. The CPLD, among other tasks,
translates the signals at the MCU voltage level of 3.3 V to the Si536x's voltage level, which is nominally 3.3, 2.5, or
1.8 V. The user has access to all of the Si536x's pins using the various jumper settings as well as through the host
PC via the MCU and CPLD.
Figure 2. Si536x TQFP Block Diagram
USB MCU
SPI bus
CPLD
ss
+3.3 V
DUT PWR
+1.8 V
Vreg
Reset
switch
LEDs
SPI bus
1.8 to 3.3 V
reg addr
Si536x Output
SMAs
Input
SMAs
Ext RefClk
Jumper
Headers
Terminate
status signals
SPI, I2C signals
Control signals
CKOUT1
CKOUT2
CKOUT3
CKOUT4
FSOUT

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 5
5.3. Si536x Input and Output Clocks
The Si536x has four differential inputs that are ac terminated to 50 and then ac coupled to the part. Single ended
operation can be implemented by simply not connecting to one of the two of the differential pairs. When operating
with clock inputs of 1 MHz or less in frequency, the appropriate dc blocking capacitors (C58, C61, C47, C50, C53,
C55, C42 and C45) located on the bottom of the board should be replaced with zero ohm resistors. The reason for
this is that the capacitive reactance of the ac coupling capacitors becomes significant at low frequencies. It is also
important that the CKIN signal meet the minumum rise time of 11 ns (CKNtrf) even though the input frequency is
low.
The four clock outputs are all differential, ac coupled and configured for driving 50 transmission lines. When
using single ended outputs, it is important that the unused half of the output be terminated. Given that the
Frame Sync signal can have a duty cycle that is far from 50%, the Frame Sync outputs are dc coupled. If the
Frame Sync or other clock ouputs signals are configured for CMOS, then the two outputs are not complements of
one another and should be wired in parallel so that the output drive current is doubled. To evaluate CMOS level
Frame Sync outputs, a 0 resistor should be installed at R19. Note that for the MCU controlled parts that support
Frame Sync mode (Si5367 and Si5368), the Frame Sync output signal format can be configured independently of
the other four outputs.
Two jumpers are provided to assist in monitoring the Si536x power. When R36 is removed, J25 can be used to
measure the device current. J18 can be used at any time to monitor the supply voltage at the device.
The Si5366, Si5368, and Si5369 require that an external reference clock be provided to enable the devices to
operate as narrowband jitter attenuators with loop bandwidths as low as 60 Hz (as low as 4 Hz for the Si5369). The
external reference clock can be either a crystal, a stand-alone oscillator or some other clock source. The range of
acceptable reference frequencies is described in the Any-Frequency Precision Clocks Family Reference Manual
(Si53xx-RM). The EVB's are shipped with a 3rd overtone 114.285 MHz crystal that is used in the majority of
applications. J1 and J2 are used when the Si536x is to be configured in narrowband mode with an external
reference oscillator (i.e., without using the 114.285 MHz crystal).
The RATE pins should also be configured for the desired mode, either through DSPLLsim or using the jumper
plugs at J17 (see Table 7 on page 11).
Table 2 shows how the various components should be configured for the three modes of operation:
For a differential external reference, connect the balanced input signals to J1 and J2. For single-ended operation,
connect the input signal to J1 and disconnect J2.
R51 is provided so that a different termination scheme can be used. If R51 is populated, then remove R52 and R24.
Table 2. Reference Input Mode
Mode
Xtal138.88 MHz Ext
Ref2Wideband
Input 1 NC3J1 NC
Input 2 NC J2 NC
C39 NOPOP4install install
C22 NOPOP install NOPOP
R50 NOPOP NOPOP install
R28 install NOPOP NOPOP
RATE0 M—H
RATE1 M—H
Notes:
1. Xtal is 114.285 MHz 3rd overtone.
2. For external reference frequencies and RATE pin settings, see the
Any-Frequency Precision Clock Family Reference Manual.
3. NC—no connect.
4. NOPOP—do not install this component.

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
6 Rev. 0.6
5.4. CPLD
This CPLD is required for the MCU to control an Si536x operating at either 1.8, 2.5, or 3.3 V. The CPLD provides
two main functions: it translates the voltage level from 3.3 V (the MCU voltage) to the Si536x voltage (either 1.8,
2.5, or 3.3 V). The MCU communicates to the CPLD with the SPI signals SS_CPLD_B (slave select), MISO
(master in, slave out), MOSI (master out, slave in) and SCLK. The MCU can talk to CPLD-resident registers that
are connected to pins that control the Si536x's pins, mainly for pin control mode. When the MCU wishes to access
a Si536x register, the SPI signals are passed through the CPLD, while being level translated, to the Si536x. The
CPLD is an EE device that is retains its code that is loaded through the JTAG port (J32). The core of the CPLD
runs at 1.8 V, which is provided by voltage regulator U4. The CPLD also logically connects many of the LEDs to the
appropriate Si536x pins.
Figure 3. SPI Mode Serial Data Flow
5.5. MCU
The MCU communicates with the PC over USB so that PC resident software can be used to control and monitor
the Si536x. The USB connector is J6 and the debug port, by which the MCU is flashed, is J31. The reset switch,
SW1, resets the MCU, but not the CPLD. The MCU is a self-contained USB master and runs all of the code
required to control and monitor the Si536x, both in the MCU mode and in the pin-controlled modes.
U3 contains a unique serial number for each board and U5 is an EEPROM that is used to store configuration
information for the board. The board powers up in free run mode with a configuration that is outlined in "Appendix—
Powerup and Factory Default Settings" on page 25. For the pin controlled parts (Si5365/66-EVB), the contents of
U5 configure the board on power up so that jumper plugs may be used. If DSPLLsim is subsequently run, the
jumper plugs should be removed before DSPLLsim downloads the configuration to the EVB so that the jumpers do
not conflict with the CPLD outputs. For microprocessor parts, U5 configures the EVB for a specific frequency plan
as described in "Appendix—Powerup and Factory Default Settings" on page 25.
The Evaluation board has a serial port connector (J22) that supports the following:
Control by the MCU/CPLD of an Any-Frequency part on an external target board.
Control of the Any-Frequency part that is on the Evaluation board through an external SPI or I2C port.
For details, see J22 (Table 6).
Though they are not needed on this Evaluation Board because the CPLD has low output leakage current, some
applications will require the use of external pullup and pulldown resistors when three level pins are being driven by
external logic drivers. This is particularly true for the pin-controlled parts: the Si5365 and Si5367. Consult the
Si53xx-RM Any-Frequency Precision Clock Family Reference Manual for details.
LVPECL outputs will not function at 1.8 V. If the Si536x part is to be operated at 1.8 V, the output format
needs to be changed by altering either the SFOUT pins (Si5365/66) or the SFOUT register bits (Si5367/68/
69).
MCU CPLD Si5367, Si5368
SS_CPLD_B
SCLK
MOSI
MISO
SS_B
SCLK
SDI
SDO
DUT_PWR
+3.3 V

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 7
5.6. Power and 2L Signals
This evaluation board requires two power inputs +3.3 V for the MCU and either 1.8, 2.5, or 3.3 V for the Any-
Frequency Precision Clock part. The power connector is J40. The grounds for the two supplies are tied together on
the EVB. There are sixteen LEDs, as described in Table 3. J14 is a three by 10 pin male header by which the user
can manually set the values of the two-level inputs using jumper plugs connected to either ground (silkscreen
labeled L) or the power supply (labeled H). J8 is a twenty pin ribbon header that brings out all of the status outputs
from the Si536x. Note that some pins are shared and serve as both inputs and outputs, depending on how the
device is configured. For users that wish to remotely access the input and output pins settings with external
hardware, J14 and J8 can be connected to ribbon cables.
5.7. 3L Pins
The three-level inputs can all be manually configured by installing jumper plugs at J17, either H or L. The M level is
achieved by not installing a jumper plug at a given location. J17 can also be used as a connection to an external
circuit that controls these pins. J22 is a ten pin ribbon header that is provided so that an external processor can
control the Si536x over either the SPI or I2C bus.

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
8 Rev. 0.6
6. Connectors and LEDs
6.1. LEDs
There are sixteen LEDs on the board which provide a quick and convenient means of determining board status.
Table 3. LED Status and Description
LED Color Label LED Color Label
D1 green 3.3 V D2 red LOL
D3 green DUT_PWR D4 red C1B
D5 red ALRMOUT D6 red C2B
D7 yellow CPLD_2 D8 red C3B
D9 yellow CPLD_1 D10 green C1A
D11 red MCU_3 D12 green C2A
D13 red MCU_2 D14 green C3A
D15 red MCU_1 D16 green C4A

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 9
6.2. User Jumpers and Headers.
Use Figure 4 to locate the jumpers described in Tables 4, 5, 6, and 7:
Figure 4. Connectors, Jumper Header Locations
J25 assists in measuring the Any-Frequency Precision Clock current draw. If J25 is to be used, R36 should be
removed.
R24, R28, C22 on top;
R50, R51, R52, C39 on bot
J18
Ext Ref, J1, J2
J17
J14
J8
J22
J25, R36
C22
R24, R28, C22 on top;
R50, R51, R52, C39 on bot
J18
Ext Ref, J1, J2
J17
J14
J8
J22
J25, R36
C22

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
10 Rev. 0.6
J14 is a three-pin by ten header that is used to establish input levels for the pin controlled two-level inputs using
jumper plugs. It also provides a means of externally driving the two-level input signals:
J8 is a 20 pin ribbon header that provides an external path to monitor the status pins.
J22 is a 10 pin ribbon header that provides an external path to serially communicate with the Any-Frequency
Precision Clock.
To control the Any-Frequency part that is on the Evaluation Board from an external serial port, open the Register
Programmer, connect to the Evaluation Board, go to Options in the top toolbar and select "Switch To External
Control Mode".
To control an Any-Frequency part that is on an external target board from the Evaluation Board using its serial port,
tie pin 9 of J22 low so that the on-board Any-Frequency part is constantly being held in reset. This will force it to
disable its SDA_SDO output buffer.
Table 4. Two-Level Input Jumper Header, J14
J36 Pin Comment
J14.1B CS0_C3A CS0
J14.2B CS1_C4A CS1
J14.3B INC
J14.4B DEC
J14.5B — not used
J14.6B — not used
J14.7B DSBL34
J14.8B FS_ALIGN
J14.9B FS_SW
J14.10B CK_CONF
Table 5. External Status Connector, J8
J37 Pin Comment
J8.1 LOL
J8.3 C1B
J8.5 C2B
J8.7 C3B
J8.9 C1A
J8.11 C2A
J8.13 CS0_C3A C3A
J8.15 CS1_C4A C4A
J8.17 INT_ALRM
J8.19 DUT_PWR

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 11
J17 is a three-pin by twenty header that is used to establish input levels for the pin controlled three-level inputs
using jumper plugs. It also provides a means of externally driving the three-level input signals.
J18 is used to monitor the Any-Frequency Precision Clock voltage.
J1 and J2 are edge mount SMA connectors that are used, if so configured, to supply an external single-ended or
differential reference oscillator.
Table 6. External Serial Port Connector, J22
J38 Pin Comment
J22.1 SDA_SDO
J22.3 SCL_SCLK
J22.5 SDI
J22.7 A2_SS
J22.9 DUT_RST_B reset
Table 7. Three-Level Input Jumper Headers, J17
J39 Pin Comment
J17.1B CMODE
J17.2B AUTOSEL
J17.3B A0_FRQSEL0
J17.4B A1_FRQSEL1
J17.5B A2_SS_FRQSEL2
J17.6B SDI_FRQSEL3
J17.7B SCL_SCLK_BWSEL0
J17.8B SDA_SDO_BWSEL1
J17.9B FRQTBL
J17.10B DBL2_BY
J17.11B BDBL_FS
J17.12B DIV34_0
J17.13B DIV34_1
J17.14B SFOUT0
J17.15B SFOUT1
J17.16B RATE0
J17.17B RATE1
J17.18B FOS_CTL
J17.19B — not used
J17.20B — not used

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
12 Rev. 0.6
7. EVB Software Installation
The release notes and the procedure for installing the EVB software can be found on the release CD included with
the EVB. These items can also be downloaded from the Silabs web site: www.silabs.com/timing. Follow the links
for 1-PLL Jitter attenuators, and look under the Tools tab.
7.1. Precision Clock EVB Software Description
There are several programs to control the Precision Clock device. Each provides a different kind of access to the
device. Refer to the online help in each program by clicking HelpHelp in the menu for more information on how
to use the software. Note: Some of the Precision Clock devices do not have a register map, so some programs
may not be applicable to them.
Table 8. User Applications
Program Description
Register Viewer The Register Viewer displays the current register map data in a table format sorted by reg-
ister address to provide an overview of the device’s state. This program can save and print
the register map.
Register Programmer The Register Programmer provides low-level register control of the device. Single and
batch operations are provided to read from and write to the device. Register map files can
be saved and opened in the batch mode.
Setting Utility This application allows for quick access to each control on the Precision Clock device
(either pin- or register-based). It can save and open text files as well.
DSPLLsim The DSPLLsim provides high-level control of the Precision Clock device. It has the fre-
quency planning wizard as well as control of the pins and registers in a organized, intuitive
manner.

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 13
8. Schematics
Figure 5. Si536x
DUT_PWR
RATE0 RATE1
DSBL34 INT_ALRM CS0_C3A CS1_C4A C1A C2A C3B C1B C2B SFOUT1 DBL_FS SFOUT0 LOL
AUTOSEL
A0_FRQSEL0
SDA_SDO_BWSEL1
A2_SS_FRQSEL2
A1_FRQSEL1
SDI_FRQSEL3
FRQTBL
CK_CONF
CMODE
INC
FOS_CTL
DEC
DIV34_0 DIV34_1 DBL2_BY
SCL_SCLK_BWSEL0
FS_SW
FS_ALIGN
DUT_RST_B
ExtRefIn+ CKIN1+ CKIN1- CKIN2+ CKIN2- CKIN3+ CKIN3- CKIN4- CKIN4+
CKOUT1+ CKOUT1- CKOUT2+ CKOUT2- CKOUT3+ CKOUT3- CKOUT4- CKOUT4+ FS_OUT+
FS_OUT-
for CMOS output
to measure DUT current
Locate next to U1
See note 1
ExtRefIn-
to power plane
C53100N C53100N
1
3
2
J37
SMA_EDGE
J37
SMA_EDGE
1
3
2
J7
SMA_EDGE
J7
SMA_EDGE
C58100N C58100N
C22
10NF
NOPOP
C22
10NF
NOPOP
C44
100N
C44
100N
R30
0 ohm
NOPOP
R30
0 ohm
NOPOP
C32
100N
C32
100N
C59
10NF
C59
10NF
C55100N C55100N
1
3
2
J39
SMA_EDGE
J39
SMA_EDGE
1
3
2
J3
SMA_EDGE
J3
SMA_EDGE
R500 ohm
NOPOP
R500 ohm
NOPOP
C39
10NF
NOPOP
C39
10NF
NOPOP
C46
10NF
C46
10NF
R54
49.9 R54 49.9
C28
100N
C28
100N
R280 ohm R280 ohm
1
3
2
J30
SMA_EDGE
J30
SMA_EDGE
C48
10NF
C48
10NF
1
3
2
J10
SMA_EDGE
J10
SMA_EDGE
C25
100N
C25
100N
1
3
2
J35
SMA_EDGE
J35
SMA_EDGE
1 2
J18J18
R5349.9 R5349.9
C17 100N C17 100N
R61 49.9 R61 49.9
C54
10NF
C54
10NF
1 3 2 4
GND
X1
114.285 MHz
GND
X1
114.285 MHz
C42100N C42100N
R2449.9 R2449.9
R31
0 ohm
R31
0 ohm
C52 1UF C52 1UF
R57 49.9 R57 49.9
R56 49.9R56 49.9
1
3
2
J1
SMA_EDGE
J1
SMA_EDGE
C29
100N
C29
100N
1
3
2
J23
SMA_EDGE
J23
SMA_EDGE
1
3
2
J15
SMA_EDGE
J15
SMA_EDGE
C56
10NF
C56
10NF
C26
100N
C26
100N
C62 10NF C62 10NF
C24 10NF C24 10NF
C19
100N
C19
100N
1
3
2
J2
SMA_EDGE
J2
SMA_EDGE
C47100N C47100N
R59
49.9 R59 49.9
R29
0 ohm R29 0 ohm
C33
100N
C33
100N
C61100N C61100N
C57
100N
C57
100N
C51
10NF
C51
10NF
C43 10NFC43 10NF
1
3
2
J38
SMA_EDGE
J38
SMA_EDGE
1
3
2
J33
SMA_EDGE
J33
SMA_EDGE
1 2
J25 NOPOP J25 NOPOP
R36 0 ohm R36 0 ohm
1
3
2
J41
SMA_EDGE
J41
SMA_EDGE
1
3
2
J21
SMA_EDGE
J21
SMA_EDGE
1 2
L2 Ferrite L2 Ferrite
C60
100N
C60
100N
C40
100N
C40
100N
R5249.9 R5249.9
1
3
2
J36
SMA_EDGE
J36
SMA_EDGE
C3
100N
C3
100N
R60
49.9 R60 49.9
C2
100N
C2
100N
1
3
2
J13
SMA_EDGE
J13
SMA_EDGE
C41
10NF
C41
10NF
R55 49.9 R55 49.9
Vdd1 5
Vdd2 6
Vdd3 15
Vdd4 27
Vdd5 62
Vdd6 63
Vdd7 76
Vdd9 81
Vdd8 79
Vdd10 84
Vdd11 86
Vdd12 89
Vdd13 91
Vdd14 94
Vdd15 96
Vdd16 99
Vdd17 100
Gnd1
7
Gnd2
8
Gnd3
14
Gnd4
18
Gnd5
19
Gnd6
26
Gnd7
28
Gnd8
31
Gnd9
33
Gnd10
36
Gnd11
38
Gnd12
41
Gnd13
43
Gnd14
46
Gnd15
64
Gnd16
65
Gnd_Slug
101
NC1 1 NC2 2 NC3 23 NC4 24 NC5 25 NC6 52 NC7 53 NC8 72 NC9 73
NC10 74 NC11 75
CKIN1+
44
CKIN1-
45
CKIN2+
34
CKIN2-
35
CKIN3+
39
CKIN3-
40
CKIN4+
29
CKIN4-
30
CKOUT1+ 83
CKOUT1- 82
CKOUT2+ 92
CKOUT2- 93
CKOUT3+ 77
CKOUT3- 78
CKOUT4+ 98
CKOUT4- 97
FS_OUT+ 88
FS_OUT- 87
SFOUT0 95 SFOUT1 80
LOL 49
C1B 9 C2B 10 C3B 11
ALRMOUT 12
RSTB
3
XA
16
XB
17
RATE0 32
RATE1 42
INC
55
DEC
54
FRQSEL3_SDI
71
FRQSEL2_A2_SS
70
FRQSEL1_A1
69
FRQSEL0_A0
68
AUTOSEL
22
CS0_C3A 13
DIV34_0
66 DIV34_1 67
CS1_C4A 57
SCL_SCLK_BWSWL0
60 SDA_SDO_BWSEL1
61
DSBL34 85
DBL2_BY
37
FS_SW
20
FS_ALIGN
21
DBL_FS 50
CK_CONF
51
CMODE
90
FOS_CTL
56
NC13
47
NC12
48
FRQTBL
4
C1A 58 C2A 59
U6
Si536x
U6
Si536x
1
3
2
J5
SMA_EDGE
J5
SMA_EDGE
1
3
2
J28
SMA_EDGE
J28
SMA_EDGE
C27
100N
C27
100N
C45100N C45100N
C49
100N
C49
100N
R51100
NOPOP
R51100
NOPOP
1
3
2
J29
SMA_EDGE
J29
SMA_EDGE
C50100N C50100N
Notes:
1. Change for Si5365, Si5367, and External Reference.

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
14 Rev. 0.6
TMS TDO TCK VCCAUX TDI
V1P8
V3P3
DUT_PWR V3P3
REG_ADR0 REG_ADR1 REG_ADR2 REG_ADR3 SS_CPLD_B MOSI SCLK
MISO CPLD_IRQ
REG_ADR4
CPLD_LED2 CPLD_LED1 CPLD_LED0
MCU_SPARE1
CPLD_RST_B
CPLD_LED3 CPLD_LED4 CPLD_LED5 CPLD_LED6 CPLD_LED7 CPLD_LED8 CPLD_LED9
MCU_SPARE2
LOL
A0_FRQSEL0 A1_FRQSEL1
A2_SS_FRQSEL2
SDI_FRQSEL3
SCL_SCLK_BWSEL0
SDA_SDO_BWSEL1
DUT_RST_B
CMODE
INT_ALRM
RATE0 RATE1
CK_CONF FOS_CTL
DBL2_BY DSBL34
AUTOSEL
FRQTBL SFOUT0 SFOUT1
C1A C2A
CS0_C3A CS1_C4A
DIV34_0 DIV34_1
FS_ALIGN
FS_SW
DBL_FS
INC DEC C1B C2B C3B
CPLD_LED10 CPLD_SPARE4 CPLD_SPARE5 CPLD_SPARE6 CPLD_SPARE7 CPLD_SPARE8 CPLD_SPARE9 CPLD_SPARE10 CPLD_SPARE11 CPLD_SPARE12 CPLD_SPARE13 CPLD_SPARE14 CPLD_SPARE1 CPLD_SPARE2 CPLD_SPARE15 CPLD_SPARE16
DUT_PWR +3.3V
JTAG connector
1.8V
C8
1UF
C8
1UF
FN5_M4_GCK1 23 FN5_M6_GCK0 22
FN6_M2_CDRST 24
FN6_M4_GCK2 27 FN6_M12_DGE 28
FN6_M14 29 FN6_M16 30
FN7_M5 19 FN7_M6 18
FN7_M11 17 FN7_M12 16 FN7_M13 15 FN7_M14 14
FN8_M6 32
FN8_M11 33 FN8_M12 34 FN8_M13 35 FN8_M14 36 FN8_M15 37 FN13_M2 53 FN13_M4 54 FN13_M6 55
FN13_M13 56
FN14_M1 52 FN14_M3 50 FN14_M5 49
FN14_M14 46 FN14_M15 44 FN15_M11 58 FN15_M12 59 FN15_M13 60 FN15_M14 61 FN15_M15 63 FN15_M16 64
FN16_M5 43 FN16_M6 42
FN16_M11 41 FN16_M12 40 FN16_M13 39
FN1_M3_GSR
99
FN1_M6
97
FN1_M12
96
FN1_M13
95
FN1_M14
94
FN2_M1_GTS2
1
FN2_M3_GTS3
2
FN2_M5_GTS0
3
FN2_M12_GTS1
4
FN2_M14
6
FN2_M15
7
FN3_M5
93
FN3_M12
92
FN3_M14
91
FN3_M16
90
FN4_M1
8
FN4_M2
9
FN4_M3
10
FN4_M5
11
FN4_M6
12
FN4_M13
13
FN9_M1
78
FN9_M2
79
FN9_M4
80
FN9_M6
81
FN9_M12
82
FN10_M1
77
FN10_M2
76
FN10_M3
74
FN10_M4
73
FN10_M5
72
FN10_M6
71
FN10_M12
70
FN11_M11
85
FN11_M12
86
FN11_M13
87
FN11_M14
89
FN12_M11
68
FN12_M13
67
FN12_M14
66
FN12_M15
65
Bank 1Bank 2
U10C
XC2C128
Bank 1Bank 2
U10C
XC2C128
R16 66.5 R16 66.5
C11 10NF C11 10NF
C20 10NF C20 10NF
In
1
Gnd
2
EN
3
FB 4
Out 5
Vreg
U4
TPS76201
Vreg
U4
TPS76201
C14 1UF C14 1UF
C13 10NF C13 10NF
C23 1UF C23 1UF
R18 0 ohm NOPOP R18 0 ohm NOPOP
R2110k R2110k
1 2 3 4 5 6
J32 SMT J32 SMT
C21 100N C21 100N
C9 1UF C9 1UF
+
C7 33UF
+
C7 33UF
R19 0 ohm R19 0 ohm
GND1 21 GND2 25 GND3 31 GND4 62 GND5 69 GND7 84 GND8 100 GND6 75
VCC1
26
VCC2
57
VCCIO1-1
20
VCCIO1-2
38
VCCIO1-3
51
VCCIO2-1
88
VCCIO2-2
98
U10A
XC2C128
U10A
XC2C128
C15 10NF C15 10NF
TCK
48
TDI
45
TDO
83
TMS
47
VCCAUX
5
U10B
XC2C128
U10B
XC2C128
C12 100N C12 100N
C10 100N C10 100N
R2310k R2310k
R20 0 ohm NOPOP R20 0 ohm NOPOP
C18 10NF C18 10NF
R1010 R1010
R15
0 ohm
R15
0 ohm
R14
10 R14 10
R45 113 R45 113
C16 10NF C16 10NF
Figure 6. CPLD

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 15
EVB_SER_NUM
VBUS
V3P3
V3P3
V3P3
V3P3
V3P3
SS_CPLD_B
MISO
SCLK
CPLD_IRQ
MOSI
MCU_SPARE1 MCU_SPARE2
REG_ADR0 REG_ADR1 REG_ADR2 REG_ADR3 REG_ADR4 MCU_LED1 MCU_LED2
CPLD_RST_B
MCU_LED3
CPLD_SPARE1 CPLD_SPARE2 CPLD_SPARE4 CPLD_SPARE5 CPLD_SPARE6 CPLD_SPARE7 CPLD_SPARE8 CPLD_SPARE9 CPLD_SPARE10
CPLD_SPARE11 CPLD_SPARE12 CPLD_SPARE13 CPLD_SPARE14 CPLD_SPARE15 CPLD_SPARE16
USB
serial number
Install 1.5K pullups
for I2C operation. On MCU: P0.0 = SDA P0.1 = SCL
MCU debug
reset
Spares
R12
10k
R12
10k
C4
1UF
C4
1UF
Vdd 10
GND
7
RST/C2CK 13
C2D 14
REGIN 11
VBUS 12
D+ 8
D- 9
P0.0
6
P0.1
5
P0.2
4
P0.3
3
P0.4
2
P0.5
1
P0.6
48
P0.7
47
P1.0
46
P1.1
45
P1.2
44
P1.3
43
P1.4
42
P1.5
41
P1.6
40
P1.7
39
P3.7 23 P3.6 24 P3.5 25 P3.4 26 P3.3 27 P3.2 28 P3.1 29 P3.0 30
P2.0
38
P2.1
37
P2.2
36
P2.3
35
P2.4
34
P2.5
33
P2.6
32
P2.7
31
P4.7 15 P4.6 16 P4.5 17 P4.4 18 P4.3 19 P4.2 20 P4.1 21 P4.0 22
C8051-
F340
U9
Si8051F340
C8051-
F340
U9
Si8051F340
R38
0 ohm
R38
0 ohm
C5
100N
C5
100N
R40
1K R40 1K
R44 1K R44 1K
R4 10k R4 10k
1 2
4 3
SW1
NO
SW1
NO
R127.4 R127.4
R1749.9 R1749.9
C37
100N
C37
100N
R8
10 R8 10
R9 10k R9 10k
R310k R310k
NC1 1
NC2 3
Gnd1 2 Gnd2
5
A
6
B
4
USB Clamp
U2
SN65220
USB Clamp
U2
SN65220
R46
10k
R46
10k
R13 1.5K NOPOP R13 1.5K NOPOP
R4149.9 R4149.9
R39
10 R39 10
12 34 56 78 910
J31
10_M_Header_SMT
J31
10_M_Header_SMT
R749.9 R749.9
V1
Gnd 4
D-
2
D+
3
S1
5
S2
6
J6 USB J6 USB
R5
1K R5 1K
C1
100N
C1
100N
Vcc 6 GND
1
I/O
2NC1 3
NC2 4 NC3 5
Ser No.
U3
DS2411
Ser No.
U3
DS2411
R1149.9 R1149.9
C6
1UF
C6
1UF
Vcc 8 Vss
4
CS 1
W3
Clk 6
D5
HOLD 7
Q
2
EEPROM
U5
M95040
EEPROM
U5
M95040
R42
49.9
R42
49.9
R37 1K R37 1K
12
34
56
78
910
J34
10_M_Header_SMT BOM = NOPOP
J34
10_M_Header_SMT BOM = NOPOP
R43
1K
NOPOP
R43
1K
NOPOP
C36 100N C36 100N
R2
27.4 R2 27.4
NC1 1
NC2 3
Gnd1 2 Gnd2
5
A
6
B
4
USB Clamp
U1
SN65220
USB Clamp
U1
SN65220
C38 100N C38 100N
Figure 7. MCU

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
16 Rev. 0.6
V3P3_LED
V3P3
DUT_PWR
DUT_PWR
DUT_PWR
DUT_PWR
CPLD_LED0 MCU_LED1 MCU_LED2 MCU_LED3 CPLD_LED1 CPLD_LED2
CPLD_LED3 CPLD_LED4 CPLD_LED5 CPLD_LED6 CPLD_LED7 CPLD_LED8 CPLD_LED9
FS_SW
FS_ALIGN
DSBL34
CK_CONF CS0_C3A
DEC INC
CS1_C4A
C1A C2A
INT_ALRM
C1B C2B C3B
LOL
CPLD_LED10
EVB main power
3.3V
3.3Vreturn
DUT_PWR
DUT_PWRreturn
+3.3V
ground pins
mounting holes
two level inputs
status
C4A C3A
C2A C1A C3B C2B C1B LOL +3.3V DUT_PWR INT_ALRM CPLD_1 MCU_1 MCU_2 MCU_3 CPLD_2
12
A
C
D7 Yel
A
C
D7 Yel
R730 ohm R730 ohm
R65 10k R65 10k
12
A
C
D5 Red
A
C
D5 Red
R27 100R27 100
18 27 36 45
R33R150x4 R33R150x4
1
J11J11
12
A
C
D12 Grn
A
C
D12 Grn
1
J19J19
12
A
C
D4 Red
A
C
D4 Red
1 2
L1
Ferrite
L1
Ferrite
1
J20J20
R71
1K
R71
1K
R48
0 ohm R48 0 ohm
R69
1K
R69
1K
1
H3
#4
H3
#4
1 2 3 4
* * * *
J40
Phoenix_4_screw
* * * *
J40
Phoenix_4_screw
1
2 3
Q1
BSS138
Q1
BSS138
1 2
J27
BOM = NOPOP
J27
BOM = NOPOP
+
C35 330UF
+
C35 330UF
18 27 36 45
R35R150x4 R35R150x4
18 27 36 45
R34R150x4 R34R150x4
12
A
C
D14 Grn
A
C
D14 Grn
1
J24J24
R66 10k R66 10k
+
C31 33UF
+
C31 33UF
12
A
C
D6 Red
A
C
D6 Red
12
A
C
D13 Red
A
C
D13 Red
1 8 2 7 3 6 4 5
R47R82x4 R47R82x4
1
H2
#4
H2
#4
+
C30
33UF
+
C30
33UF
1
J12J12
R49
82.5 R49 82.5
1
J26J26
12
A
C
D11 Red
A
C
D11 Red
1 8 2 7 3 6 4 5
R6R82x4 R6R82x4
12
A
C
D16 Grn
A
C
D16 Grn
12
A
C
D3 Grn
A
C
D3 Grn
R6310k R6310k
12
A
C
D8 Red
A
C
D8 Red
1
H4
#4
H4
#4
12 34 56 78 910 1112 1314 1516 1718 1920
J8
20_M_Header_SMT
J8
20_M_Header_SMT
IN7
9IN6 8IN5 7IN4 6IN3 5IN2 4IN1 3IN0 2
O7 11 O6 12 O5 13 O4 14 Q3 15 O2 16 O1 17 O0 18
Vcc 20
GND
10
OE1
1
OE2
19
Buffer
U7
74LCX541
Buffer
U7
74LCX541
1
J4J4
12
A
C
D1 Grn
A
C
D1 Grn
+
C34
330UF
+
C34
330UF
1
H1
#4
H1
#4
8A 8B
7C
9A 9B
8C
10A 10B
9C 5C5A 6C
6B 6A 7B 5B 7A 1A 2A 1B 3B
4C 1C
3A 3C
2C
2B
10C
4A 4B
J14
10x3_M_HDR_SMT
J14
10x3_M_HDR_SMT
12
A
C
D9 Yel
A
C
D9 Yel
R68 10kR68 10k
12
A
C
D10 Grn
A
C
D10 Grn
IN7
9IN6 8IN5 7IN4 6IN3 5IN2 4IN1 3IN0 2
O7 11 O6 12 O5 13 O4 14 Q3 15 O2 16 O1 17 O0 18
Vcc 20
GND
10
OE1
1
OE2
19
Buffer
U8
74LCX541
Buffer
U8
74LCX541
1
J9J9
1
J16J16
12
A
C
D15 Red
A
C
D15 Red
12
A
C
D2 Red
A
C
D2 Red
18 27 36 45
R32R150x4 R32R150x4
Figure 8. Power, LEDs and 2L Inputs

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 17
DUT_PWR
DUT_PWR
DUT_PWR
FRQTBL AUTOSEL SFOUT1
RATE1
FOS_CTL
RATE0
DBL_FS DBL2_BY
SDA_SDO_BWSEL1
A0_FRQSEL0
SFOUT0
SCL_SCLK_BWSEL0
SDI_FRQSEL3
DIV34_1
A2_SS_FRQSEL2
DIV34_0 CMODE
A1_FRQSEL1
DUT_RST_B
three level inputs
SPI, I2C port
install for I2C
see note 2
8A 8B
7C
9A 9B
8C
10A 10B
9C 5C5A 6C
6B 6A 7B 5B 7A 1A 2A 1B 3B
4C 1C
3A 3C
2C
2B
15A 13B 16A 16B 17B 17A
16C 13C 11C
12A 11A 14B 15B
17C 10C
11B 14A
15C
13A 12B
12C 14C
4A 4B
19B
18C
20B 19A 19C 18B
20C20A
18A
J17
20x3_M_HDR_SMT
J17
20x3_M_HDR_SMT
R22
1.5K
NOPOP
R22
1.5K
NOPOP
R2610 R2610
12 34 56 78 910
J22
10_M_Header_SMT
J22
10_M_Header_SMT
R7210k R7210k
R620 ohm
NOPOP
R620 ohm
NOPOP
R7010k R7010k
R640 ohm
NOPOP
R640 ohm
NOPOP
18
27
36
45
R67
R82x4
R67
R82x4
R58 100 R58 100
R25
1.5K NOPOP
R25
1.5K NOPOP
Notes:
2. NOPOP for Si5365 and Si55366.
Figure 9. Serial Port, 3L Inputs

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
18 Rev. 0.6
9. Bill of Materials
Table 9. Si536x Bill of Materials
Item Qty Reference Part Mfgr MfgrPartNum
1 32 C1,C2,C3,C5,C10,C12,C17,C19,C21
,C25,C26,C27,C28,C29,C32,C33,C3
6,C37,C38,C40,C42,C44,C45,C47,C
49,C50,C53,C55,C57,C58,C60,C61
100 N Venkel C0603X7R160-104KNE
2 7 C4,C6,C8,C9,C14,C23,C52 1 UF Venkel C0603X7R6R3-
105KNE
3 3 C7,C30,C31 33 UF Venkel TA0006TCM336MBR
4 16 C11,C13,C15,C16,C18,C20,C24,C41
,C43,C46,C48,C51,C54,C56,C59,C6
2
10 NF Venkel C0603X7R160-103KNE
6 2 C34,C35 330 UF Panasonic EEE-HA0J331XP
7 6 D1,D3,D10,D12,D14,D16 Grn Lumex SML-LXT0805GW-TR
8 8 D2,D4,D5,D6,D8,D11,D13,D15 Red Lumex SML-LXT0805SRW-TR
9 2 D7,D9 Yel Lumex SML-LXT0805YW-TR
10 4 H1,H2,H3,H4 #4 mounting hole
11 20 J1,J2,J3,J5,J7,J10,J13,J15,J21,J23,
J28,J29,J30,J33,J35,J36,J37,J38,J3
9,J41
SMA_EDGE Johnson 142-0701-801
12 9 J4,J9,J11,J12,J16,J19,J20,J24,J26 Jmpr_1pin
13 1 J6 USB FCI 61729-0010BLF
14 1 J8 20_M_Header_SMT Samtec HTST-110-01-lm-dv-a
15 1 J14 10x3_M_HDR_SMT Samtec TSM-110-01-L-TV
16 1 J17 20x3_M_HDR_SMT Samtec TSM-120-01-L-TV
17 1 J18 Jmpr_2pin
18 1 J22 10_M_Header_SMT Samtec HTST-105-01-lm-dv-a
20 1 J31 10_M_Header_SMT Samtec HTST-105-01-lm-dv-a
21 1 J32 SMT Sullins GZC36SABN-M30
23 1 J40 Phoenix_4_screw Phoenix MKDSN 1.5/4-5.08
24 2 L1,L2 Ferrite Venkel FBC1206-471H
25 1 Q1 BSS138 On Semi BSS138LT1G
26 2 R1,R2 27.4 Venkel CR0603-16W-27R4FT
27 13 R3,R4,R9,R12,R21,R23,R46,R63,
R65,R66,R68,R70,R72 10 k Venkel CR603-16W-1002FT
28 6 R5,R37,R40,R44,R69,R71 1 K Venkel CR0603-16W-1001FT
29 3 R6,R47,R67 R82x4 Panasonic EXB-38V820JV
30 15 R7,R11,R17,R24,R41,R42,R52,R53,
R54,R55,R56,R57,R59,R60,R61 49.9 Venkel CR0603-16W-49R9FT
Table 9. Si536x Bill of Materials (Continued)
Item Qty Reference Part Mfgr MfgrPartNum

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
Rev. 0.6 19
33 9 R15,R19,R28,R29,R31,R36,R38,
R48,R73 0 ohm Venkel CR0603-16W-000T
34 1 R16 66.5 Venkel CR0603-16W-66R5FT
36 2 R27,R58 100 Venkel CR0603-16W-1000FT
37 4 R32,R33,R34,R35 R150x4 Panasonic EXB-38V151JV
39 1 R45 113 Venkel CR0603-16W-1130FT
40 1 R49 82.5 Venkel CR0603-16W-82R5FT
42 1 SW1 NO Mountain Switch 101-0161-EV
43 2 U1,U2 SN65220 TI SN65220DBVT
44 1 U3 DS2411 Maxim/Dallas DS2411P
45 1 U4 TPS76201 TI TPS76201DBVT
46 1 U5 M95040 ST Micro M95040-WMN6P
47 1 U6 Si5368A-X-GQ* Silicon Labs Si5368A-X-GQ
48 2 U7,U8 74LCX541 Fairchild 74LCX541MTC_NL
49 1 U9 Si8051F340 Silicon Labs C8051F340-GQ
50 1 U10 XC2C128 Xilinx XC2C128-7VQG100I
51 1 X1 for Si5365/66-EVB and
Si5367/68-EVB 114.285 MHz TXC 7MA1400014
51 1 X1 for the Si5369-EVB 114.285 MHz, 20 ppm NDK EX500A-C500997
Not Populated
5 2 C22,C39 10 NF Venkel C0603X7R160-103KNE
19 2 J25,J27 Jmpr_2pin
22 1 J34 10_M_Header_SMT Samtec HTST-105-01-lm-dv-a
32 3 R13,R22,R25 1.5 K Venkel CR0603-16W-1501FT
35 6 R18,R20,R30,R50,R62,R64 0 ohm Venkel CR0603-16W-000T
38 1 R43 1 K Venkel CR0603-16W-1001FT
41 1 R51 100 Venkel CR0603-16W-1000FT
*Note: X denotes the product revision. Consult the ordering guide in the Si5368 Data Sheet for the latest product revision.
For the Si5365/66-EVB, substitute Si5366-C-GQ. For the Si5369-EVB, substitute Si5369A-C-GQ.
Table 9. Si536x Bill of Materials (Continued)
Item Qty Reference Part Mfgr MfgrPartNum

Si5365/66-EVB Si5367/68-EVB Si5369-EVB
20 Rev. 0.6
10. Layout
Figure 10. Silkscreen Top
Figure 11. Layer 1