SMC Networks SMC91C95 User manual

SMC91C95
PRELIMINARY
ISA/PCMCIA Full Duplex Single-Chip
Ethernet and Modem Controller with RAM
FEATURES
• ISA/PCMCIA Single Chip Ethernet Controller
With Modem Support
• 6 Kbytes Built-In RAM
• Supports IEEE 802.3 (ANSI 8802-3) Ethernet
Standards
• Full Duplex Support
• Hardware Memory Management Unit
• Built-In AUI and 10BASE-T Network
Interfaces
• Simultasking - Early Transmit and Early
Receive Functions
• Advanced Power Management
Features/Including Magic Packet Frame
Control
• Software Compatible with SMC91C92/
SMC91C94 (in ISA Mode)
• Configuration Registers Implement Cardbus
Multi-Function Specification V3.0 with
Backward Compatibility to V2.1
• Interfaces Directly to Lucent Technologies and
Rockwell International Modem Chipsets
• On-Chip Attribute Memory (CIS) of up to 512
Bytes (On Even Addresses) For Card
Configuration Information; Expandable
Externally
• Option for Serial or Parallel EEPROM for CIS
• Optional External Flash Capability for XIP
(Execute in Place)
• Automatic Technology to Detect TX/RX
10BASE-T Tranceiver Pair Miswiring
• Low Power CMOS Design
• Supports Magic Packet Wakeup
• 128 Pin VTQFP Package
Bus Interface
• Direct Interface to ISA and PCMCIA with
No Wait States
• High Impedance Speaker Interface
• Flexible Bus Interface
• 16-Bit Data and Control Paths
• Fast Access Time (40 ns)
• Pipelined Data Path
• Handles Block Word Transfers for Any
Alignment
• High Performance Chained ("Back-to-
Back") Transmit and Receive
• Flat Memory Structure for Low CPU
Overhead
• Dynamic Memory Allocation Between
Transmit and Receive
• Buffered Architecture, Insensitive to Bus
Latencies (No Overruns/Underruns)
• Supports Boot PROM for Diskless ISA
Applications
Simultasking is a trademark and SMC is a registered trademark of Standard Microsystems Corporation

2
TABLE OF CONTENTS
FEATURES.......................................................................................................................................................1
PIN CONFIGURATION....................................................................................................................................3
GENERAL DESCRIPTION...............................................................................................................................4
OVERVIEW ......................................................................................................................................................4
PIN REQUIREMENTS......................................................................................................................................7
DESCRIPTION OF PIN FUNCTIONS..............................................................................................................9
BUFFERTYPES........................................................................................................................................... 17
FUNCTIONAL DESCRIPTION.......................................................................................................................21
INTERRUPT STRUCTURE............................................................................................................................32
RESET LOGIC.............................................................................................................................................. 33
POWERDOWN LOGIC................................................................................................................................ 34
PCMCIA ATTRIBUTE MEMORY: ADDRESS 0- 7FFEH............................................................................................ 35
PCMCIA CONFIGURATIONREGISTERS: ADDRESS 8000-803EH............................................................................. 35
INTERNAL VS EXTERNAL ATTRIBUTE MEMORY MAP.................................................................................................. 36
THEORY OF OPERATION............................................................................................................................69
“MAGIC PACKET” SUPPORT.................................................................................................................................. 70
INTERNAL VS. EXTERNAL ATTRIBUTE MEMORY MAP........................................................................ 80
PCMCIA CONFIGURATION REGISTERS DESCRIPTION....................................................................... 82
FUNCTIONAL DESCRIPTION OF THE BLOCKS...................................................................................... 91
BOARD SETUP INFORMATION............................................................................................................... 100
OPERATIONAL DESCRIPTION..................................................................................................................104
TIMING DIAGRAMS ....................................................................................................................................108
Related Documentation
1. PCMCIA 2.1 Standard (for PCMCIA timing and functionality)
2. PCMCIA 3.X spec (for multi-function extensions)
3. AT&T HSM288xCF Modem Chip Set Data Sheet - July 5, 1994
4. Rockwell RC224ATF and C39 Modem Chip Sets Designer’s Guide

3
Network Interface
• Integrates 10BASE-T Transceiver
Functions:
-Driver and Receiver
-Link Integrity Test
-Receive Polarity Detection and
Correction
• Integrates AUI Interface
• Implements 10 Mbps Manchester
Encoding/Decoding and Clock Recovery
• Automatic Retransmission, Bad Packet
Rejection, and Transmit Padding
• External and Internal Loopback Modes
• Four Direct Driven LEDs for Status/
Diagnostics
Software Drivers
• Uses Certified SMC9000 Drivers Which
Operate with Every Major Network
Operating System
• Software Driver Compatible with
SMC91C92, SMC91C94 and SMC91C100
(100 Mbps) Controllers in ISA Mode
• Software Driver Utilizes Full Capability of
32 Bit Microprocessor
PIN CONFIGURATION
AVDD
TXP/nCOLL
TXN/nCRS
TPETXP
TEPTXDP
TPETXN
TPETXDN
AVSS
nTXLED/nTXEN
nRXLED/RXCLK
nLINKLED/TXD
nBSELED/RXD
VDD
SPKRIN
SPKROUT
nMIS16
MRDY
MINT
VSS
MRINGIN
nMRINGOA
MRINGOB
nMCS
nMRESET
VDD
MIDLEN1
nMPWDN
nMPDOUT
MFBK1
VSS
NC
ND
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
NC AVSS COLN COLP RECN RECP TPERXN TPERXP AVDD AVSS RBIAS AVDD nXENDEC nEN16 PWRDWN/TXCLK nROM/nPCMCIA VSS ENEEP EESK EECS EEDO/SDOUT EEDI IOS2 IOS1 VDD IOS0 XTAL2 XTAL1 WAKEUP nWAKEUP_EN RESET NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
NC
NC
VSS
INTR3
INTR2/nSTSCHG
INTR1/nINPACK
INTR0/nIREQ
VDD
nIORD
nIOWR
nMEMR/nOE
nIOSC16/nIOIS16
VSS
IOCHRDY/nWAIT
BALE/nWE
nSBHE/nCE2
VDD
D15
D14
D13
D12
VSS
D11
D10
D9
VDD
D8
D7
D6
VSS
D5
D4
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97
SMC91C95
128 Pin VTQFP
NC
AEN/nREG
A0 A1
VDD
A2 A3 A4 A5 A6 A7
VSS
A8 A9
A10 A11 A12 A13
VDD
A14 A15
A16/nFWE
A17/nFCS
A18
A19/nCE1
VSS
D0 D1 D2
VDD
D3
NC

4
GENERAL DESCRIPTION
The SMC91C95 is a VLSI Ethernet Controller
that combines ISA and PCMCIA interfaces, as
well as an interface to a companion modem
chip set, in one chip. The SMC91C95
integrates all the MAC and physical layer
functions as well as the packet RAM needed to
implement a high performance 10BASE-T
(twisted pair) node. For 10BASE5 (thick coax),
10BASE2 (thin coax), and 10BASE-F (fiber)
implementations, the SMC91C95 interfaces to
external transceivers via its AUI port. Only one
additional IC is required on most applications.
The SMC91C95 occupies 16 I/O locations and
no memory space except for PCMCIA attribute
memory space. The same I/O space is used for
both ISA and PCMCIA operations. The
SMC91C95 can directly interface the ISA and
PCMCIA buses and deliver no wait state
operation. Its shared memory is sequentially
accessed with 40ns access times to any of its
registers, including its packet memory. No
DMA services are used by the SMC91C95;
virtually decoupling network traffic from local or
system bus utilization. For packet memory
management, the SMC91C95 integrates a
unique hardware Memory Management Unit
(MMU) with enhanced performance and
decreased software overhead when compared
to ring buffer and linked list architectures. The
SMC91C95 is portable to different CPU and bus
platforms due to its flexible bus interface, flat
memory structure (no pointers), and its loosely
coupled buffered architecture (not sensitive to
latency).
The SMC91C95 interfaces directly with
Rockwell International L39/C39 controller-based
modems and Lucent Technologies’
HSM288xCF modem.
OVERVIEW
A unique architecture allows the SMC91C95 to
combine high performance, flexibility, high
integration and simple software interface.
The SMC91C95 incorporates the SMC91C92/4
functionality for ISA environments with several
new features, as well as a PCMCIA interface
and attribute registers that comply with the
PCMCIA Multi-Function specification. Mode
selection between ISA and PCMCIA is static
and is done only once at the end of power on
reset. The SMC91C95 consists of the same
logical I/O register structure in ISA and
PCMCIA modes. However, some of the signals
used to access the PCMCIA differ from the ISA
mode. Additional registers exist in the PCMCIA
attribute space. The ROM memory space only
exists in ISA mode and the attribute space only
exists in PCMCIA mode.
I/O decoders are included in the SMC91C95’s
PCMCIA interface, with independent decoders
for the LAN and for the modem functions.
These decoders are used whenever the
SMC91C95 is used as a multi-function card,
and they can be bypassed when only one
function is enabled. The SMC91C95 also
merges the LAN’s internal interrupt source with
the external modem interrupt connected to the
SMC91C95.
The MMU (Memory Management Unit)
architecture used by the SMC91C95 combines
the simplicity and low overhead of fixed areas
with the flexibility of linked lists providing
improved performance over other methods.
The SMC91C95 is designed to support full
duplex switched Ethernet where transmit and

5
receive are fully independent. It has 6 kbytes of
internal memory and the MMU manages
memory in 256 byte pages. The memory size
accommodates the increase in interrupt latency
resulting from simultaneous LAN and modem
operation as well as the potential for
simultaneous transmit and receive traffice in
some full duplex applications.
Packet reception and transmission are
determined by memory availability. All other
resources are always available if memory is
available. To complement this flexible
architecture, all ISA bus interface functions are
incorporated in the SMC91C95, as well as a
4608 byte packet RAM and serial EEPROM-
based setup. The user can select or modify
configuration choices.
The SMC91C95 stores the Configuration
Information Structure (CIS) on reset or power-
up from the serial EEPROM. This allows the
host to access data to allow the setup of the
PCMCIA multi-function card.
In ISA mode, the serial EEPROM acts as
storage for configuration and IEEE Ethernet
address information compatible with the existing
SMC9000 family of ISA Ethernet controllers.
In PCMCIA mode, the serial EEPROM stores
the CIS, as well as the IEEE address,
information, but it does not store any I/O or IRQ
information since this information is handled by
the host’s socket controller. For CIS
requirements above 512 bytes, an optional
external parallel EEPROM can be used in
conjunction with the internal CIS. This allows
additional external, non-volatile storage for
applications that require XIP and use the
modem function. If the serial EEPROM is not
used in PCMCIA mode, the parallel EEPROM
must be used. In this case, the parallel
EEPROM is selected for the first 512 bytes of
storage as well, allowing the CIS to be stored in
the parallel EEPROM and, on power-up, to be
read directly by the host. The remaining
parallel EEPROM can be used for XIP
applications, if needed.
The SMC91C95 integrates most of the 802.3
functionality, incorporating the MAC layer
protocol, the physical layer encoding and
decoding functions with the ability to handle the
AUI interface. For twisted pair networks, the
SMC91C95 integrates the twisted pair
transceiver as well as the link integrity test
functions.
The SMC91C95 is a true 10BASE-T single chip
able to interface a system or a local bus.
Directly-driven LEDs for installation and run-
time diagnostics are provided, as well as 802.3
statistics gathering to facilitate network
management.
The SMC91C95 offers:
High integration:
Single chip adapter including:
Packet RAM
ISA bus interface
PCMCIA interface
EEPROM interface
Encoder decoder with AUI interface
Full duplex, magic packet 10BASE-T
transceiver
Lucent Technologies and Rockwell
International modem interface
High performance:
Chained (“back-to-back”) packet handling
with no CPU intervention:
Queues transmit packets
Queues receive packets
Full duplex operation for higher
network throughput
Stores results in memory along with
packet
Queues Ethernet and modem
interrupts
Optional single interrupt upon
completion of transmit chain

6
Fast block move operation for load/unload:
CPU sees packet bytes as if stored
contiguously
Handles 16 bit transfers regardless of
address alignment
Access to packet through fixed window
Fast bus interface:
Compatible with ISA type and faster buses
Flexibility:
Flexible packet and header processing:
Can be set to Simultasking - Early
Receive and transmit modes
Can access any byte in the packet
Can immediately remove undesired
packets from queue
Can move packets from receive to
transmit queue
Can alter receive processing order
without copying data
Can discard or enqueue again a failed
transmission
Resource allocation:
Memory dynamically allocated for transmit
and receive
Can automatically release memory on
successful transmission
Configuration:
ISA:Uses non-volatile jumperless setup via
serial EEPROM
PCMCIA:
Uses serial EEPROM for attribute
memory storage. PCMCIA I/O ignores
address lines A4-A15 and relies on the
PCMCIA host, decoding for the slot
nROM/nPCMCIA on the SMC91C95 is left
open with a pullup for ISA mode. This pin
is sampled at the end of Power On Reset.
If found low, the SMC91C95 is configured
for PCMCIA mode.

7
PIN REQUIREMENTS
FUNCTION ISA PCMCIA NUMBER OF
PINS
SYSTEM ADDRESS BUS A0-A15
A16
A17
A18
A19
AEN
A0-A15
nFWE
nFCS
nCE1
nREG
21
SYSTEM DATA BUS D0-D15 D0-D15 16
SYSTEM CONTROL BUS RESET
BALE
nIORD
nIOWR
nMEMR
IOCHRDY
nIOCS16
nSBHE
INTR0
INTR1
INTR2
INTR3
RESET
nWE
nIORD
nIOWR
nOE
nWAIT
nIOIS16
nCE2
nIREQ
nINPACK
nSTSCHG
12
MODEM INTERFACE nMRESET
MINT
nMCS
MRDY
nMPWDN
MIDLEN1
MRINGIN
nMRINGOA
MRINGOB
SPKRIN
SPKROUT
nMPDOUT
MFBK1
nMIS16
nMRESET
MINT
nMCS
MRDY
nMPWDN
MIDLEN1
MRINGIN
nMRINGOA
MRINGOB
SPKRIN
SPKROUT
nMPDOUT
MFBK1
nMIS16
14
SERIAL EEPROM EEDI
EEDO
EECS
EESK
ENEEP
IOS0
IOS1
IOS2
EEDI
EEDO
EECS
EESK
ENEEP
IOS0
IOS1
IOS2
8

8
FUNCTION ISA PCMCIA NUMBER OF
PINS
CRYSTAL OSC. XTAL1
XTAL2 XTAL1 XTAL2 2
POWER VDD
AVDD VDD AVDD 12
GROUND GND
AGND GND AGND 12
10BASE-T INTERFACE TPERXP
TPERXN
TPETXP
TPETXN
TPETXDP
TPETXDN
TPERXP
TPERXN
TPETXP
TPETXN
TPETXDP
TPETXDN
6
AUI INTERFACE RECP
RECN
COLP
COLN TXP/nCOLL
TXN/nCRS
RECP
RECN
COLP
COLN
TXP/nCOLL
TXN/nCRS
6
LEDs nLNKLED/TXD
nRXLED/RXCLK
nBSELED/RXD
nTXLED/nTXEN
nLNKLED/TXD
nRXLED/RXCLK
nBSELED/RXD
nTXLED/nTXEN
4
MISC. RBIAS
WAKEUP
nWAKEUPEN
PWRDWN/TXCLK
nXENDEC
nEN16
ROM/nPCMCIA
RBIAS
WAKEUP
nWAKEUPEN
PWRDWN/TXCLK
nXENDEC
nEN16
ROM/nPCMCIA
7
TOTAL PINS 120

9
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
113 nROM/
nPCMCIA I/O4 with pullup This pin is sampled at the end of RESET. When this pin is sampled low the SMC91C95
is configured for PCMCIA operation and all
pin definitions correspond to the PCMCIA
mode. For ISA operation this pin is left open
and is used as a ROM chip select output that
goes active when nMEMR is low and the
address bus contains a valid ROM address.
35, 36,
38-43,
45-50,
52, 53
Address 0-
15 A0-A15 IInput address lines 0 through 15.
54 Address 16 A16 IISA - Input address line 16.
nFlash
Memory
Write
nFWE O4 PCMCIA - Output. Flash Memory Write
Enable used for programming the attribute
memory. Goes active (low) when nWE=0 and
WRATTRIB=1 (in ECOR bit 3).
55 Address 17 A17 IISA - Input address line 17.
nFlash
Memory
Chip Select
nFCS O4 PCMCIA - Output. Flash Memory Chip Select
used to access attribute memory. Goes active
(low) when nREG=0, nCE1=0 and A15=0.
56 Address 18 A18 IInput address line 18.
57 Address 19 A19 I with pullup ISA - Input address line 19.
Card Enable
1nCE1 PCMCIA - Card Enable 1 input. Used to select card on even byte accesses.
34 Address
Enable AEN I with pullup ISA - Address enable input. Used as an address qualifier. Address decoding is only
enabled when AEN is low.
nREG PCMCIA - Attribute memory and IO select
input. Asserted when the card attribute space
or IO space is being accessed.

10
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
81 nByte High
Enable nSBHE I with pullup ISA - Byte High Enable input. Asserted (low) by the system to indicate a data transfer on
the upper data byte.
nCard
Enable 2 nCE2 PCMCIA - Card Enable 2 input. Used to select card on odd byte accesses.
83 Ready IOCHRDY OD24 with
pullup ISA - Output. Optionally used by the SMC91C95 to extend host cycles.
nWait nWAIT PCMCIA - Output. Optionally used by the
SMC91C95 to extend host cycles.
59, 60,
61, 63,
65, 66,
68-70,
72-74,
76-79
Data Bus D0-D15 I/O24 Bidirectional. 16 bit data bus used to access
the SMC91C95 internal registers. The data
bus has weak internal pullups. Supports direct
connection to the system bus without external
buffering.
98 Reset RESET IS with
pullup Input. Active high Reset. This input is not considered active unless it is active for at least
100ns to filter narrow glitches. A POR circuit
generates an internal reset upon power up for
at least 15msec. All hardware reset
references in this spec relate to the OR
function of the POR and the RESET pin.
82 Address
Latch BALE IS with pullup ISA - Input. Address strobe. For systems that require address latching, the falling edge of
BALE latches address lines and nSBHE.
nWrite
Enable nWE PCMCIA - Write Enable input. Used for writing into COR and CSR registers as well as
attribute memory space.
90 Interrupt INTR0 O24 ISA - Active high interrupt signal. The interrupt
line selection is determined by the value of
INT SEL1-0 bits in the Configuration Register.
This interrupt is tri-stated when not selected.

11
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
nInterrupt
Request nIREQ PCMCIA - Active low interrupt request output. Pin acts as a Ready pin during power-up. The
pin should be pulled low within 10us of the
application of the VCC or Reset (which ever
occurs later). It remains low(0) until the CIS is
loaded in the Internal SRAM. The high(1)
state indicates to the host controller that the
device is ready.
91 Interrupt 1 INTR1 O24 ISA - Output. Active high interrupt signal. The
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
nINPACK PCMCIA - Output asserted to acknowledge
read cycles for an enabled function.
92 Interrupt 2 INTR2 O24 ISA - Output. Active high interrupt signal. The
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
nStatus
Changed nSTSCHG PCMCIA - Status changed bit. Depending on the setting of the RingEn bit (Modem CCSR),
this pin either reflects the ringing status (ExCA
mode) or the state of the Modem Changed bit.
The ringing status is obtained by stretching
the MRINGIN to convert a 20Hz toggle rate to
a constant level.
93 Interrupt 3 INTR3 O24 ISA - Output. Active high interrupt signal. The
interrupt line selection is determined by the
value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
selected.
85 nI/O 16 nIOCS16 OD24 ISA - Active low output asserted in 16 bit
mode when AEN is low and A4-A15 decode
to the SMC91C95 address programmed into
the high byte of the Base Address Register.

12
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
nIOIS16 PCMCIA - Active low output asserted
whenever the SMC91C95 is in 16 bit mode,
and “Enable Function” bit in the ECOR
register is high, nREG is low and A4-A15
decode to the LAN address specified in I/O
Base Registers 0 and 1 in PCMCIA attribute
space.
88 nI/O Read nIORD IS with
pullup Input. Active low read strobe used to access the SMC91C95 IO space.
87 nI/O Write nIOWR IS with
pullup Input. Active low write strobe used to access the SMC91C95 IO space.
86 nMemory
Read nMEMR IS with pullup ISA - Active low signal used by the host processor to read from the external ROM.
nOutput
Enable nOE PCMCIA - Output Enable input used to read from the COR, CSR and attribute memory.
24 nModem
Reset nMRESET O4 Reset output to Modem. Asserted whenever RESET pin is high, internal POR is active, or
SRESET bit is high (MCOR bit 7).
18 Modem
Interrupt MINT I with pull down Interrupt input from Modem. Reflected in INTR (CSR bit 1) and asserts the appropriate
interrupt pin if enabled.
23 nModem
Chip Select nMCS O4 Chip select output to modem.
17 Modem
Ready MRDY I with pullup Modem ready input. Low indicates the modem is not ready, either after reset or exiting from
stop or sleep modes.
27 nModem
Powerdown nMPWDN O4 Powerdown output to modem controller. This pin is active (low) when either the PWRDWN
bit (CSR bit 2) is set or the modem is disabled
(not configured).

13
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
26 MIDLEN1 O4 Powerdown output to modem controller. This
pin is active (high) when either the PWRDWN
bit (CSR bit 2) is set or the modem is disabled
(not configured).
20 Modem Ring
Input MRINGIN IRing input from the modem controller. Toggles when ringing, low when not ringing.
21 nModem
Ring Output
A
nMRINGOA O4 Ring output signal. When there is no ringing
on the MRINGIN pin and the modem is not in
Powerdown mode this output is high. During
ringing this signal is the inverse of the
MRINGIN input. When the PWRDWN bit is
set or the function is disabled, this output is
low. This signal is activated about 12 msec
after removing Powerdown.
22 Modem Ring
Output B MRINGOB O4 Ring output signal. When the modem is not in Powerdown mode (PWRDWN bit is zero and
the function is enabled) this output follows the
value of the MRINGIN input. When entering
Powerdown mode, a rising edge is generated
on the pin. A rising edge is also generated
when exiting Powerdown mode also. Refer to
Figure 2.
14 Speaker
Input SPKRIN I with pullup Speaker Input. This is a digitized (single level) audio input from the modem controller.
15 Speaker
Output SPKROUT O4 tri-stable with pullup Speaker Output. This pin reflects the SPKRIN pin when enabled by the AUDIO bit (Modem
CSR bit 3). When disabled this pin is tri-
stated.
28 nMPDOUT I Schmitt Used to control Powerdown mode. Tie to a
180K pull-up and a 0.1uF cap to ground.
Tie high when not used. This signal is used
in the RC time constant.
29 MFBK1 O4 with
pullup Tie to nMPDOUT through a 5.1M resistor. This signal is used in the RC time constant
in conjuction with the nMPDOUT pin.

14
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
16 n16 Bit
Modem nMIS16 I with pullup Input. When low, it indicates a 16 bit modem, otherwise the modem is 8 bit wide. Used to
determine if nIOIS16 (PCMCIA) and nIOCS16
(ISA) need to be asserted for modem cycles.
The value of this pin may change from cycle
to cycle.
110 EEPROM
Clock EESK O4 Output. 4µs clock used to shift data in and out of the serial EEPROM.
109 EEPROM
Chip Select EECS O4 Output. Serial EEPROM chip select.
108 EEPROM
Data Out EEDO/ SDOUT O4 Output. Connected to the DI input of the serial EEPROM.
107 EEPROM
Data In EEDI I with pull- down Input. Connected to the DO output of the serial EEPROM.
103,
105, 106 I/O Base IOS0-IOS2 I with pullup Input. External switches can be connected to these lines to select between predefined
EEPROM configurations. The values of these
pins are readable. These pins are used in ISA
mode only. If in PCMCIA mode, these pins
are not used.
9nTransmit
LED nTXLED OD16 Internal ENDEC - Transmit LED output.
nTransmit
Enable nTXEN O162 External ENDEC - Active low Transmit Enable output.
12 nRoard
Select LED nBSELED OD16 Internal ENDEC - Board Select LED activated by accesses to I/O space (nIORD or nIOWR
active with AEN low and valid address decode
for ISA, and with nREG low and and “Enable
Function” bit in the ECOR register is high for
PCMCIA). The pulse is stretched beyond the
access duration to make the LED visible.
Receive
Data RXD I with pullup External ENDEC - NRZ receive data input.

15
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
10 nReceive
LED nRXLED OD16 Internal ENDEC - Receive LED output.
Receive
Clock RXCLK I with pullup External ENDEC - Receive clock input.
11 nLink LED nLNKLED OD16 Internal ENDEC - Link LED output.
Transmit
Data TXD 0162 External ENDEC - Transmit Data output.
111 Enable
EEPROM ENEEP I with pullup Input. This active high input enables the EEPROM to be read or written by the
SMC91C95. Internally pulled up. Must be
connected to ground if no serial EEPROM is
used. In PCMCIA mode, a parallel EEPROM
is required if no serial EEPROM is used.
115 nEnable 16
Bit nEN16 I with pullup Input. When low the SMC91C95 is configured for 16 bit bus operation. If left open the
SMC91C95 works in 8 bit bus mode. 16 bit
configuration can also be programmed via
serial EEPROM (In ISA Mode only) or via
software initialization of the CONFIGURATION
REGISTER.
101
102
Crystal 1
Crystal 2
XTAL1
XTAL2
Iclk An external parallel resonance 20 MHz crystal
should be connected across these pins. If an
external clock source is used, it should be
connected to XTAL1 and XTAL2 should be
left open.
123
124
AUI Receive RECP
RECN
Diff. Input AUI receive differential inputs.
2
3AUI
Transmit TXP/nCOLL TXN/nCRS Diff. Output Internal ENDEC - (nXENDEC pin open). In this mode TXP and TXN are the AUI transmit
differential outputs. They must be externally
pulled up using 150 ohm resistors.
IExternal ENDEC - (nXENDEC pin tied low).
In this mode the pins are inputs used for
collision and carrier sense functions.

16
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
125
126 AUI Collision COLP
COLN Diff. Input AUI collision differential inputs. A collision is indicated by a 10 MHz signal at this input pair.
121
122 TPE Receive TPERXP
TPERXN Diff. Input 10BASE-T receive differential inputs.
4
6TPE
Transmit TPETXP TPETXN Diff. Output Internal ENDEC - 10BASE-T transmit differential outputs.
5
7TPE
Transmit
Delayed
TPETXDP
TPETXDN Diff. Output 10BASE-T delayed transmit differential outputs. Used in combination with TPETXP
and TPETXN to generate the 10BASE-T
transmit pre-distortion.
114 Powerdown PWRDWN I with pullup Internal ENDEC - Powerdown input. It keeps
the SMC91C95 in powerdown mode when
high (open). Must be low for normal operation.
Refer to the Powerdown Matrix following for
further details.
Transmit
Clock TXCLK External ENDEC - Transmit clock input from external ENDEC
99 nWakeup
Enable nWAKEUP- EN I with pullup Input. When pulled down, the device will enable Magic Packet (MP) logic and put the
Ethernet function in powerdown mode. The
pin assertion will override the state of
WAKEUP_EN and PWRDN bits in CTR,
Pwrdwn bit in ECSR, and Enable Function bit
ECOR. When deasserted, the WAKEUP_EN
and PWRDN bits will be changed to (0),
Pwrdwn to (0), and Enable Function to (1).
100 Wakeup WAKEUP O4Output. Asserted high if nWAKEUP_EN is
asserted and a valid Magic Packet (MP)
pattern is detected. The pin remains asserted
until nWAKEUP_EN is deasserted.
118 Bias
Resistor RBIAS Analog Input A 22 kohm 1% resistor should be connected between this pin and analog ground.

17
DESCRIPTION OF PIN FUNCTIONS
PIN NO. NAME SYMBOL TYPE DESCRIPTION
116 nExternal
ENDEC nXENDEC I with pullup When tied low the SMC91C95 is configured for external ENDEC. When tied high or left
open the SMC91C95 will use its internal
encoder/decoder.
13, 25,
37, 51,
62, 71,
80, 89,
104
Power VDD +5V power supply pins
1, 117,
120 Analog Power AVDD +5V analog power supply pins
19, 30,
44, 58,
67, 75,
84, 94,
112
Ground VSS Ground pins
8, 119,
127 Analog Ground AVSS Analog ground pins
BUFFER TYPES
O4 Output buffer with 2mA source and 4mA sink
O162 Output buffer with 2mA source and 16mA sink
O24 Output buffer with 12mA source and 24mA sink
OD16 Open drain buffer with 16mA sink
OD24 Open drain buffer with 24mA sink
I/O24 Bidirectional buffer with 12mA source and 24mA sink
IInput buffer with TTL levels
IS Input buffer with Schmitt Trigger Hysteresis
Iclk Clock input buffer

18
Figure 1- SMC91C95 System Block Diagram for ISA Bus with Boot PROM
TPETXP
TPETXN
TPETXDP
TPETXDN
TPERXP
TPERXN
TXP
TXN
RECP
RECN
COLP
COLN
XTAL1XTAL2EEDI
EECS
EEDO
EESK
IOS0IOS1IOS2nEN16ENEEP
AEN BALE RESET
nSBHE
nIORD,nIOWR,
nMEMR
D0-15
A0-19nROMnIOCS16IOCHRDYINTR0-3
4
DIAGNOSTIC
LEDs
SERIAL
EEPROM
4
20MHz
3
SYSTEMBUS
ADDRESS
PROM
DATA
nIRQ
4
N/C
RBIAS
BUFFER
SMC91C95
CABLE SIDE
10BASET AUI

19
Figure 2- SMC91C95 System Block Diagram for Dual Function PCMCIA Card
MODEM
CHIPSET
SMC91C95
nCE1 nCE2 nREG nWE
nIREQ
D0-D15
RESET
nIORD nIOWR
A0-A9, A15
nIOIS16 nINPACK
nWAIT
nCEnWE
nOE
nOE
D0-D7
A0-X
PCMCIA CONNECTOR
10BASE-T/AUI
INTERFACE
nRESET
INT
nCS
RDY
PWDN
RINGIN
STSCHG
RINGOUTB
SPKROUT
PHONE LINE
nMRESET
MINT
nMCS
MRDY
MPWDN
MRINGIN
MRINGOB
nFWE
nFCS
SPKRIN SPKR
CS,SK,DI,DO
SERIAL EPROM
(ISA-Hy9346)
(PCMCIA-Hy93c66)
EXTENDED
ATTRIBUTE
EPROM
2816
(Optional)

20
Figure 3- SMC91C95 Internal Block Diagram
MODEM
INTERFACE
TWISTED PAIR
TRANSCEIVER
DATA
BUS
ADDRESS
BUS
CONTROL
BUS
INTERFACE
ARBITER
CSMA/CD
ENDEC
AUI
MMU
10BASE-T
RAM
MANAGEMENT