Sony ICX274AQ User manual

– 1 – E01410B23-PS
Sony reserves the right to change products and specifications without prior notice.This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices.Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX274AQ
20 pin DIP (Plastic)
Description
The ICX274AQ is a diagonal 8.923mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 2.01M effective pixels. Progressive
scan allows all pixels' signals to be output
independently within approximately 1/15 second,
and output is also possible using various addition
and pulse elimination methods.This chip features an
electronic shutter with variable charge-storage time
which makes it possible to realize full-frame still
images without a mechanical shutter.High resolution
and high color reproductivity are achieved through
the use of R, G, B primary color mosaic filters as the
color filters. Further, high sensitivity and low dark
current are achieved through the adoption of Super
HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
Features
•High horizontal and vertical resolution
•Supports the following modes
Progressive scan mode (with/without mechanical shutter)
2/8-line readout mode
2/4-line readout mode
2-line addition mode
Center scan modes (1), (2) and (3)
AF modes (1) and (2)
•Square pixel
•Horizontal drive frequency: 28.6364MHz (typ.), 36.0MHz (max.)
•Reset gate bias are not adjusted
•R, G, B primary color mosaic filters on chip
•High sensitivity, low dark current
•Continuous variable-speed shutter function
•Excellent anti-blooming characteristics
•20-pin high-precision plastic package
Device Structure
•Interline CCD image sensor
•Image size: Diagonal 8.923mm (Type 1/1.8)
•Total number of pixels: 1688 (H) ×1248 (V) approx. 2.11M pixels
•Number of effective pixels: 1628 (H) ×1236 (V) approx. 2.01M pixels
•Number of active pixels: 1620 (H) ×1220 (V) approx. 1.98M pixels
•Recommended number of
recording pixels: 1600 (H) ×1200 (V) approx. 1.92M pixels
•Chip size: 8.50mm (H) ×6.80mm (V)
•Unit cell size: 4.40µm (H) ×4.40µm (V)
•Optical black: Horizontal (H) direction:Front 12 pixels, rear 48 pixels
Vertical (V) direction: Front 10 pixels, rear 2 pixels
•Number of dummy bits: Horizontal 28
Vertical 1
•Substrate material: Silicon
Optical black position
(Top View)
2
10
V
H
Pin 1
Pin 11 48
12
∗Wfine CCD is trademark of Sony corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Diagonal 8.923mm (Type 1/1.8) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras

–2 –
ICX274AQ
11 12 13 14 15 16 17 18 19 20
Horizontal register
Note)
V
DD
φRG
Hφ
2B
Hφ
1B
GND
φSUB
C
SUB
V
L
Hφ
1A
Hφ
2A
10 9 8 7 6 5 4 3 2 1
V
OUT
GND Vφ
1
Vφ
2C
Vφ
2B
Vφ
2A
Vφ
3C
Vφ
3B
Vφ
3A
Vφ
4
B
G
B
G
B
G
R
G
R
G
B
G
B
G
B
G
R
G
R
G
GRGR
B
G
G
R
B
G
G
R
Vertical register
Note) : Photo sensor
Block Diagram and Pin Configuration
(Top View)
Pin Description
∗1DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance of
0.1µF.
Pin No. Symbol Description Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
Vφ4
Vφ3A
Vφ3B
Vφ3C
Vφ2A
Vφ2B
Vφ2C
Vφ1
GND
VOUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
11
12
13
14
15
16
17
18
19
20
VDD
φRG
Hφ2B
Hφ1B
GND
φSUB
CSUB
VL
Hφ1A
Hφ2A
Supply voltage
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
GND
Substrate clock
Substrate bias∗1
Protective transistor bias
Horizontal register transfer clock
Horizontal register transfer clock

–3 –
ICX274AQ
Absolute Maximum Ratings
∗2+24V (Max.) is guaranteed when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed during power-on or power-off.
Item
VDD, VOUT, φRG –φSUB
Vφ2α, Vφ3α–φSUB (α= A to C)
Vφ1, Vφ4, VL–φSUB
Hφ1β, Hφ2β, GND –φSUB (β= A, B)
CSUB –φSUB
VDD, VOUT, φRG, CSUB –GND
Vφ1, Vφ2α, Vφ3α, Vφ4–GND (α= A to C)
Hφ1β, Hφ2β–GND (β= A, B)
Vφ2α, Vφ3α–VL (α= A to C)
Vφ1, Vφ4, Hφ1β, Hφ2β, GND –VL (β= A, B)
Voltage difference between vertical clock input pins
Hφ1β–Hφ2β(β= A, B)
Hφ1β, Hφ2β–Vφ4 (β= A, B)
Against φSUB
Against GND
Against VL
Between input
clock pins
Storage temperature
Guaranteed temperature of performance
Operating temperature
–40 to +12
–50 to +15
–50 to +0.3
–40 to +0.3
–25 to
–0.3 to +22
–10 to +18
–10 to +6.5
–0.3 to +28
–0.3 to +15
to +15
–6.5 to +6.5
–10 to +16
–30 to +80
–10 to +60
–10 to +75
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
∗2
Ratings Unit Remarks

–4 –
ICX274AQ
Bias Conditions
∗1Progressive scan mode, 2/8-line readout mode, 2/4-line readout mode, center scan modes (1) and (3),
and AF modes (1) and (2)
∗22-line addition mode and center scan mode (2)
∗3VLsetting is the VVL voltage of the vertical clock waveform, or the same voltage as the VLpower supply
for the V driver should be used.
∗4Substrate voltage (VSUB2) setting value indication
The substrate voltage (VSUB) for modes without line addition is generated internally.
The substrate voltage setting value for use with vertical 2-line addition is indicated by a code on the
bottom surface of the image sensor. Adjust the substrate voltage to the indicated voltage.
VSUB2 code –1-digit indication ↑
VSUB2 code
The code and the actual value correspond as follows.
[Example] "h" indicates a VSUB2 setting of 11.6V.
∗5Do not apply a DC bias to the reset gate clock pin, because a DC bias is generated within the CCD.
DC characteristics
Supply current Item IDD
Symbol 10.0 Min. Unit RemarksTyp. Max. mA13.07.0
J
11.8 K 12.0 L 12.2 m 12.4 N 12.6 P 12.8 R 13.0 S 13.2 U 13.4 V 13.6 W 13.8 X 14.0 Y 14.2 Z 14.4
VSUB2 code
Actual value
1
8.8 2 9.0 3 9.2 4 9.4 6 9.6 7 9.8 8 10.0 9 10.2 A 10.4 C 10.6 d 10.8 E 11.0 f 11.2 G 11.4 h 11.6
VSUB2 code
Actual value
Supply voltage
Protective transistor bias
Substrate voltage
adjustment range
Substrate voltage adjustment accuracy
Reset gate clock
Item VDD
VL
VSUB
VSUB2
∆VSUB
φRG
Symbol 15.0
∗3
Internally generated value
Indicated
voltage
∗5
Min. V
V
V
V
Unit
∗4
RemarksTyp. Max.
No line addition∗1
2-line addition∗2
14.55
8.8
Indicated
voltage –0.2
15.45
14.4
Indicated
voltage + 0.2

–5 –
ICX274AQ
Clock Voltage Conditions
Readout clock
voltage
Vertical transfer
clock voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock
voltage
Item
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
VVH3 –VVH
VVH4 –VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VCR
VφRG
VRGLH –VRGLL
VRGL –VRGLm
VφSUB
Symbol
14.55
–0.05
–0.2
–8.0
6.8
–0.25
–0.25
4.75
–0.05
0.8
3.0
21.5
Min.
15.0
0
0
–7.5
7.5
5.0
0
2.5
3.3
22.5
Typ.
15.45
0.05
0.05
–7.0
8.05
0.1
0.1
0.5
0.5
0.5
0.5
5.25
0.05
5.25
0.4
0.5
23.5
Max. Unit
1
2
2
2
2
2
2
2
2
2
2
3
3
3
4
4
4
5
Waveform
diagram
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV= VVHn –VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Cross-point voltage
Low-level coupling
Low-level coupling
Remarks
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

–6 –
ICX274AQ
Clock Equivalent Circuit Constants
Note 1) Expressions using parentheses such as CφV2 (A,B), 3C indicate items which include all combinations of
the pins within the parentheses.
For example, CφV2 (A, B), 3C indicates [CφV2A3C, CφV2B3C].
CφV1
CφV2A, CφV2B
CφV2C
CφV3A, CφV3B
CφV3C
CφV4
CφV12 (A, B)
CφV12C
CφV13 (A, B)
CφV13C
CφV14
CφV2 (A, B), 3 (A, B)
CφV2 (A, B), 3C
CφV2 (A, B), 4
CφV2C, 3 (A, B)
CφV2C, 3C
CφV2C, 4
CφV3 (A, B), 4
CφV3C, 4
CφH1
CφH2
CφHH
CφRG
CφSUB
R1, R4
R2 (A, B, C), 3 (A, B, C)
RGND
RφH
RφH2
RφRG
Symbol
Capacitance between vertical transfer clock and
GND
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Horizontal transfer clock ground resistor
Reset gate clock and series resistor
Item Min. 3300
1200
2700
1000
1800
6800
120
220
150
270
2700
470
680
680
1000
820
1800
820
1500
100
100
47
2
820
30
62
15
7
20
4.7
Typ. Max. pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Ω
kΩ
Ω
Unit Remarks

–7 –
ICX274AQ
Horizontal transfer clock equivalent circuit
Reset gate clock equivalent circuitVertical transfer clock equivalent circuit
Note 2) Cφ2α2βand Cφ3α3β(α= A to C, β= A to C other than α) are
sufficiently small relative to other capacitance between
other vertical clocks in the equivalent circuit, so these
are omitted from the equivalent circuit diagram.
Vφ 4
Vφ 1
Vφ 2α(α= A to C)
Vφ 3α(α= A to C)
Cφ V2α4 (α= A to C)
R GND
Cφ V1
Cφ V3α(α= A to C)
Cφ V4
Cφ V2α(α= A to C)
Cφ V2α3α(α= A to C)
Cφ V3α4 (α= A to C)
Cφ V12α(α= A to C)
Cφ V13α(α= A to C)
Cφ V14
R 4
R 3α(α= A to C)
R 1
R 2α(α= A to C)
Hφ 1B Hφ 2B
Cφ H1
Cφ H2
Cφ HH
Rφ H
Rφ H2
Rφ H
Hφ 1A Hφ 2A
Rφ H Rφ H
RGφRφ
RG
Cφ RG

–8 –
ICX274AQ
Drive ClockWaveform Conditions
(1) Readout clock waveform
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV= VVHn –VVLn (n = 1 to 4)
(2)Vertical transfer clock waveform
100%
90%
10%
0% tr tf 0V
twh
φM
2
φM
V VT
V VH1
V VHH
V VHL
V VH
V VLH
V VL1
V VLL
V VHL
V VHH
V VL
V VH2
V VHH
V VHH
V VHL
V VHL
V VH
V VLH
V VL2
V VLL
V VL
V VHH
V VH
V VLH
V VLL
V VL
V VHL
V VL3
V VHL
V VH3
V VHH
V VH
V VL
V VHL
V VLH
V VLL
V VHL
V VH4
V VHH
V VHH
V VL4
Vφ1Vφ3A, Vφ3B, Vφ3C
Vφ2A, Vφ2B, Vφ2C Vφ4

–9 –
ICX274AQ
VHL
VCR
twl
two
twh
VφH
VφH
2
tr
Hφ2β
90%
10%
Hφ1β
tf
RG waveform
V
RGLH
V RGH
V RGL
V RGLL
V RGLm
tr twh
twl
tf
Vφ RG
Point A
V SUB
(Internally generated bias)
100%
90%
10%
0% tr tftwh
φM
2
φM
Vφ SUB
(3) Horizontal transfer clock waveform
Cross-point voltage for the Hφ1βrising side of the horizontal transfer clocks Hφ1βand Hφ2βwaveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1βand Hφ2βis two. (β= A, B)
(4) Reset gate clock waveform
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH –VRGL
Negative overshoot level during the falling edge of RG isVRGLm.
(5) Substrate clock waveform

–10 –
ICX274AQ
∗1When two vertical transfer clock drivers CXD3400N are used.
∗2tf ≥tr –2ns, and the cross-point voltage (VCR) for the Hφ1β(β= A, B) rising side of the Hφ1βand Hφ2β
waveforms must be VφH/2 [V] or more.
Clock Switching Characteristics (Horizontal drive frequency: 28.6364MHz)
Min. twh Typ. Max.Min. Typ. Max.Min. Typ. Max.Min. Typ.Max.
twl tr tf
3.3
10
10
4
3.5
12.5
12.5
7
2.1
10
10
12.5
12.5
24
0.5
5
5
2
7.5
7.5
0.5
15
0.5
5
5
3
400
7.5
7.5
0.5
Unit
µs
ns
ns
ns
µs
Remarks
During
readout
∗1
∗2
During drain
charge
Item
Readout clock
Vertical transfer
clock
Horizontal
transfer clock
Reset gate clock
Substrate clock
Symbol
VT
Vφ1, Vφ4,
Vφ2α, Vφ3α
(α= A to C)
Hφ1β(β= A, B)
Hφ2β(β= A, B)
φRG
φSUB
Min. two Typ. Max.
810
Unit
ns
RemarksItem
Horizontal
transfer clock
Symbol
Hφ1A, Hφ1B,
Hφ2A, Hφ2B
Clock Switching Characteristics (Horizontal drive frequency: 36MHz)
Min. twh Typ. Max.Min. Typ. Max.Min. Typ. Max.Min. Typ.Max.
twl tr tf
4.0
8
8
4
4.2
9
9
5.5
1.67
8
8
9
9
8
0.5
5
5
2
6
6
0.25
15
0.5
5
5
3
400
6
6
0.25
Unit
µs
ns
ns
ns
µs
Remarks
During
readout
∗1
∗2
During drain
charge
Item
Readout clock
Vertical transfer
clock
Horizontal
transfer clock
Reset gate clock
Substrate clock
Symbol
VT
Vφ1, Vφ4,
Vφ2α, Vφ3α
(α= A to C)
Hφ1β(β= A, B)
Hφ2β(β= A, B)
φRG
φSUB
Min. two Typ. Max.
89
Unit
ns
RemarksItem
Horizontal
transfer clock
Symbol
Hφ1A, Hφ1B,
Hφ2A, Hφ2B