ST SPC56A Series User manual

Introduction
The SPC56A-Discovery+ Evaluation board, here after named SPC56A-DISP, helps you evaluate the SPC56 A line Power
Architecture® Microcontrollers.
The discovery board is based on SPC564A70L7, a 32-bit Power Architecture Book E compliant e200z335 CPU core with 1.5
Mbyte on-chip in an LQFP176 package.
The numerous interfaces including CAN/SCI/K-LINE/DSPI/GPIO make the SPC564A-DISP an excellent starter kit for customer
quick evaluation and project development.
The SPC56 A line is designed to address cost sensitive powertrain and transmission applications.
The SPC56 A line key functionality is a Time Processing Unit (eTPU) with a coprocessor to create events in sync with internal or
external signals without flooding the CPU with interrupt to serve.
Free ready-to-run application firmware examples are available inside SPC5Studio at www.st.com to support quick evaluation
and development.
SPC56A-Discovery+ Evaluation board
UM1700
User manual
UM1700 - Rev 3 - July 2021
For further information contact your local STMicroelectronics sales office.
www.st.com

1SPC564A-DISP with SPC564A70L7
1.1 SPC564A-DISP Discovery board
Figure 1. SPC564A-DISP Discovery board
The content of hardware of SPC564A-DISP withSPC564A70L7 consists of:
• SPC564A-DISP Discovery board (see Figure 1);
• Power Supply (Mains: 90-240 VAC - Output: 5 VDC).
The PCB, the components and all HW parts assembled in the board meet requirements of the applicable RoHS
directives.
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SPC564A-DISP with SPC564A70L7
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2Hardware overview
Figure 2. HW overview
Potentiometer
for ADC
LEDs and User
button
Start-up
configuration
Reset
2 CAN
2 SCI
K-LINE
1 extra CAN
5 VDC power supply
and switch
JTAG connector Nexus connector
(Option)
SPC56EL70L5
4x36 Header
2.1 5 VDC power supply
The 5 VDC voltage is used to supply the whole board including SPC564A70L7 and communication interface
transceiver chips. A zener diode, rating 5.1 V, closed to the power supply connector is used to protect the chips
for high voltage (wrong connection) in a short time. On the board a slide switch for quickly switching on/off is
present.
Figure 3. PSU Section (+5.0 VDC)
The test point TP2 is available to measure the DC input voltage levels (+5 V) while TP3 is connected to GND.
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Hardware overview
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2.2 Device start-up configuration
When the MCU is power-on, it will latch the status of pin WKPCFG, BOOTCFG1 and PLLREF.
• “WKPCFG” determines the weak pull up/down configuration of eMIOS and eTPUpins;
• “BOOTCFG1” is for boot selection;
• “PLLREF” set the source of clock reference input and external circuit related to clock source.
The detailed logic table is the following:
Table 1. SPC564A-DISP – Device startup configuration
WKPCFG BOOTCFG1 PLLREF
0 - Low Weak pull down Boot from internal flash Clock from external reference
1 - High Weak pull up Serial boot from FlexCAN/eSC Clock from external oscillator
The evaluation board provides three jumpers, JP14, JP15 and JP16, which can be used by the user to configure
the device in different working conditions. The figure below shows a typical configuration of the evaluation board
which has only an external crystal oscillator.
Figure 4. Device start-up configuration
2.3 User LEDs
The board provides four LEDs for device status and monitors GPIO98 and GPIO99 outputs. The detailed
information is given in User LEDs here below:
Table 2. User LEDs
Item Mark Color Function
LE1 - Green GPIO99 switching high/low test
ON: LOW, OFF: HIGH
LE2 - Red GPIO98 switching high/low test
ON: LOW, OFF: HIGH
LE3 Power Green Turn on when 5 V supply is ON and it is plugged into the socket (X4)
LE4 EINIT Green Indication for internal / external RESET
OFF: RESET, ON: normal
Figure 5. User LEDs
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Device start-up configuration
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Figure 6. User LEDs - LE1/LE2 (schematic diagram)
Figure 7. User LEDs - LE3/LE4 (schematic diagram)
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User LEDs
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2.4 JTAG/Nexus debug connection
Two kinds of debug interfaces are used in the evaluation board:
• the standard 14-pin JTAG connector of PPC for low-cost/end tools;
• 3MTM Mictor 38-pin connector for Nexus interface in high-end development tools.
Prior to connect any development tool to the debug interface, it is highly recommended to switch off the power
supply of the board and make sure the pin 1 of the tools’ ribbon cable lines up with the pin 1 of onboard
connector.
Figure 8. JTAG/Nexus debug connection
Figure 9. JTAG/Nexus debug connection (schematic diagram)
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JTAG/Nexus debug connection
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2.5 High speed CAN interface
The whole CAN interface circuit usually includes the CAN module in microcontroller, CAN transceiver and CAN
connector.
In the evaluation board, CAN module is integrated with L9616 transceiver which supports high-speed CAN.
Regarding the CAN connectors, the two basic CAN channels of SPC564A70L7, CANA and CANC, are located in
two DB9 male connectors.
Figure 10. High speed CAN interface
As the CAN TX/RX IO of microcontroller is multiplexed with other functions, several jumpers are placed between
L9616 and the MCU. It avoids unwanted connections to L9616 if the CAN TX/RX has been configured to GPIO;
detailed information is reported in the following figure.
Figure 11. High speed CAN interface (schematic diagram)
Note: jumpers JP9, JP12 and JP31 are used to set proper 120 Ω termination resistor for CAN bus. Please disconnect
the jumper if unnecessary.
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High speed CAN interface
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2.6 eSCI/K-LINE
eSCI stands for enhanced serial communication interface, as it enhances the conventional asynchronous RX/TX
with DMA and LIN support. High speed CAN interface, HW configurations show the hardware connection on the
evaluation board:
ST232 is the bridge between RS232 DB9 female interface and TX/RX signal of microcontroller.
L9637 is the ISO9141 interface chip. In the microcontroller side, user can set the jumper 20, 21, 23, 26 to choose
two SCI interfaces, 1x SCI + 1x K-Line or 1x SCI/K-Line.
Figure 12. High speed CAN interface (schematic diagram)
Figure 13. High speed CAN interface, HW configurations
2x SCI,
SCIA,
SCIB
SCIA + K-
Line on
T/RXD_B
SCIB +
K-Line on
T/RXD_A
SCIA SCIB K-Line on
T/RXD_A
K-Line on
T/RXD_B
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eSCI/K-LINE
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2.7 I/O header
All GPIOs/DSPI/eMIOS/eTPU of the MCU can be accessed through the 4x36 I/O headers.
Table 3. I/O header: pin out table
Pin number A B C D
1 GND GND GND 5 V
2 AN10/ AN39/ANY AN9/ANX AN37 AN36
3 AN11/ANZ AN16 AN22 AN24
4 AN18 PCS_B1/GPIO106 AN27 AN30
5PCS_B5/PCS_C0
GPIO110
eTPU_A12/PCS_B1
GPIO126 AN32 AN34
6PCS_B0
GPIO105
eTPU_A17
GPIO131 AN17 eTPU_A29 AN15/ FCK
7eTPU_A10/eTPU_A22
GPIO124
eTPU_A9/eTPU_A21
GPIO123
MCKO
GPIO219
MDO0/eTPU_A13
GPIO220
8eTPU_A11/eTPU_A23
GPIO125
TDI18/eMIOS5
GPIO232
MDO1/eTPU_A19
GPIO221
MDO2/eTPU_A21
GPIO222
9eTPU_A16
GPIO130 eTPU_A27_O MDO3/eTPU_A25 GPIO223 GPIO219
10 eTPU_A18
GPIO132
eTPU_A21
IRQ9
GPIO135
GPIO206
eTPU_A24/IRQ12
SCK_C_LVDS-
GPIO138
11 eTPU_A19
GPIO133
eTPU_A23/IRQ11
eTPU_A21
GPIO137
TXD_A
eMIOS13
GPIO89
RXD_A
eMIOS15
GPIO90
12 RESET eTPU_A13_O RESET_OUT PLLREF/IRQ4/ETRIG0
GPIO208
13 GPIO207
EVTI
eTPU_A2
GPIO231
BOOTCFG1/IRQ3
ETRIG11
GPIO212
VSTBY
14 GPIO99 MSEO0/eTPU_A27
GPIO224
WKPCFG/NMI
GPIO213 eTPU_A29_O
15 eMIOS1/eTPU_A1
GPIO180
PCS_B4/SCK_C
GPIO109
CNRX_A/RXD_A
GPIO84 eTPU_A2_O
16 PCS_B2/SOUT_C
GPIO107
PCS_B3/SIN_C
GPIO108
CNRX_C
GPIO88 eTPU_A4_O
17
CNTX_A
TXD_A
GPIO83
CNTX_C
GPIO87
eMIOS8/eTPU_A8
TXDB
GPIO187
MSEO1
eTPU_A29
GPIO225
18
eMIOS14/IRQ0
eTPU_A29
GPIO193
eTPU_A27
AN14
MA2/SDI
eMIOS9/eTPU_A9
RXDB
GPIO188
eTPU_A28
PCS_C1
GPIO142
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I/O header
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Pin number A B C D
19
eTPU_A19
AN12
MA0/SDS
eMIOS13
GPIO192
eTPU_A27/IRQ15
SOUT_C_LVDS+
SOUTB/ GPIO141
eTPU_A26/IRQ14
SOUT_C_LVDS-
GPIO140
20
eTPU_A29
PCS_C2
GPIO143
eTPU_A21
AN13
MA1/SDO
GPIO98
eTPU_A14/PCS_B4
eTPU_A9
GPIO128
21 RXD_B
GPIO92
TXD_B
GPIO91
eMIOS11
GPIO190
eTPU_A15/PCS_B5
GPIO129
22
eMIOS4
eTPU_A4
GPIO183
eMIOS12/DSPI_C_SOUT
eTPU_A27
GPIO191
eMIOS15
IRQ1
GPIO194
eTPU_A8/eTPU_A20
SOUT_B_LVDS+
GPIO122
23
eMIOS2
eTPU_A2
GPIO181
eMIOS23
GPIO202
eTPU_A7/eTPU_A19
SOUT_B_LVDS-
eTPU_A6/GPIO121
eTPU_A6/eTPU_A18
SCK_B_LVDS+
GPIO120
24
eTPU_A20
IRQ8
GPIO134
eTPU_A22/IRQ10
eTPU_A17
GPIO136
eTPU_A5/eTPU_A17
SCK_B_LVDSGPIO119
eTPU_A4
eTPU_A16
GPIO118
25
eTPU_A30/PCS_C3
eTPU_A11
GPIO144
eTPU_A25/IRQ13
SCK_C_LVDS+
GPIO139
eTPU_A3
eTPU_A15
GPIO117
SCK_B
PCS_C1
GPIO102
26 AN21 AN1/ DAN0- SOUT_B/PSC_C5
GPIO104
SIN_B/PCS_C2
GPIO103
27 AN0/DAN0+ AN3/DAN1-
eTPU_A0/eTPU_A12
eTPU_A19
GPIO114
eMIOS0/eTPU_A0
eTPU_A25
GPIO179
28 AN2/DAN1+ AN5/DAN2- eMIOS10
GPIO189
eTPU_A1/eTPU_A13
GPIO115
29 AN4/DAN2+ AN7/DAN3-
eTPU_A31/PCS_C4
eTPU_A13
GPIO145
eTPU_A2
eTPU_A14
GPIO116
30 AN6/DAN3+ AN25 TDO/eMIOS6
GPIO228
eTPU_A13/PCS_B3
GPIO127
31 AN23 AN31 VRH EVTO/eTPU_A4G
GPIO227
32 AN28 AN35 GND GND
33 AN33 AN8/AN38/ANW 5 V 5 V
34 GND GND GND 5 V
35 GND eTPU_A19_O eTPU_A21_O eTPU_A25_O
36 GND eMIOS3/eTPUA3_O
GPIO182
eMIOS6/eTPUA6_O
GPIO185
eMIOS7/eTPUA7_O
GPIO186
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I/O header
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