ST STM32F10 Series Installation and operating instructions

July 2007 Rev 1 1/23
AN2586
Application note
STM32F10xxx hardware development:
getting started
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use the STM32F10xxx product family and describes the minimum hardware
resources required to develop an STM32F10xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
www.st.com

Contents AN2586 - Application note
2/23
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 6
1.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . . 8
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 12
2.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 13
2.3 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Embedded Boot Loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 18

AN2586 - Application note Contents
3/23
4.3.4 SWJ debug port connection with Standard JTAG connector . . . . . . . . . 19
5 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

List of tables AN2586 - Application note
4/23
List of tables
Table 1. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2. Debug port pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. SWJ I/O pin availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AN2586 - Application note List of figures
5/23
List of figures
Figure 1. Power supply overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Clock overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Crystal/ceramic resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Crystal/ceramic resonators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. STM32F10xxx microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power supplies AN2586 - Application note
6/23
1 Power supplies
1.1 Introduction
The device requires a 2.0 V to 3.6 V operating voltage supply (VDD). An embedded regulator
is used to supply the internal 1.8 V digital power.
The real-time clock (RTC) andbackup registers can be powered from the VBAT voltage when
the main VDD supply is powered off.
Figure 1. Power supply overview
1.1.1 Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply that can be
filtered separately, and shielded from noise on the PCB.
●the ADC voltage supply input is available on a separate VDDA pin
●an isolated supply ground connection is provided on the VSSA pin
When available (depending on package), VREF– must be tied to VSSA.
On 100-pin packages
To ensure a better accuracy on low-voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF+. The voltage on VREF+ may range from 2.0 V to
VDDA.
A/D converter
VDDA
VDD
VSSA
VREF+
VBAT
VSS I/O Ring
BKP registers
Temp. sensor
Reset block
Standby circuitry
PLL
(Wakeup logic,
IWDG)
RTC
Voltage regulator
Core
memories'
digital
peripherals
Low voltage detector
VREF- VDDA domain
VDD domain 1.8 V domain
Backup domain
LSE crystal 32K osc
RCC BDCR register
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AN2586 - Application note Power supplies
7/23
On packages with 64 pins or less
The VREF+ and VREF- pins are not available, they are internally connected to the ADC
voltage supply (VDDA) and ground (VSSA).
1.1.2 Battery backup
To retain the content of the Backup registers when VDD is turned off, the VBAT pin can be
connected to an optional standby voltage supplied by a battery or another source.
The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main
digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the power
down reset (PDR) circuitry embedded in the Reset block.
If no external battery is used in the application, VBAT must be connected externally to VDD.
1.1.3 Voltage regulator
The voltage regulator is always enabled after reset. It works in three different modes
depending on the application modes.
●in Run mode,the regulator supplies full power to the 1.8 V domain (core, memories and
digital peripherals)
●in Stop mode, the regulator supplies low power to the 1.8 V domain, preserving the
contents of the registers and SRAM
●in Standby mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for those concerned with the Standby circuitry and the Backup domain.
1.2 Power supply schemes
The circuit is powered by a stabilized power supply, VDD.
●Caution:
– If the ADC is used, the VDD range is limited to 2.4 V to 3.6 V
– If the ADC is not used, the VDD range is 2 V to 3.6 V
●The VDD pins must be connected to VDD with external stabilization capacitors (five
100 nF ceramic capacitor + one Tantalum capacitor (min. 4.7 µF typ.10 µF).
●The VBAT pin must be connected to the external battery (1.8 V < VBAT < 3.6 V). if no
external battery is used, this pin must be connected to VDD with a 100 nF external
ceramic stabilization capacitor.
●The VDDA pin must be connected to two external stabilization capacitors (10 nF
ceramic + 1 µF Tantalum).
●The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, two 10 nF and 1 µF capacitors must be
connected on this pin. In all cases, VREF+ must be kept between 2.0 V and VDDA.

Power supplies AN2586 - Application note
8/23
Figure 2. Power supply scheme
1. Optional. If a separate, external reference voltage is connected on VREF+, the two capacitors (10 nF and
1 µF) must be connected.
2. VREF+ is either connected to VDDA or to VREF.
1.3 Reset & power supply supervisor
1.3.1 Power on reset (POR) / power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting from
2V.
The device remains in the Reset mode as long as VDD is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power down reset threshold, refer to the electrical characteristics in the
STM32F101xx and STM32F103xx datasheets.
Figure 3. Power on reset/power down reset waveform
VBAT
STM32F10xxx
5 × 100 nF
VDD
+ 1 × 10 µF
10 nF + 1 µF
10 nF + 1 µF
(note 1)
Battery
VBAT VREF+
VDDA
VSSA
VREF–
VDD 1/2/3/4/5
VSS 1/2/3/4/5
VREF
VDD
ai14363
VDD
POR
PDR
40 mV
hysteresis
Temporization
tRSTTEMPO
RESET
ai14364

AN2586 - Application note Power supplies
9/23
1.3.2 Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate
whether VDD is higher or lower than the PVD threshold. This event is internally connected to
EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD
output interrupt can be generated when VDD drops below the PVD threshold and/or when
VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge
configuration. As an example the service routine can perform emergency shutdown tasks.
Figure 4. PVD thresholds
1.3.3 System reset
A system reset sets all registers to their reset values except for the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 1).
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. window watchdog end-of-count condition (WWDG reset)
3. Independent watchdog end-of-count condition (IWDG reset)
4. A software reset (SW reset)
5. Low-power management reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.
V
DD
100 mV
hysteresis
PVD threshold
PVD output
ai14365

Power supplies AN2586 - Application note
10/23
Figure 5. Reset circuit
RON
VDD
Filter
0.1 µF
External
reset circuit NRST System nreset
WWDG reset
IWDG reset
POR/PDR reset
Software reset
Low-power management reset
Pulse
generator
(min 20 µs)
ai14366

AN2586 - Application note Clocks
11/23
2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
●HSI oscillator clock (high speed internal clock signal)
●HSE oscillator clock (high speed external clock signal)
●PLL clock
The devices have two secondary clock sources:
●32 kHz low speed internal RC (LSI RC) that drives the independent watchdog and,
optionally, the RTC used for Auto Wake-up from the Stop/Standby modes.
●32.768 kHz low speed external crystal (LSE crystal) that optionally drives the real-time
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
the power consumption.
Figure 6. Clock overview
1. HSE = High-speed external clock signal; HSI = high-speed internal clock signal; LSI = low-speed internal
clock signal; LSE = low-speed external clock signal.
HSE OSC
4-16 MHz
OSC_IN
OSC_OUT
OSC32_IN
OS32_OUT
LSE OSC
32.768 kHz
LSI RC
32 kHz
PLL
x2, x3, x4
PLLMUL
MCO Clock Output
Main
PLLXTPRE
..., x16
PLLCLK
HSI
HSE
APB1
Prescaler
/1, 2, 4,8, 16
ADCCLK
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
TIM2, 3, 4
x1, 2 Multiplier
USBCLK
to USB interface
to TIM2, 3
and 4
USB
Prescaler
/1, 1.5
toADC
LSE
LSI
HSI
/2
HSI
HSE peripherals
to APB1
Peripheral Clock
Enable (3 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
TIM1 Timer
x1, 2 Multiplier to TIM1
peripherals
to APB2
48 MHz
72MHz 36 MHzmax
toRTC
PLLSRC SW
MCO
CSS
to Cortex System timer
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TIM1CLK
TIMXCLK
IWDGCLK
SYSCLK
FCLK Cortex
free running clock
8 MHz
HSI RC
72 MHz max
72 MHz max
Peripheral Clock
Enable (11 bits)
Peripheral Clock
Enable (1 bit)
to independent watchdog (IWDG)
Clock
Enable (3 bits)
Peripheral Clock
Enable (13 bits)
/2
/128
/2
AHB
Prescaler
/1,2...512
/8
ADC
Prescaler
/2, 4, 6, 8
ai14367

Clocks AN2586 - Application note
12/23
2.1 HSE OSC clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
●HSE external crystal/ceramic resonator (see Figure 8)
●HSE user external clock (see Figure 7)
1. CL1 and CL2 represent the load capacitances.
2. The value of REXT depends on the crystal characteristics. Typical value is in the range of 5 to 6 RS
(resonator series resistance).
2.1.1 External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
25 MHz. The external clock signal (square, sine or triangle) with a duty cycle of about 50%,
has to drive the OSC_IN pin while the OSC_OUT pin must be left in the high impedance
state (see Figure 8 and Figure 7).
2.1.2 External crystal/ceramic resonator (HSE crystal)
The 4-to-16 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock. The associated hardware configuration is shown in Figure 8.
The resonator and the load capacitors have to be connected as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The load
capacitance values must be adjusted according to the selected oscillator.
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF-to-
25 pF range (typ.), designed for high-frequency applications and selected to meet the
requirements of the crystal or resonator. CL1 and CL2, are usually the same value. The
crystal manufacturer typically specifies a load capacitance that is the series combination of
CL1 and CL2. The PCB and MCU pin capacitances must be included when sizing CL1 and
CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance).
Refer to the electrical characteristics sections in the STM32F101xx and STM32F103xx
datasheets for more details.
Figure 7. External clock Figure 8. Crystal/ceramic resonators
OSC_OUTOSC_IN
External source (Hi-Z)
ai14369
Hardware configuration OSC_OUTOSC_IN
ai14370
STM32F10xxx
REXT(1)
CL1 CL2
Hardware configuration

AN2586 - Application note Clocks
13/23
2.2 LSE OSC clock
The low-speed external clock signal (LSE) can be generated from two possible clock
sources:
●LSE external crystal/ceramic resonator (see Figure 10)
●LSE user external clock (see Figure 9)
2.2.1 External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency of
32.768 kHz. The external clock signal (square, sine or triangle) with a duty cycle of about
50% has to drive the OSC32_IN pin while the OSC32_OUT pin must be left high impedance
(see Figure 10 and Figure 9).
2.2.2 External crystal/ceramic resonator (LSE crystal)
The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the
advantage of providing a low-power, but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The resonator and the load capacitors have to be connected as close as possible to the
oscillator pins in order to minimize output distortion and start-up stabilization time. The load
capacitance values must be adjusted according to the selected oscillator.
2.3 Clock-out capability
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be
programmed in alternate function mode. One out of four clock signals can be selected as
the MCO clock:
●SYSCLK
●HSI
●HSE
●PLL clock divided by 2
Figure 9. External clock Figure 10. Crystal/ceramic resonators
OSC32_OUTOSC32_IN
External source (Hi-Z)
ai14371
Hardware configuration
OSC32_OUTOSC32_IN
ai14372
STM32F10xxx
CL1 CL2
Hardware configuration

Clocks AN2586 - Application note
14/23
2.4 Clock security system (CSS)
The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
●If a failure is detected on the HSE oscillator clock, the oscillator is automatically
disabled. A clock failure event is sent to the break input of the TIM1 advanced control
timer and an interrupt is generated to inform the software about the failure (clock
security system interrupt CSSI), allowing the MCU to perform rescue operations. The
CSSI is linked to the Cortex™-M3 NMI (non-maskable interrupt) exception vector.
●If the HSE oscillator is used directly or indirectly as the system clock (indirectly means
that it is used as the PLL input clock, and the PLL clock is used as the system clock), a
detected failure causes a switch of the system clock to the HSI oscillator and the
disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the
clock entry of the PLL used as system clock when the failure occurs, the PLL is
disabled too.
For details, see reference manual UM0306 available from the STMicroelectronics website
www.st.com.

AN2586 - Application note Boot configuration
15/23
3 Boot configuration
3.1 Boot mode selection
In the STM32F10xxx, three different boot modes can be selected by means of the
BOOT[1:0] pins as shown in Table 1.
This selection aliases the physical memory associated with each boot mode to Block 000
(boot memory). The values on the BOOT pins are latched on the 4th rising edge of SYSCLK
after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the
required boot mode.
The BOOT pins are also re-sampled when exiting the Standby mode. Consequently, they
must be kept in the required Boot mode configuration in the Standby mode.
Even when aliased in the boot memory space, the related memory (Flash memory or
SRAM) is still accessible at its original memory space.
After this startup delay has elapsed, the CPU starts code execution from the boot memory,
located at the bottom of the memory address space starting from 0x0000_0000.
3.2 Boot pin connection
Figure 11 shows the external connection required to select the boot memory of the
STM32F10xxx.
Figure 11. Boot mode selection implementation example
1. Resistor values are given only as a typical example.
Table 1. Boot modes
BOOT mode selection pins Boot mode Aliasing
BOOT1 BOOT0
x0User Flash memory User Flash memory is selected as boot
space
01System memory System memory is selected as boot
space
11Embedded SRAM Embedded SRAM is selected as boot
space
ai14373
VDD
STM32F10xxx
BOOT0
BOOT1
VDD
10 kΩ
10 kΩ

Boot configuration AN2586 - Application note
16/23
3.3 Embedded Boot Loader mode
The Embedded Boot Loader mode is used to reprogram the Flash memory using one of the
serial interfaces (typically a UART). This program is located in the system memory and is
programmed by ST during production.
For details, refer to the STM32F10xxx Flash programming manual, PM0042, available from
the STMicroelectronics website, www.st.com.

AN2586 - Application note Debug management
17/23
4 Debug management
4.1 Introduction
The Host/Target interface is the hardware equipment that connects the host to the
application board. This interface is made of three components: a hardware debug tool, a
JTAG or SW connector and a cable connecting the host to the debug tool.
Figure 12 shows the connection of the host to the STM3210B-EVAL board.
Figure 12. Host-to-board connection
4.2 SWJ debug port (serial wire and JTAG)
The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP). It is an
ARM® standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and a
SW-DP (2-pin) interface.
●The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port
●The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
4.3 Pinout and debug port pins
The STM32F10xxx MCU is offered in various packages with different numbers of available
pins. As a result, some functionality related to the pin availability may differ from one
package to another.
4.3.1 SWJ debug port pins
Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose
I/Os (GPIOs). These pins, shown in Table 2, are available on all packages.
STM3210B-EVAL
Host PC Power supply
JTAG/SW connector
Debug tool
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Debug management AN2586 - Application note
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4.3.2 Flexible SWJ-DP pin assignment
After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as
dedicated pins immediately usable by the debugger host (note that the trace outputs are not
assigned except if explicitly programmed by the debugger host).
However, the STM32F10xxx MCU implements a register to disable some part or all of the
SWJ-DP port, and so releases the associated pins for general-purpose I/Os usage. This
register is mapped on an APB bridge connected to the Cortex™-M3 system bus. This
register is programmed by the user software program and not by the debugger host.
Table 3 shows the different possibilities to release some pins.
For more details, see the STM32F10xxx reference manual, UM0306, available from the
STMicroelectronics website www.st.com.
4.3.3 Internal pull-up and pull-down on JTAG pins
The JTAG input pins must not be floating since they are directly connected to flip-flops to
control the debug mode features. Special care must be taken with the SWCLK/TCK pin that
is directly connected to the clock of some of these flip-flops.
Table 2. Debug port pin assignment
SWJ-DP pin name JTAG debug port SW debug port Pin
assignment
Type Description Type Debug assignment
JTMS/SWDIO I JTAG Test Mode
Selection I/O Serial Wire Data Input/Output PA13
JTCK/SWCLK I JTAG Test Clock I Serial Wire Clock PA14
JTDI I JTAG Test Data Input - - PA15
JTDO/TRACESWO O JTAG Test Data Output - TRACESWO if async trace
is enabled PB3
JNTRST I JTAG Test nReset - - PB4
Table 3. SWJ I/O pin availability
Available Debug ports
SWJ I/O pin assigned
PA13 /
JTMS/
SWDIO
PA14 /
JTCK/
SWCLK
PA15 /
JTDI PB3 / JTDO PB4/ JNTRST
Full SWJ (JTAG-DP + SW-DP) - reset state X X X X X
Full SWJ (JTAG-DP + SW-DP) but without
JNTRST XXXX
JTAG-DP disabled and SW-DP enabled X X
JTAG-DP disabled and SW-DP disabled Released

AN2586 - Application note Debug management
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To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-up and pull-
down resistors on JTAG input pins:
●JNTRST: Internal pull-up
●JTDI: Internal pull-up
●JTMS/SWDIO: Internal pull-up
●TCK/SWCLK: Internal pull-down
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
●JNTRST: Input pull-up
●JTDI: Input pull-up
●JTMS/SWDIO: Input pull-up
●JTCK/SWCLK: Input pull-down
●JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
Note: The JTAG IEEE standard recommends to add pull-up resistors on TDI, TMS and nTRST but
there is no special recommendation for TCK. However, for the STM32F10xxx, an integrated
pull-down resistor is used for JTCK.
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.
4.3.4 SWJ debug port connection with Standard JTAG connector
Figure 13 shows the connection between the STM32F10xxx and a standard JTAG
connector.
Figure 13. JTAG connector implementation
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VDD VDD
STM32F10xxx
nJTRST
JTDI
JSTM/SWDIO
JTCK/SWCLK
JTDO
nRSTIN
(1) VTREF
(3) nTRST
(5) TDI
(7) TMS
(9) TCK
(11) RTCK
(13)TDO
(15) nSRST
(17) DBGRQ
(19) DBGACK
10 kΩ
10 kΩ
10 kΩVSS
(2)
(4)
(6)
(8)
(10)
(12)
(14)
(16)
(18)
(20)
Connector 2 × 10
JTAG connector CN9

Reference design AN2586 - Application note
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5 Reference design
5.1 Main
The reference design shown in Figure 14, is based on the STM32F10xxx, a highly
integrated microcontroller running at 72 MHz, that combines the new Cortex™-M3 32-bit
RISC CPU core with 128 Kbytes of embedded Flash memory and up to 20 Kbytes of high
speed SRAM.
5.1.1 Clock
Two clock sources are used for the microcontroller:
●X1– 32.768 kHz crystal for the embedded RTC
●X2– 8 MHz crystal for the STM32F10xxx microcontroller
Refer to Section 2: Clocks on page 11.
5.1.2 Reset
The reset signal in Figure 14 is active low. The reset sources include:
●Reset button (B1)
●Debugging tools via the connector CN1
Refer to Section 1.3: Reset & power supply supervisor on page 8.
5.1.3 Boot mode
The STM32F10xxx is able to boot from the:
●embedded user Flash memory
●embedded SRAM for debugging
●system memory
The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 3: Boot configuration on page 15.
5.2 SWJ interface
The STM32F10xxx core integrates the serial wire / JTAG debug port (SWJ-DP). The
reference design shows the connection between the STM32F10xxx and a standard JTAG
connector. Refer to Section 4: Debug management on page 17.
5.3 Power supply
Refer to Section 1: Power supplies on page 6.