ST STM32L0 Series Installation and operating instructions

April 2014 DocID026156 Rev 1 1/34
AN4467
Application note
Getting started with STM32L0xx hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use STM32L0xx product families and describes the minimum hardware
resources required to develop an STM32L0xx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
Table 1. Applicable products
Type Product categories
Microcontrollers STM32L0 Series
www.st.com

Contents AN4467
2/34 DocID026156 Rev 1
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 8
1.1.2 Independent LCD supply (STM32L0x3 only) . . . . . . . . . . . . . . . . . . . . . . 9
1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.1 Power-on reset (POR) / Power-down reset (PDR),
Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.3 Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.4 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 18
2.3 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3.1 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 20
2.3.2 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Clock security system on HSE (CSSHSE) . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Embedded boot loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 BOOT0 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 SWD debug port (serial wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

DocID026156 Rev 1 3/34
AN4467 Contents
3
4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4 Serial wire debug (SWD) pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4.1 SWD pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4.2 Internal pull-up and pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . 25
4.4.3 SWD port connection with standard SWD connector . . . . . . . . . . . . . . 25
5 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Ground and power supply (VSS, VDD,VSSA, VDDA) . . . . . . . . . . . . . . . . . 27
5.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.4 SWD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

List of tables AN4467
4/34 DocID026156 Rev 1
List of tables
Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. VLCD rails connections to GPIO pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. SWD port pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DocID026156 Rev 1 5/34
AN4467 List of figures
5
List of figures
Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. PVD thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. SWD port connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Reference design (based on STM32L053RBT6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power supplies AN4467
6/34 DocID026156 Rev 1
1 Power supplies
1.1 Introduction
The chip requires power supply on different power pins:
•VDD= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins. For VDD below 1.8 V see Section 1.3.3: Brownout reset
(BOR)
•VDDA = VDD: external analog power supply for ADC/DAC, Comparators, Reset
blocks, RCs and PLL. The minimum voltage to be applied to VDDA is 1.8 V when the
ADC and DAC are used.The VDDA voltage level must always be equal to the VDD
voltage level, A maximum difference of 300 mV between VDD and VDDA can be
tolerated during power-up and normal operation.
•VLCD= 2.5V to 3.6V when the LCD controller is powered externally. When the LCD is
powered internally from the voltage generated by the embedded step-up converter,
VLCD pin must be connected to a capacitor. If the LCD is not used at all, this pin should
be connected to VDDA.
•VDD_USB= 3.0 to 3.6 V, VDD_USB is a dedicated independent USB power supply for
USB transceivers. The minimum value of 3.0 V guarantees the USB’s signal voltage
level. When USB is not used the application must supply VDD_USB=1.65V to 3.6V.
Digital power voltage (VCORE) is provided with an embedded linear voltage regulator with
three different programmable ranges from 1.2 to 1.8 V.
To be fully functional at full speed, the device requires a 1.71 to 3.6 V operating voltage
supply (VDD), making possible to reach the digital power voltage VCORE close to 1.8 V
(product voltage range 1).
Product voltage range 2 (VCORE = 1.5 V) and 3 (VCORE = 1.2 V) can be selected when the
VDD operates from 1.65 to 3.6 V. Therefore, frequency is limited to 16 MHz and 4.2 MHz
respectively.
When the ADC, DAC and brownout reset (BOR) are not used, the device can operate at
power voltages below 1.8 V, down to 1.65 V.

DocID026156 Rev 1 7/34
AN4467 Power supplies
33
Figure 1. Power supply overview
Note: VDDA and VSSA must be connected to VDD and VSS, respectively.
-36
!$#
6$$
6,#$
633
)/SUPPLY
6$$6$$!
FROM6UPTO6$$!62%&
4E M P  SE N S O R
2ESETBLOCK
3TANDBYCIRCUITRY
7AKEUPLOGIC
)7$'24#
,3%CRYSTAL
+OSC
2###32
0,,
6OLTAGEREGULATOR
$YNAMICVOLTAGE
SCALING

6$$!DOMAIN
$!#
&LASHMEMORY
,#$
6$$DOMAIN
6#OREDOMAIN
6$$?53" 53"TRANSCEIVER
#ORE
-EMORIES
$IGITAL
PERIPHERALS
633633!

Power supplies AN4467
8/34 DocID026156 Rev 1
1.1.1 Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC and the DAC have an independent power supply
that can be filtered separately, and shielded from noise on the PCB.
•The ADC voltage supply input is available on a separate VDDA pin
•An isolated supply ground connection is provided on the VSSA pin
VDDA and VREF+ require a stable voltage. The consumption on VDDA can reach several mA
(see IDD(ADCx), IDD(DAC), IDD(COMPx), IVDDA, and IVREF in the product datasheets for
further information).
When available (depending on the package), VREF- must be tied to VSSA.
VSSA and VDDA must be tied to VSS directly, without any filtering device, this avoids some
ESD issues.
On some packages with the pin VREF+ to ensure a better accuracy on low-voltage inputs
and outputs, the user can connect to VREF+ a separate external reference voltage which is
lower than VDD. VREF+ is the highest voltage, represented by the full scale value, for an
analog input (ADC) or output (DAC) signal.
On packages without such a dedicated pin, VREF+ is internally connected to the ADC
voltage supply (VDDA).

DocID026156 Rev 1 9/34
AN4467 Power supplies
33
1.1.2 Independent LCD supply (STM32L0x3 only)
The VLCD pin is provided to control the contrast of the glass LCD. This pin can be used in
two ways:
•It can receive, from an external circuitry, the desired maximum voltage that is provided
on the segment and common lines to the glass LCD by the microcontroller.
•It can also be used to connect an external capacitor that is used by the microcontroller
for its voltage step-up converter. This step-up converter is controlled by software to
provide the desired voltage to the segment and common lines of the glass LCD. Refer
to the specific product datasheet for the capacitor value.
The voltage provided to the segment and common lines defines the contrast of the glass
LCD pixels. This contrast can be reduced when the dead time between frames is
configured.
In case of LCD with big pixel, the high capacitance of the pixel might degrade the LCD
signal shape. So the device offer the possibility to connect internal VLCD rails
(LCD_VLCD1, LCD_VLCD2, LCD_VLCD3) to optional capacitors. This improves the
Segment and Common line signals shape with limited use of high drive resistor network, so
it improves the signal shape without extra current consumption. The values of these
decoupling capacitors must be tuned accordingto the LCD glass and the PCB capacitances.
As a guideline the user can set the decoupling capacitor values to approximately 10 times
the LCD and PCB capacitance. The LCD rails to be connected depends on the Bias
configuration.
1.1.3 Voltage regulator
The internal voltage regulator is always enabled after reset. It can be configured to provide
the core with three different voltage ranges. Choosing a range with low Vcore reduces the
consumption but lowers the maximum acceptable core speed. Consumption ranges in
decreasing consumption order are as follows:
•Range 1, available only for VDD above 1.71 V, allows maximum speed
•Range 2 allows CPU frequency up to 16 MHz
•Range 3 allows CPU frequency up to 4 MHz
Note: In Range 1, when VDD is below 2.0V, the CPU frequency in run mode must be managed to
prevent any changes exceeding a ratio of 4 in one shot. A delay of 5µs must be respected
between 2 changes. There is no limitation when waking up from low-power mode.
Table 2. VLCD rails connections to GPIO pins
Bias Pin selected by
CAPA[2:0] bits
1/2 1/3 1/4
LCD_VLCD3 Not used Not used 3/4 VLCD PB0
LCD_VLCD2 1/2 VLCD 2/3 VLCD 1/2 VLCD PB2
LCD_VLCD1 Not used 1/3 VLCD 1/2 VLCD PB12

Power supplies AN4467
10/34 DocID026156 Rev 1
Voltage regulator works in three different modes depending on the application:
•In Run mode, the regulator supplies full power to the Vcore domain (core, memories
and digital peripherals).
•In Stop mode, low-power run and low-power wait modes, the regulator supplies low-
power to the Vcore domain, preserving the contents of the registers and SRAM.
•In Standby mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for those powered with the Standby circuitry.

DocID026156 Rev 1 11/34
AN4467 Power supplies
33
1.2 Power supply schemes
The circuit is powered by a stabilized power supply, VDD.
•The VDD pins must be connected to VDD with external decoupling capacitors; one
single Tantalum or Ceramic capacitor (minimum 4.7 µF typical 10 µF) for the package +
one 100 nF Ceramic capacitor for each VDD pin).
•The VDDA pin must be connected to two external decoupling capacitors (100 nF
Ceramic capacitor + 1 µF Tantalum or Ceramic capacitor).
•The VREF+ pin can be connected to the VDDA external power supply. If a separate,
external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitor must be
connected on this pin. To compensate peak consumption on Vref, the 1 µF capacitor
may be increased up to 10 µF when the sampling speed is high. When ADC or DAC is
used, VREF+ must remain between 1.8 V and VDDA. VREF+ can be grounded when ADC
and DAC are not active; this enables the user to power down an external voltage
reference.
•Additional precautions can be taken to filter digital noise: VDDA can be connected to
VDD through a ferrite bead. In this case take care to keep a (VDDA-VDD) difference
lower than 300 mV.
Figure 2. Power supply scheme
1. VREF+ is either connected to VDDA or to VREF.
2. N is the number of VDD and VSS inputs.
06Y9
9''1
$QDORJ
5&V
3//
*3,2V
287
,1 .HUQHOORJLF
&38'LJLWDO
0HPRULHV
6WDQGE\SRZHUFLUFXLWU\
26&.57&:DNHXSORJLF
57&EDFNXSUHJLVWHUV
1îQ)
î)
5HJXODWRU
9661
9''$
95()
95()
966$
$'&
/HYHOVKLIWHU
,2
/RJLF
9''
Q)
)
95()
Q)
)
9''$

Power supplies AN4467
12/34 DocID026156 Rev 1
Figure 3. Optional LCD power supply scheme
•Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL
switch is open.
•Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch
is closed, an external capacitance is needed for correct behavior of this converter.
Note: The availability of the VLCD rails depend on device package
1.3 Reset and power supply supervisor
The input supply to the main and low-power regulators is monitored by a power-on/power-
down/brownout reset circuit. Power-on/power-down reset are a null power monitoring with
fixed threshold voltages, whereas brownout reset gives the choice between several
thresholds with a very low, but not null, power consumption.
In addition, the STM32L0xx embeds a programmable voltage detector that compares the
power supply with the programmable threshold. An interrupt can be generated when the
power supply drops below the VPVD threshold and/or when the power supply is higher than
the VPVD threshold. The interrupt service routine then generates a warning message and/or
puts the MCU into a safe state.
06Y9
9''1
1[Q)
[)
6WHSXS
FRQYHUWHU
9661
9''
Q)
9/&'
9/&'B9/&'
9/&'
3%RU3(
3%
3%RU3(
&(;7
&UDLO
/&'
96(/
&UDLO &UDLO
2SWLRQ
2SWLRQ
9/&'B9/&'
9/&'B9/&'

DocID026156 Rev 1 13/34
AN4467 Power supplies
33
Figure 4. Power supply supervisors
1. The PVD is available on all STM32L devices and it is enabled or disabled by software.
2. The BOR is available only on devices operating from 1.8 to 3.6 V, and unless disabled by option byte it
masks the POR/PDR threshold.
3. When the BOR is disabled by option byte, the reset is asserted when VDD goes below PDR level.
4. For devices operating from 1.65 to 3.6 V, there is no BOR and the reset is released when VDD goes above
POR level and asserted when VDD goes below PDR level.
VDD/V DDA
PVD output
100 mV
hysteresis
VPVD
VBOR hysteresis
100 mV
IT enabled
BOR reset
(NRST)
POR/PDR reset
(NR ST)
PVD
BOR always active
POR/PDR (BOR not available) ai17211b
POR
V/PDR
V
BOR/PDR reset
(NRST)
BOR disabled by option byte
(Note 1)
(Note 2)
(Note 3)
(Note 4)

Power supplies AN4467
14/34 DocID026156 Rev 1
1.3.1 Power-on reset (POR) / Power-down reset (PDR),
Brownout reset (BOR)
The monitoring voltage begins at 0.7 V.
During power-on, for devices operating between 1.8 and 3.6 V, the BOR keeps the device
under reset until the supply voltages (VDD and VDDA) come close to the lowest acceptable
voltage (1.8 V). At power-up this internal reset is maintained during ~1 ms to wait for the
supply to reach its final value and stabilize.
At power-down the reset is activated as soon as the power drops below the lowest limit (i.e.
1.65 V).
At power-on, a defined reset should be maintained below 0.7 V. The upper threshold for a
reset release is defined in the electrical characteristics section of the product datasheets.
Figure 5. Power on reset/power down reset waveform
For a programmable threshold above the chip lowest limit, a brownout reset can be
configured to the desired value. The BOR can also be used to detect a power voltage drop
earlier. The threshold values of the BOR can be configured through the FLASH_OBR option
byte.
1.3.2 Programmable voltage detector (PVD)
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. Seven different PVD levels
can be selected by software between 1.85 V and 3.05 V, with a 200 mV step.
An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine then generates a
warning message and/or puts the MCU into a safe state. The PVD is enabled by software
configuration. As an example, the service routine can perform emergency shutdown tasks.
VDD/VDDA
Reset
POR
PDR
Temporization
tRSTTEMPO

DocID026156 Rev 1 15/34
AN4467 Power supplies
33
Figure 6. PVD thresholds
1.3.3 Brownout reset (BOR)
During power on, the brownout reset (BOR) keeps the device under reset until the supply
voltage reaches the specified VBOR threshold.
For devices operating from 1.65 to 3.6 V, the BOR option is not available and the power
supply is monitored by the POR/PDR. As the POR/PDR thresholds are at 1.5 V, a “grey
zone” exists between the VPOR/VPDR thresholds and the minimum product operating voltage
1.65 V.
For devices operating from 1.8 to 3.6 V, the BOR is always active at power on and its
threshold is 1.8 V.
When the system reset is released, the BOR level can be reconfigured or disabled by option
byte loading.
If the BOR level is kept at the lowest level, 1.8 V at power-on and 1.65 V at power down, the
system reset is fully managed by the BOR and the product operating voltages are within
safe ranges.
When the BOR option is disabled by option byte, the power down reset is controlled by the
PDR and a “grey zone” exists between the 1.65 V and VPDR.
VBOR is configured through device option bytes. By default, lowest level 0 threshold is
activated. Five programmable VBOR thresholds can be selected (see product datasheets for
actual VBOR0 to VBOR4 thresholds).
When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is
generated. When the VDD is above the VBOR upper limit the device reset is released and the
system can start.
BOR can be disabled by programming the device option bytes. To disable the BOR function,
VDD must have been higher than VBOR0 to start the device option byte programming
sequence. The power-on and power-down is then monitored by the POR and PDR (see
power-on reset (POR)/power-down reset (PDR) section in the product datasheets).
The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the
supply voltage).
VDD/VDDA
PVD output
100 mV
hysteresis
PVD threshold

Power supplies AN4467
16/34 DocID026156 Rev 1
1.3.4 System reset
A system reset sets all registers to their reset values except for the RTC, backup registers
and RCC control/status register, RCC_CSR.
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end-of-count condition (WWDG reset)
3. Independent watchdog end-of-count condition (IWDG reset)
4. A reset bit set by software (SWreset)
5. Entering Standby or Stop mode configured to generate a reset (Low-power
management reset)
6. Option byte loader reset
7. Exiting Standby mode
8. Firewall reset.
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.
Figure 7. Simplified diagram of the reset circuit
The STM32L does not require an external reset circuit to power-up correctly. Only a pull-
down capacitor is recommended to improve EMS performance by protecting the device
against parasitic resets (see Figure 7).
Charging/discharging the pull-down capacitor through the internal resistor adds to the
device power consumption. The recommended value of 100 nF for the capacitor can be
reduced to 10 nF to limit power consumption.
EZ^d
ZWh
ss

tt'ƌĞƐĞƚ
/t'ƌĞƐĞƚ
WƵůƐĞ
ŐĞŶĞƌĂƚŽƌ
WŽǁĞƌƌĞƐĞƚ
džƚĞƌŶĂů
ƌĞƐĞƚ
;ŵŝŶϮϬђƐͿ
^LJƐƚĞŵƌĞƐĞƚ
& ŝůƚĞƌ
^ŽĨƚǁĂƌĞƌĞƐĞƚ
>ŽǁͲƉŽǁĞƌŵĂŶĂŐĞŵĞŶƚƌĞƐĞƚ
ĂŝϭϲϬϵϱĚ
džŝƚŝŶŐƐƚĂŶĚͲďLJƌĞƐĞƚ
&ŝƌĞǁĂůůƌĞƐĞƚ


DocID026156 Rev 1 17/34
AN4467 Clocks
33
2 Clocks
Four different clock sources can be used to drive the system clock (SYSCLK):
•HSI16 (high-speed internal) oscillator clock
•HSE (high-speed external) oscillator clock
•PLL clock
•MSI (multispeed internal) oscillator clock
The MSI is used as a system clock source after startup from reset, wake-up from Standby
low-power modes.The MSI, HSI16 or HSI16 divided by four, are used as a system clock
source after wake-up from Stop low-power mode.
The devices have the following two secondary clock sources:
•37 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for auto-wakeup from Stop/Standby mode.
•32.768 kHz low speed external crystal (LSE crystal) which optionally drives the
real-time clock (RTCCLK)
The STM32L0x2 and STM32L0x3 have HSI48 (high-speed internal) oscillator clock
available for USB and Random generator. This permits a USB communication without the
need for external clock source.
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Refer to the STM32L0xx reference manual (RM0367, RM0376, RM0377) for a description
of the clock tree.
2.1 MSI clock
The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be
adjusted by software through the RCC_ICSCR register. Seven frequency ranges are
available: 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz (default value) and
4.2 MHz. Those frequencies are multiple values of 32.768 kHz.
The MSI clock is used as a system clock after a restart from reset.
The MSI RC oscillator has the advantage of providing a low-cost (no external components)
low-power clock source. It is used as a wakeup clock in low-power modes to reduce power
consumption and wakeup time.
The MSIRDY flag in the RCC_CR register indicates wether the MSI RC is stable or not. At
startup, the MSI RC output clock is not released until this bit is set by hardware.
The MSI RC can be switched on and off through the RCC_CR register (default is on).
Calibration
If the application is subject to voltage or temperature variations, this may affect the RC
oscillator speed. You can trim the MSI frequency in the application through the RCC_ICSCR
register. Typically, this uses the HSE or LSE as reference (see RM0367/376/377 for details
on clock measurement with TIM21). For more information refer to AN3300 “How to calibrate
an STM32Lxx internal RC oscillator”.

Clocks AN4467
18/34 DocID026156 Rev 1
2.2 HSE OSC clock
The high-speed external clock signal (HSE) can be generated from two possible clock
sources:
•HSE user external clock (see Figure 8)
•HSE external crystal/ceramic resonator (see Figure 9)
1. The value of REXT depends on the crystal characteristics. A typical value is in the range of 5 to 6 RS
(resonator series resistance).To fine tune the REXT value ,refer to AN2867(Oscillator design guide for ST
microcontrollers)
2. Load capacitance, CL, has the following formula: CL= CL1 x CL2 / (CL1 + CL2) + Cstray where: Cstray is the
pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Please
refer to Section 5.4: Decoupling to minimize its value.
2.2.1 External source (HSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
32 MHz.
The external clock signal (square, sine or triangle) with a duty cycle of about 50%, has to
drive the OSC_IN pin, while the OSC_OUT pin can be used as a GPIO. From current
consumption standpoint a square signal is preferred (see Figure 8).
When HSE Bypass is used with VDD below 2.0V and in range 1, take care of the frequency
drop as explained in Section 1.1.3: Voltage regulator.
2.2.2 External crystal/ceramic resonator (HSE crystal)
The external oscillator frequency ranges from 1 to 25 MHz.
The external oscillator has the advantage of producing a very accurate rate on the main
clock. The associated hardware configuration is shown in Figure 9.
The resonator and the load capacitors have to be connected as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The load
capacitance values must be adjusted according to the selected oscillator.
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25
pF range (typical), designed for high-frequency applications and selected to meet the
requirements of the crystal or resonator. CL1 and CL2, are usually the same value. The
crystal manufacturer typically specifies a load capacitance that is the series combination of
Figure 8. External clock Figure 9. Crystal/ceramic resonators
K^ͺKhdK^ͺ/E
džƚĞƌŶĂůƐŽƵƌĐĞ
'W/K
ĂŝϭϰϯϲϵĂ
,ĂƌĚǁĂƌĞĐŽŶĨŝŐƵƌĂƚŝŽŶ
K^ͺKhdK^ͺ/E
ĂŝϭϰϯϳϬĐ
^dDϯϮ>dždždž
Z yd;ϭͿ
 >ϭ
 >Ϯ
,ĂƌĚǁĂƌĞĐŽŶĨŝŐƵƌĂƚŝŽŶ

DocID026156 Rev 1 19/34
AN4467 Clocks
33
CL1 and CL2. The PCB and MCU pin capacitances must be included when sizing CL1 and
CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance).
Refer to the electrical characteristics sections in the datasheet of your product for more
details and to the application note AN2867 “Oscillator design guide for STM
microcontrollers”.

Clocks AN4467
20/34 DocID026156 Rev 1
2.3 LSE OSC clock
The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
2.3.1 External crystal/ceramic resonator (LSE crystal)
The LSE crystal is switched on and off using the LSEON bit in RCC control/status register
(RCC_CSR). The crystal oscillator driving strength can be changed at runtime using the
LSEDRV[1:0] bits (in RCC_CSR register) to obtain the best compromise between
robustness and short start-up time on one side and low-power consumption on the other
(see Figure 10).
The LSERDY flag (in RCC_CSR) indicates whether the LSE crystal is stable or not. At
startup, the LSE crystal output clock signal is not released until this bit is set by hardware.
An interrupt can be generated, if enabled, in the Clock interrupt enable register
(RCC_CIER).
2.3.2 External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to 1
MHz. You select this mode by setting the LSEBYP and LSEON bits (in RCC_CSR). The
external clock signal (square, sinus or triangle) has to drive the OSC32_IN pin, from current
consumption standpoint a square signal is preferred. The OSC32_OUT pin can be used as
GPIO (see Figure 10)
1. OSC32_IN and OSC_OUT pins can be also used as GPIOs, but it is recommended not to use them as
both RTC and GPIO pins in the same application.
Figure 10. External clock Figure 11. Crystal/ceramic resonators
K^ϯϮͺKhdK^ϯϮͺ/E
džƚĞƌŶĂůƐŽƵƌĐĞ
'W/K
ĂŝϭϰϯϳϭĂ
,ĂƌĚǁĂƌĞĐŽŶĨŝŐƵƌĂƚŝŽŶ
K^ϯϮͺKhdK^ϯϮͺ/E
ĂŝϭϰϯϳϮĞ
^dDϯϮ>dždždž
>ϭ >Ϯ
,ĂƌĚǁĂƌĞĐŽŶĨŝŐƵƌĂƚŝŽŶ