Toshiba TXZ SERIES User manual

TXZ Family
Serial Peripheral Interface
2019-02-28 1 / 67 Rev. 3.0
© 2017-2019
Toshiba Electronic Devices & Storage Corporation
2019-02
32-bit RISC Microcontroller
TXZ Family
Reference Manual
Serial Peripheral Inteface
(TSPI-B)
Revision 3.0

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Serial Peripheral Interface
2019-02-28 2 / 67 Rev. 3.0
Table of Contents
Preface.................................................................................................................................................................5
Related document.....................................................................................................................................................5
Conventions ............................................................................................................................................................6
Terms and Abbreviation............................................................................................................................................8
Outline...........................................................................................................................................................9
Configuration...............................................................................................................................................14
Operation description..................................................................................................................................16
3.1. Basic operation ................................................................................................................................................16
3.1.1. Clock supply...............................................................................................................................................................16
3.1.2. Initial setting of TSPI...................................................................................................................................................16
3.1.3. Start and stop transfer................................................................................................................................................16
3.2. Data Format.....................................................................................................................................................17
3.2.1. Data Format without Parity.........................................................................................................................................18
3.2.2. Data Format with a Parity...........................................................................................................................................22
3.3. Operation .........................................................................................................................................................26
3.3.1. Transfer clock.............................................................................................................................................................26
3.3.1.1. Master operation ...........................................................................................................................................................26
3.3.1.2. Slave operation .............................................................................................................................................................27
3.3.2. Communication mode.................................................................................................................................................28
3.3.2.1. SPI mode ......................................................................................................................................................................28
3.3.2.2. SIO mode......................................................................................................................................................................29
3.3.2.3. Master / Slave selection ................................................................................................................................................29
3.3.3. Buffer Structure ..........................................................................................................................................................29
3.3.3.1. Data Length and FIFO Operation..................................................................................................................................30
3.3.4. Communication Operation mode................................................................................................................................32
3.3.4.1. Full duplex communication mode..................................................................................................................................32
3.3.4.2. Transmit mode ..............................................................................................................................................................34
3.3.4.3. Receive mode ...............................................................................................................................................................35
3.3.5. Transfer mode............................................................................................................................................................36
3.3.5.1. Single transfer...............................................................................................................................................................36
3.3.5.2. Burst transfer.................................................................................................................................................................36
3.3.5.3. Continuously transfer ....................................................................................................................................................36
3.3.6. Data sampling timing..................................................................................................................................................37
3.3.7. Special control............................................................................................................................................................40
3.3.7.1. Polarity of TSPIxCS0/1/2/3 signal and generation timing ..............................................................................................40
3.3.7.2. Polarity of the Clock ......................................................................................................................................................41
3.3.7.3. TSPIxTXD Output during Idle........................................................................................................................................41
3.3.8. Communication control by trigger...............................................................................................................................43
3.3.9. Interrupt Request........................................................................................................................................................44
3.3.9.1. Transmit Completion Interrupt/Receive Completion Interrupt........................................................................................45
3.3.9.2. Transmit FIFO Interrupt/Receive FIFO Interrupt............................................................................................................45
3.3.9.3. Error Interruption...........................................................................................................................................................45

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3.3.10. DMA request.............................................................................................................................................................47
3.3.10.1. Transmit DMA request ................................................................................................................................................47
3.3.10.2. Receive DMA request .................................................................................................................................................47
3.3.11. Coordinated movements by the completion of communication ................................................................................47
3.3.12. Software reset..........................................................................................................................................................47
Registers.....................................................................................................................................................48
4.1. Register List.....................................................................................................................................................48
4.2. Detail of Register .............................................................................................................................................49
4.2.1. [TSPIxCR0] (TSPI Control Register 0) .......................................................................................................................49
4.2.2. [TSPIxCR1] (TSPI Control Register 1) .......................................................................................................................50
4.2.3. [TSPIxCR2] (TSPI Control Register 2) .......................................................................................................................52
4.2.4. [TSPIxCR3] (TSPI Control Register 3) .......................................................................................................................54
4.2.5. [TSPIxBR] (TSPI Baud Rate Register).......................................................................................................................54
4.2.6. [TSPIxFMTR0] (TSPI Format Control Register 0)......................................................................................................55
4.2.7. [TSPIxFMTR1] (TSPI Format Control Register 1)......................................................................................................57
4.2.8. [TSPIxDR] (TSPI Data Register) ................................................................................................................................57
4.2.9. [TSPIxSR] (TSPI Status Register)..............................................................................................................................58
4.2.10. [TSPIxERR] (TSPI Error Flag Register)....................................................................................................................61
Example for use..........................................................................................................................................62
Precautions.................................................................................................................................................64
Revision History..........................................................................................................................................65
RESTRICTIONS ON PRODUCT USE...............................................................................................................67

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List of Figures
Figure 2.1 Block diagram of TSPI............................................................................................................14
Figure 3.1 Data format.............................................................................................................................17
Figure 3.2 MSB first (32-bit data without a parity bit)...............................................................................18
Figure 3.3 MSB first (16-bit data without a parity bit)...............................................................................19
Figure 3.4 LSB first (32-bit data without a parity bit)................................................................................20
Figure 3.5 LSB first (16-bit data without a parity bit)................................................................................21
Figure 3.6 MSB first (31-bit data with a parity) ........................................................................................22
Figure 3.7 MSB first (15-bit data with parity)............................................................................................23
Figure 3.8 LSB first (31-bit data with parity).............................................................................................24
Figure 3.9 LSB first (15-bit data with parity).............................................................................................25
Figure 3.10 Transfer clock generation circuit...........................................................................................26
Figure 3.11 Operation in 7 to 16-bit data length......................................................................................30
Figure 3.12 Operation in 17 to 32-bit data length....................................................................................31
Figure 3.13 Operation example of full duplex communication.................................................................32
Figure 3.14 Operation example of transmit mode ...................................................................................34
Figure 3.15 Operation example in receive mode.....................................................................................35
Figure 3.16 Data sampling timing of SPI mode (master).........................................................................38
Figure 3.17 Data sampling timing of SPI mode (slave)...........................................................................39
Figure 3.18 Data sampling timing of SIO mode (master)........................................................................39
Figure 3.19 Data sampling timing of SIO mode (slave)...........................................................................39
Figure 3.20 Transfer format and timing adjustment(Example for 2nd edge sampling) ............................40
Figure 3.21 Idle state in SPI mode and the transmit pin status...............................................................42
Figure 3.22 Idle state in SIO mode and the transmit pin status...............................................................42
Figure 3.23 Circuit of interrupt request ....................................................................................................44
Figure 3.24 Overrun error and underrun error.........................................................................................46
List of Tables
Table 1.1 Functional outline (SPI mode, master) ....................................................................................10
Table 1.2 Functional outline (SPI mode, slave).......................................................................................11
Table 1.3 Functional outline (SIO mode, master)....................................................................................12
Table 1.4 Functional outline (SIO mode, slave).......................................................................................13
Table 2.1 List of Signals...........................................................................................................................15
Table 3.1Example of fclk/ΦT0/ΦTx/ transfer clock and usability.............................................................27
Table 3.2 Data format and settable fill level.............................................................................................29
Table 3.3 Usability of communication mode and data sampling timing...................................................37
Table 3.4 Data capture timing..................................................................................................................37
Table 3.5 TSPIxTXD output during idle state ..........................................................................................41
Table 3.6 Interrupt events and requests..................................................................................................44
Table 4.1 Initialized registers by software reset.......................................................................................49
Table 4.2 The timing of write "0" to <TRXE>, and state of <TSPISUE>.................................................60
Table 4.3 Current value of fill level depending on the range of <TLVL>/<RLVL>...................................60
Table 5.1 Transfer starting and stopping operation in each mode setting (Master)................................ 62
Table 7.1 Revision History.......................................................................................................................65

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Serial Peripheral Interface
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Preface
Related document
Document name
Clock Control and Operation Mode
Exception
Input/Output Ports
Product Information

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Serial Peripheral Interface
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Conventions
●Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 – It is possible to omit the “0b” when the number of bit can be distinctly
understood from a sentence.
●“_N” is added to the end of signal names to indicate low active signals.
●It is called “assert” that a signal moves to its active level, “deassert” to its inactive level.
●When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
●The characters surrounded by [ ] defines the register.
Example: [ABCD]
●“n” substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3]

[XYZn]
●"x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, “x” means A, B, and C . . .
Example: [ADACR0], [ADBCR0], [ADCCR0]

[ADxCR0]
In case of channel, “x” means 0, 1, and 2 . . .
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA]

[T32AxRUNA]
●The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
●The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> = 0x01 (hexadecimal), [XYZn]<VW> = 1 (binary)
●Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
●Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
●Unless otherwise specified, register access supports only word access.
●The register defined as reserved must not be rewritten. Moreover, do not use the read value.
●The value read from the bit having default value of "-" is unknown.
●When a register containing both of writable bits and read-only bits is written, read-only bits should be
written with their default value, In the cases that default is “-“, follow the definition of each register.
●Reserved bits of the Write-only register should be written with their default value. In the cases that default is
“-“, follow the definition of each register.
●Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

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Serial Peripheral Interface
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The flash memory uses the Super Flash® technology under license from Silicon Storage Technology, Inc.
Super Flash® is registered trademark of Silicon Storage Technology, Inc.
All other company names, product names, and service names mentioned herein may be trademarks of their respective
companies.
***********************************************************************************************************************
Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere. All rights reserved.
***********************************************************************************************************************

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Serial Peripheral Interface
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Terms and Abbreviation
Some of abbreviations used in this document are as follows:
ACK Acknowledgement
DMA Direct Memory Access
FIFO First-In First-Out
LSB Least Significant Bit
MSB Most Significant Bit
SIO Serial Input/Output
TSPI Toshiba Serial Peripheral Interface

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Serial Peripheral Interface
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Outline
TSPI(Serial Peripheral Interface) has four operation mode as SPI/SIO mode, and the clock master/ clock slave mode.
One channel/unit which is built-in TSPIxTXD,TSPIxRXD,TSPIxSCK,TSPIxCS0,TSPIxCS1, TSPIxCS2,TSPIxCS3, and
TSPIxCSIN can be transmit and receive circuit. functions are as below.

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Table 1.1 Functional outline (SPI mode, master)
Function classification Function A Functional Description or the range
SPI mode
(Master)
Transmission
Speed
Control
Prescaler dividing selection
The clock inputted from the prescaler can be
divided 1/1,1/2,1/4..up to 1/512.
Baud rate generator
The input clock to baud rate generator.
dividing 1/N x 1/2 (N= 1 to 16)
Data
Format
Data length
The data length can be setup in a 1-bit unit.
8 to 32bits (with no parity)
7 to 31bits (with parity)
Parity
Selection of with parity/without parity is possible.
Selection of even parity/odd parity is possible.
The direction of data transfer Selection of the LSB first/ MSB first is possible.
Transmit and
Receive
Control
FIFO number of section
Transmission: 8 steps (16bits), 4 steps (32bits)
Reception: 8 steps (16bits), 4 steps (32bits)
Communication Operation
mode
Full duplexes (transmission and reception),
transmission, reception
Transfer mode
Single transfer (one burst transfer)
Burst transfer (2 to 255 times transfer)
Continuously transfer (No limit of transfer times
specification)
Data sampling timing
Data is sampled with 1st edge.
Data is sampled with 2
nd
edge.
CS control
Selection of TSPIxCS0/1/2/3 is possible.
Polarity: Selection of positive logic/ negative logic is
possible.
Ganged
Control
Interruption
Transmit interrupt (Transmit completion interrupt,
Transmit FIFO interrupt)
Receive interrupt (Receive completion interrupt,
Receive FIFO interrupt)
Error Interrupt (Vertical parity error interrupt, Trigger
error interrupt)
Various status detection
TSPI modify status,
Transmit shift operation, Transmit completion,
Transmit FIFO fill level/ empty detection,
Receive operation, Receive completion, Receive
FIFO fill level /full detection
DMA request
Transmit:Single DMA request, Burst DMA request
Receive: Single DMA request, Burst DMA request
Trigger communication control
Starting communication by trigger. Refer to the
"Product Information" on a reference manual for a
trigger source.
Special
Control
Output level of TSPIxTXD
during an idle term
High, Low, a last bit data hold, Hi-z
Polarity of TSPIxSCK during
an idle term
It is Low to during idle term.
It is High to during idle term.
Interval time between frames
at the time of burst transfer. 0 x TSPIxSCK cycle to 15 x TSPIxSCK cycles
Idle time at the time of
continuously transfer
Period of changing TSPIxCS0/1/2/3 pin to asserted,
deasserted, asserted.
1 x TSPIxSCK cycle to 15 x TSPIxSCK cycles
TSPIxSCK delay of deasert
Time of delay between from TSPIxCS0/1/2/3 is
asserted to TSPIxSCK is started.
1 x TSPIxSCK cycle - a 16 x TSPIxSCK cycles
TSPIxCS0/1/2/3 deassertion
delay
Time until TSPIxCS0/1/2/3 pin is deasserted from
last data
1 x TSPIxSCK cycle to 16 x TSPIxSCK cycle
Software reset Reset by software

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Table 1.2 Functional outline (SPI mode, slave)
Function classification Function A Functional Description or the range
SPI mode
(Slave)
Data
Format
Data length
The data length can be setup in a 1-bit unit.
8 to 32bits (with no parity)
7 to 31bits (with parity)
Parity
Selection of with parity/without parity is possible.
Selection of even parity/odd parity is possible.
The direction of data transfer Selection of the LSB first/ MSB first is possible.
Transceiver
Control
FIFO number of section
Transmission: 8 steps (16bits), 4 steps (32bits)
Reception: 8 steps (16bits), 4 steps (32bits)
Communication Operation
mode
Full duplexes (transmission and reception),
transmission, reception
Transfer mode
Single transfer (one burst transfer)
Burst transfer (2 to 255 times transfer)
Continuously transfer (No limit of transfer times
specification)
Data sampling timing Data is sampled with 2nd edge.
CS control
TSPIxCSIN
Polarity: Selection of positive logic/ negative logic
is possible.
Ganged
Control
Interruption
Transmit interrupt (Transmit completion interrupt,
Transmit FIFO interrupt)
Receive interrupt (Receive completion interrupt,
Receive FIFO interrupt)
Error Interrupt (Vertical parity error interrupt, Over
run interrupt, Under run interrupt)
Various status detection
TSPI modify status,
Transmit shift operation, Transmit completion,
Transmit FIFO fill level/ empty detection,
Receive operation,Receive completion, Receive
FIFO fill level /full detection
DMA demand
Transmit:Single DMA request, Burst DMA request
Receive: Single DMA request, Burst DMA request
Special
Control
Output level of TSPIxTXD
during an idle term
High, Low, a last bit data hold, Hi-z
Output level of TSPIxTXD
when underrun error occurred
High, Low
Software reset Reset by software.

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Table 1.3 Functional outline (SIO mode, master)
Function classification Function A Functional Description or the range
SIO mode
(Master)
Transmission
speed
Control
Prescaler dividing selection
The clock inputted from the prescaler can be
divided 1/1,1/2,1/4..up to 1/512.
Baud rate generator
The input clock to baud rate generator.
dividing 1/N x 1/2 (N= 1 to 16)
Data
Format
Data length
The data length can be setup in a 1-bit unit.
8 to 32bits (with no parity)
7 to 31bits (with parity)
Parity
Selection of with parity/without parity is possible.
Selection of even parity/odd parity is possible.
The direction of data transfer Selection of the LSB first/ MSB first is possible.
Transceiver
Control
FIFO number of section
Transmission: 8 steps (16bits), 4 steps (32bits)
Reception: 8 steps (16bits), 4 steps (32bits)
Communication Operation
mode
Full duplexes (transmission and reception),
transmission, reception
Transfer mode
Single transfer (one burst transfer)
Burst transfer (2 to 255 times transfer)
Continuously transfer (No limit of transfer times
specification)
Data sampling timing Data is sampled with 2nd edge.
Ganged
Control
Interruption
Transmit interrupt (Transmit completion interrupt,
Transmit FIFO interrupt)
Receive interrupt (Receive completion interrupt,
Receive FIFO interrupt)
Error Interrupt (Vertical parity error interrupt,
Trigger error interrupt)
Various status detection
TSPI modify status,
Transmit shift operation, Transmit completion,
Transmit FIFO fill level/ empty detection,
Receive operation,Receive completion, Receive
FIFO fill level /full detection
DMA demand
Transmit:Single DMA request, Burst DMA request
Receive: Single DMA request, Burst DMA request
Trigger communication control
Starting communication by trigger. Refer to the
"Product Information" on a reference manual for a
trigger source.
Special
Control
Output level of TSPIxTXD
during an idle term
High, Low, a last bit data hold, Hi-z
Polarity of TSPIxSCK during an
idle term
It is Low to during idle term.
It is High to during idle term.
Interval time between frames at
the time of burst transfer.
0 x TSPIxSCK cycle to 15 x TSPIxSCK cycles
Idle time at the time of
continuously transfer
1 x TSPIxSCK cycle to 15 x TSPIxSCK cycles
Software reset Reset by software is possible.

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Table 1.4 Functional outline (SIO mode, slave)
Function classification Function A Functional Description or the range
SIO mode
(Slave)
Data
Format
Data length
The data length can be setup in a 1-bit unit.
8 to 32bits (with no parity)
7 to 31bits (with parity)
Parity
Selection of with parity/without parity is possible.
Selection of even parity/odd parity is possible.
The direction of data transfer Selection of the LSB first/ MSB first is possible.
Transceiver
Control
FIFO number of section
Transmission: 8 steps (16bits), 4 steps (32bits)
Reception: 8 steps (16bits), 4 steps (32bits)
Communication Operation
mode
Full duplexes (transmission and reception),
transmission, reception
Transfer mode
Single transfer (one burst transfer)
Burst transfer (2 to 255 times transfer)
Continuously transfer (No limit of transfer times
specification)
Data sampling timing Data is sampled with 2nd edge.
Ganged
Control
Interruption
Transmit interrupt (Transmit completion interrupt,
Transmit FIFO interrupt)
Receive interrupt (Receive completion interrupt,
Receive FIFO interrupt)
Error Interrupt (Vertical parity error interrupt, Over
run interrupt, Under run interrupt)
Various status detection
TSPI modify status,
Transmit shift operation, Transmit completion,
Transmit FIFO fill level/ empty detection,
Receive operation,Receive completion, Receive
FIFO fill level /full detection
DMA demand
Transmit:Single DMA request, Burst DMA request
Receive: Single DMA request, Burst DMA request
Special
Control
Final bit hold time of a
TSPIxTXD pin
2/fclk to 128/fclk (Note)
Output level of TSPIxTXD
during an idle term
High, Low, a last bit data hold, Hi-z
Output level of TSPIxTXD
when underrun error occurred
High, Low
Software reset Reset by software is possible.
Note: fclk is either the system clock (fsys) or high speed clock (fc), depending on the product. For the details, refer to
“Product Information” in Reference manual.

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Configuration
The block diagram of the TSPI and the signal list are shown.
ΦTx
TSPIxSCK
TSPIxTXD
Baud Rate
Generator
Transmit Counter
Clock for pre-scalar
ΦT0
TSPI Control
Register 0
[TSPIxCR0]
Pre-scalar
CS Control
Clock
Control
TSPI Control
Register 1
[TSPIxCR1]
TSPI Control
Register 2
[TSPIxCR2]
TSPI Control
Register 3
[TSPIxCR3]
TSPI Baud Rate
Register
[TSPIxBR]
TSPI Format Control
Register 0
[TSPIxFMTR0]
TSPI Format Control
Register 1
[TSPIxFMTR1]
TSPI Data Register
[TSPIxDR]
TSPI Error Flag
Register 1
[TSPIxERR]
TSPI Status Register
[TSPIxSR]
DMA
Control
Interrupt
Control
Transmit DMA request
TSPIxTX_DMA
Receive DMA request
TSPIxRX_DMA
Error Interrupt request
INTTxERR
Transmit Control
Transmit Data Length
Control Counter Transmit FIFO Transmit Shift Register
Receive Control
Receive Counter
Receive data Length
Control Register Receive FIFO Receive Shift Register TSPIxRXD
TSPIxCS1
TSPIxCS2
TSPIxCS3
TSPIxCS0/TSPIxCSIN
1/2
Trigger input for
start transition
TSPIxTRG
Receive interrupt request
INTTxRX
Transmitinterrupt request
INTTxTX
TransmitCompletion
TSPIxTXEND
Receive Completion
TSPIxRXEND
<SWRST>
<SWRST>
Operation clock
f
clk
Figure 2.1 Block diagram of TSPI
Note: Regarding to product, TSPIxCS0 and TSPIxCSIN may be assigned to a different pin. For details, refer to
"Input/Output Ports" of reference manual.
(Note)

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Table 2.1 List of Signals
No
Signal symbol
Signal name
I/O
Reference manual
1 fclk (Note) Operation clock Input
Clock Control and Operation Mode
Product Information
2
ΦT0
Clock for prescaler
Input
Clock Control and Operation Mode
3 TSPIxSCK Serial clock output/ Serial clock input Input/Output Input/Output Ports
4 TSPIxCS0 Chip select 0 Output Input/Output Ports
5 TSPIxCS1 Chip select 1 Output Input/Output Ports
6
TSPIxCS2
Chip select 2
Output
Input/Output Ports
7 TSPIxCS3 Chip select 3 Output Input/Output Ports
8
TSPIxCSIN
Chip select input for slave operation
Input
Input/Output Ports
9
TSPIxTXD
Serial data of transmission
Output
Input/Output Ports
10
TSPIxRXD
Serial data of reception
Input
Input/Output Ports
11
INTTxTX
Transmit interrupt request
Output
Exception
12
INTTxRX
Receive interrupt request
Output
Exception
13
INTTxERR
Error interrupt request
Output
Exception
14
TSPIxTRG
Trigger input for start communication
Input
Product Information
15
TSPIxTX_DMA
Transmit DMA request
Output
Product Information
16
TSPIxRX_DMA
Receive DMA request
Output
Product Information
17
TSPIxTXEND
Transmit Completion
Output
Product Information
18
TSPIxRXEND
Receive Completion
Output
Product Information
Note: fclk is either the system clock (fsys) or high speed clock (fc), depending on the product. For the details, refer to
“Product Information” in Reference manual.

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Operation description
3.1. Basic operation
3.1.1. Clock supply
When TSPI is used, the corresponding clock enable bits should be set to “1” (Clock supply) in fsys supply stop
register A ([CGFSYSENA] and [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB] and
[CGFSYSMENB]), and fc supply stop register ([CGFCEN]). The corresponding registers and the bit locations
depend on a product. Some products do not have all registers. For the details, refer to “Clock Control and
Operation Mode” in Reference manual.
When stopping supply of a clock, please check that TSPI has stopped ([TSPIxCR0]<TSPIE>=0 (TSPI control)).
Moreover, also when you change operational mode to STOP1/STOP2, please check that TSPI has stopped.
3.1.2. Initial setting of TSPI
First, [TSPIxCR0]<TSPIE>(TSPI operation control) set as "1". Please perform needed setup, such as
communicate mode, transfer mode, and a transfer format, after checking that [TSPIxSR]<TSPISUE>(TSPI
modify status flag) is "0".
3.1.3. Start and stop transfer
There are two methods for a transfer start in the case of full duplex communication mode and transmitting mode.
1. Write Data to data register [TSPIxDR],after wrote “1” to [TSPIxCR1] <TRXE> for enable
communication.
2. Write “1” to [TSPIxCR1]<TRXE>, after wrote data to data register [TSPIxDR].
In the case of receiving mode, reception is started shortly after setting to [TSPIxCR1]<TRXE>=1.
In order to stop transfer, please set "0" to [TSPIxCR1]<TRXE>. In single transfer burst transfer and continuously
transfer, transfer is performed to the last of the frame under transfer.,
After stopped, TSPIxSCK,TSPIxCS0/1/2/3,and TSPIxTXD will be in an idle state. Please refer to “3.3.7. Special
control”.
If a transfer is enabled again after stopping transfer in a burst mode, operation will be started from the beginning
of the stopped burst transfer.

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3.2. Data Format
When specifying the transfer direction MSB/LSB first and frame length, set up [TSPIxFMTR0](TSPI format
control register 0). When specifying the enable parity and even/odd parity, set up [TSPIxFMTR1](TSPI format
control register 1).
Note: When the parity function is enabled, data length is 31 bits at maximum.
Figure 3.1 Data format

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3.2.1. Data Format without Parity
If data format is without parity bit, the length of frame must be the same as the length of data. For example, when
the length of data is 10-bit, set "001010" to [TSPIxFMTR0]<FL[5:0]>. The data in the transmit FIFO is
transferred remaining unchanged to the shift register.
(1) MSB First Transfer (32-bit data, without parity, 32-bit frame length)
Figure 3.2 shows a transmit/receive operation (without parity, MSB first, 32-bit data length).
In the transmission, data in the transmit FIFO is copied to D31 through D0 in the shift register.
Transmit data copied to shift register is transferred sequentially from D31 through D0 on serial clock.
In the reception, receive data is stored in the D0 of the shift register. Shift operation repeats on serial clock.
If the shift register stores 32-bit reception data, data is copied to the receive FIFO.
Figure 3.2 MSB first (32-bit data without a parity bit)
[TSPIxDR] (Data register)
[TSPIxDR] (Data register)

TXZ Family
Serial Peripheral Interface
2019-02-28 19 / 67 Rev. 3.0
(2) MSB First Transfer (16-bit data without a parity bit, 16-bit data frame length)
Figure 3.3 shows a transmit/receive operation (without parity, MSB first, 32-bit data length).
In the transmission, data in the transmit FIFO is copied to D15 through D0 in the shift register.
Transmit data copied to shift register is transferred sequentially from D15 through D0 on serial clock.
In the reception, receive data is stored in the D0 of the shift register. Shift operation repeats on serial clock.
If the shift register stores 16-bit reception data, data is copied to the receive FIFO.
Figure 3.3 MSB first (16-bit data without a parity bit)
[TSPIxDR] (Data register)
[TSPIxDR] (Data register)

TXZ Family
Serial Peripheral Interface
2019-02-28 20 / 67 Rev. 3.0
(3) LSB First Transfer (32-bit data without a parity bit, 32-bit frame length)
Figure 3.4 shows a 32-bit data length transmit/receive operation when parity function is disabled.
In the transmission, data in the transmit FIFO is sorted bit by bit when the data is copied to the shift register.
Transmit data copied to the shift register is transferred from D0 until reaching 32-bit shifted data on serial
clock.
In the reception, receive data is stored in D31 of the shift register. Shift operation repeats on serial clock. If
the shift register stores 32-bit reception data, data is sorted bit by bit and copied to the receive FIFO.
Figure 3.4 LSB first (32-bit data without a parity bit)
[TSPIxDR] (Data register)
[TSPIxDR] (Data register)