Texas Instruments MSPM0G310 Series User manual

MSPM0G310x Mixed-Signal Microcontrollers with CAN-FD Interface
1 Features
•Core
– Arm® 32-bit Cortex®-M0+ CPU with memory
protection unit, frequency up to 80 MHz
•Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62 V to 3.6 V
•Memories
– Up to 128KB of flash memory with built-in error
correction code (ECC)
– Up to 32KB of ECC protected SRAM with
hardware parity
•High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADC's) with up to
11 external channels
• 14-bit effective resolution at 250-ksps with
hardware averaging
– One general-purpose amplifier (GPAMP)
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
•Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 458 µA at 4 MHz
– STOP: 47 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 78 nA with IO wakeup capability
•Intelligent digital peripherals
– 7-channel DMA controller
– Two 16-bit advanced control timers supporting
dead band insertion and fault handling
– Seven timers supporting up to 22 PWM
channels
• One 16-bit general purpose timer
• One 16-bit general purpose timer supports
QEI
• Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
• One 32-bit general-purpose timer
• Two 16-bit advanced timers with deadband
– Two window-watchdog timers
– RTC with alarm and calendar mode
•Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
– Two I2C interfaces supporting up to FM+
(1 Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Two SPI interfaces, with one SPI interface
supporting upto 32Mbits/s
– One Controller Area Network (CAN) interface
supports CAN 2.0 A or B and CAN-FD
•Clock system
– Internal 4- to 32-MHz oscillator with upto ±1.2%
accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz oscillator (LFOSC)
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
•Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128 or 256-bit key
•Flexible I/O features
– Up to 28 GPIOs
• Two 5-V tolerant IOs
• Two high-drive IOs with 20-mA drive
strength
•Development support
– 2-pin serial wire debug (SWD)
•Package options
– 32-pin VQFN
– 28-pin VSSOP
– 20-pin VSSOP
•Family members (also see Device Comparison)
– MSPM0G3105: 32KB flash, 16KB RAM
– MSPM0G3106: 64KB flash, 32KB RAM
– MSPM0G3107: 128KB flash, 32KB RAM
•Development kits and software (also see Tools
and Software)
–LP-MSPM0G3507 LaunchPad™ development
kit
– MSP Software Development Kit (SDK)
2 Applications
•Motor control
•Home appliances
•Uninterruptible power supplies and inverters
•Electronic point of sale systems
•Medical and healthcare
•Test and measurement
•Factory automation and control
•Industrial transport
•Grid infrastructure
•Smart metering
ADVANCE INFORMATION
MSPM0G3107, MSPM0G3106, MSPM0G3105
SLASF12A – FEBRUARY 2023 – REVISED JUNE 2023
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.

•Communication modules •Lighting
3 Description
MSPM0G310x microcontrollers (MCUs) are part of the MSP highly-integrated, ultra-low-power 32-bit MCU
family based on the enhanced Arm® Cortex®-M0+ 32-bit core platform operating at up to 80-MHz frequency.
These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature
ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V.
The MSPM0G310x devices provide up to 128KB embedded flash program memory with built-in error correction
code (ECC) and up to 32KB SRAM with ECC and hardware parity option. They also incorporate a memory
protection unit, 7-channel DMA, and a variety of high-performance analog peripherals such as as two 12-bit
4-Msps ADCs, configurable internal shared voltage reference, and one general-purpose amplifier. These devices
also offer intelligent digital peripherals such as two 16-bit advanced control timers, five general purpose timers
(with one 16-bit general-purpose timer for QEI interface, two 16-bit general-purpose timers for STANDBY mode,
and one 32-bit general-purpose timer), two windowed-watchdog timers, and one RTC with alarm and calendar
mode. These devices provide data integrity and encryption peripherals (CRC, TRNG, AES) and enhanced
communication interfaces (four UART, two I2C, two SPI, CAN 2.0/FD).
The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital
integration allowing for customers find the MCU that meets their project's needs. The MSPM0 MCU platform
combines the Arm Cortex-M0+ platform with a holistic ultra-low-power system architecture, allowing system
designers to increase performance while reducing energy consumption.
MSPM0G310x MCUs are supported by an extensive hardware and software ecosystem with reference designs
and code examples to get the design started quickly. Development kits include a LaunchPad available for
purchase. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of
Code Composer Studio™ IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are
also supported by extensive online collateral, training with MSP Academy, and online support through the TI
E2E™ support forums.
For complete module descriptions, see the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Manual.
CAUTION
System-level ESD protection must be applied in compliance with the device-level ESD specification
to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level
ESD Considerations for more information. The principles in this application note are applicable to
MSPM0 MCUs.
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4 Functional Block Diagram
Figure 4-1 shows the MSPM0G310x functional block diagram.
CPU SUB SYSTEM
Arm
Cortex-M0+
fmax = 80 MHz
NVIC
MPU
SWD + MTB
IOPORT
AHB BUS (MCLK)
CPU-ONLY PD1 PERIPHERAL BUS (MCLK)
DMA
7-ch
PD1 PERIPHERAL BUS (MCLK)
AES
CRC
TRNG
GPIO
tIOBUSt
PD0 PERIPHERAL BUS (ULPCLK)
12b ADC0
12b ADC1
TIMG0
TIMG8
UART0
I2C0
I2C1
IOMUX
PMCU (SYSCTL) GPAMP
FLASHCTL
ULPCLK
ULPCLK
PD1, CPU ACCESS ONLY
PD1, CPU/DMA ACCESS
PD1/PD0, CPU/DMA ACCESS
PD0, CPU/DMA ACCESS
LEGEND
EVENTRTC
WWDT0
WWDT1
UART1
UART2
VREF
PD0 PERIPHERAL BUS (ULPCLK)
TEMP SENSOR
SYSOSC
SYSPLL
LFXT
HFXT
LFOSC
CKM
LDO
PMU
BOR
POR
VBOOST
DEBUG
RTC_OUT
TX, RX,
CTS, RTS
TX, RX,
CTS, RTS
SDA, SCL
2-CH
IN+, IN-,
OUT
VREF+,
VREF-
A0_x
A1_x
PAx, PBx
LFXIN, LFXOUT
HFXIN, HFXOUT
ROSC
CLK_OUT, FCC_IN
VDD, VSS
VCORE, NRST
2-CH
QEI/HALL
SPI0
SPI1
UART3
CAN-FD
TIMA0
TIMA1
TIMG6
TIMG7
TIMG12
32-bit 2-CH
2-CH
2-CH
2-CH
FAULT
4-CH
FAULT
TX, RX,
CTS, RTS
TX, RX
FLASH
Up to 128KB
SRAM
Up to 32KB
ROM
BCR, BSL
POCI, PICO,
SCK, CSx
SWCLK,
SWDIO
Figure 4-1. MSPM0G310x Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Device Comparison.........................................................5
6 Pin Configuration and Functions...................................6
6.1 Pin Diagrams.............................................................. 6
6.2 Pin Attributes...............................................................9
6.3 Signal Descriptions................................................... 12
6.4 Connections for Unused Pins................................... 19
7 Specifications................................................................ 20
7.1 Absolute Maximum Ratings...................................... 20
7.2 ESD Ratings............................................................. 20
7.3 Recommended Operating Conditions.......................20
7.4 Thermal Information..................................................21
7.5 Supply Current Characteristics................................. 22
7.6 Power Supply Sequencing........................................23
7.7 Flash Memory Characteristics.................................. 24
7.8 Timing Characteristics...............................................25
7.9 Clock Specifications..................................................26
7.10 Digital IO................................................................. 28
7.11 Analog Mux VBOOST............................................. 31
7.12 ADC........................................................................ 31
7.13 Temperature Sensor............................................... 33
7.14 VREF...................................................................... 33
7.15 GPAMP................................................................... 34
7.16 I2C.......................................................................... 35
7.17 SPI.......................................................................... 35
7.18 UART...................................................................... 37
7.19 TIMx........................................................................38
7.20 TRNG......................................................................38
7.21 Emulation and Debug............................................. 38
8 Detailed Description......................................................39
8.1 CPU.......................................................................... 39
8.2 Operating Modes...................................................... 39
8.3 Power Management Unit (PMU)...............................41
8.4 Clock Module (CKM).................................................41
8.5 DMA..........................................................................42
8.6 Events.......................................................................43
8.7 Memory.....................................................................43
8.8 Flash Memory........................................................... 46
8.9 SRAM........................................................................47
8.10 GPIO.......................................................................47
8.11 IOMUX.................................................................... 47
8.12 ADC........................................................................ 47
8.13 Temperature Sensor............................................... 48
8.14 VREF...................................................................... 48
8.15 GPAMP................................................................... 48
8.16 TRNG......................................................................49
8.17 AES.........................................................................49
8.18 CRC........................................................................ 49
8.19 UART...................................................................... 49
8.20 I2C.......................................................................... 50
8.21 SPI.......................................................................... 50
8.22 CAN-FD.................................................................. 51
8.23 WWDT.................................................................... 51
8.24 RTC.........................................................................51
8.25 Timers (TIMx)..........................................................51
8.26 Device Analog Connections....................................54
8.27 Input/Output Diagrams............................................55
8.28 Serial Wire Debug Interface....................................56
8.29 Boot Strap Loader (BSL).........................................56
8.30 Device Factory Constants ......................................56
8.31 Identification............................................................57
9 Applications, Implementation, and Layout................. 58
9.1 Typical Application.................................................... 58
10 Device and Documentation Support..........................59
10.1 Getting Started and Next Steps.............................. 59
10.2 Device Nomenclature..............................................59
10.3 Tools and Software................................................. 60
10.4 Documentation Support.......................................... 61
10.5 Support Resources................................................. 61
10.6 Trademarks.............................................................61
10.7 Electrostatic Discharge Caution..............................61
10.8 Glossary..................................................................61
11 Mechanical, Packaging, and Orderable
Information.................................................................... 62
12 Revision History.......................................................... 62
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5 Device Comparison
Device Comparison
DEVICE NAME (1) (4) FLASH / SRAM
(KB) QUAL(2) ADC / CHAN GPAMP UART / I2C / SPI CAN TIMA TIMG GPIO PACKAGE [PACKAGE SIZE] (3)
MSPM0G3105SRHB 32 / 16
S 2 / 11 1 4 / 2 / 2 1 2 5 28 32 VQFN
[5 mm × 5 mm]
MSPM0G3106SRHB 64 / 32
MSPM0G3107SRHB 128 / 32
MSPM0G3105SDGS28 32 / 16
S 2 / 11 1 4 / 2 / 2 1 2 5 24 28 VSSOP
[7.1 mm × 4.9 mm]
MSPM0G3106SDGS28 64 / 32
MSPM0G3107SDGS28 128 / 32
MSPM0G3105SDGS20 32 / 16
S 2 / 6 1 4 / 2 / 2 1 2 5 16 20 VSSOP
[5.1 mm × 4.9 mm]
MSPM0G3106SDGS20 64 / 32
MSPM0G3107SDGS20 128 / 32
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 11, or see the TI website.
(2) Device Qualifications:
• S = –40°C to 125°C
(3) The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section 11.
(4) For more infromation about the device name, see Section 10.2.
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6 Pin Configuration and Functions
The System Configuration tool provides a graphical interface to enable, configurable, and generate initialization
code for pin multiplexing and simplifying pin settings. The pin diagrams shown in the data sheet show the
primary peripheral functions, some of the integrated device features, and available clock signals to simplify the
device pinout.
For full descriptions of the pin functions, see the Pin Attributes and Signal Descriptions sections.
6.1 Pin Diagrams
Power
Reset
High-Speed I/O (HSIO)
5-V Tolerant Open-Drain I/O (ODIO)
High-Drive I/O (HDIO)
Figure 6-1. Pin Diagram Color Coding
VQFN32
Thermal pad
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
NRST
VDD
VSS
VCORE
PA0 / FCC_IN
PA1
PA2 / ROSC
PA3 / LFXIN
PA4 / LFCLK_IN / LFXOUT
PA5 / HFXIN / FCC_IN
PA6 / HFCLK_IN / HFXOUT
PA7 / CLK_OUT
PA8
PA9 / RTC_OUT / CLK_OUT
PA10 / CLK_OUT
PA11
PA12 / FCC_IN
PA20 / SWCLK
PA19 / SWDIO
PA18 / A1_3
PA17 / A1_2
PA16 / A1_1/ FCC_IN
PA15 / A1_0
PA14 / CLK_OUT / A0_12
PA13
PA27 / RTC_OUT / A0_0
PA26 / A0_1 PA25 / A0_2 PA24 / A0_3 PA22 / A0_7
PA21 / A1_7 / VREF-
PA23 / VREF+
Figure 6-2. 32-Pin RHB(VQFN) (Top View)
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VSSOP28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PA20 / SWCLK
PA19 / SWDIO
VCORE
NRST
VDD
VSS
PA0
PA1
PA2 / ROSC
PA3 / LFXIN
PA4 / LFCLK_IN / LFXOUT
PA5 / HFXIN / FCC_IN
PA6 / HFCLK_IN / HFXOUT
PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT
PA11
PA16 / A1_1 / FCC_IN
PA15 / A1_0
PA14 / CLK_OUT / A0_12
PA18 / A1_3
PA17 / A1_2
PA25 / A0_2
PA24 / A0_3
PA22 / CLK_OUT / A0_7
PA21 / A1_7 / VREF-
PA27 / RTC_OUT / A0_0
PA26 / A0_1
PA23 / VREF+
Figure 6-3. 28-Pin DGS28(VSSOP) (Top View)
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VSSOP20
20
19
18
17
16
15
14
13
12
11
PA20 / SWCLK
PA19 / SWDIO
VCORE
NRST
VDD
VSS
PA2 / ROSC
PA5 / HFXIN / FCC_IN
PA6 / HFCLK_IN / HFXOUT
PA9 / RTC_OUT / CLK_OUT
PA18 / A1_3
PA17 / A1_2
PA24 / A0_3
PA22 / CLK_OUT / A0_7
PA27 / RTC_OUT / A0_0
PA26 / A0_1
PA23 / VREF+
PA12 / FCC_IN
PA10 / CLK_OUT
PA11
1
2
3
4
5
6
7
8
9
10
Figure 6-4. 20-Pin DGS20 (VSSOP) (Top View)
Note
For full pin configuration and functions for each package option, refer to Pin Attributes and Signal
Descriptions.
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6.2 Pin Attributes
The following table describes the functions available on every pin for each device package.
Note
Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that
lets users configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1. Pin Attributes
PINCMx PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTURE
ANALOG DIGITAL [PIN FUNCTION] (1)
32 VQFN
28 VSSOP 20 VSSOP
N/A VDD 4 7 5 Power
N/A VSS 5 8 6 Power
N/A VCORE 32 3 3 Power
N/A NRST 3 6 4 Reset
1PA0 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C0 [4] /
TIMA_FAL1 [5] / TIMG8_C1 [6] / FCC_IN [7] 1 4 – 5V Tol. Open- Drain
2PA1 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C1 [4] /
TIMA_FAL2 [5] / TIMG8_IDX [6] / TIMG8_C0 [7] 2 5 – 5V Tol. Open- Drain
3PA28 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C3 [4] /
TIMA_FAL0 [5] / TIMG7_C0 [6] / TIMA1_C0 [ 7] – – – High-Drive
4PA29 I2C1_SCL [2] / UART2_RTS [3] / TIMG8_C0 [4] /
TIMG6_C0 [5] – – – Standard
5PA30 I2C1_SDA [2] / UART2_CTS [3] / TIMG8_C1 [4] /
TIMG6_C1 [5] – – – Standard
6
PA31 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C3N [4] /
TIMG12_C1 [5] / CLK_OUT [6]/ TIMG7_C1 [7] /
TIMA1_C1 [8]
– – – High-Drive
7PA2 ROSC TIMG8_C1 [2] / SPI0_CS0 [3] / TIMG7_C1 [4] / SPI1_CS0
[5] 6 9 7 Standard
8
PA3
LFXIN
TIMG8_C0 [2] / SPI0_CS1 [3] / UART2_CTS [4] /
TIMA0_C2 [5] / TIMG7_C0 [7] / TIMA0_C1 [8] / I2C1_SDA
[9]
7 10 – Standard
9
PA4
LFXOUT
TIMG8_C1 [2] / SPI0_POCI [3] / UART2_RTS
[4] / TIMA0_C3 [5] / LFCLK_IN [6] / TIMG7_C1 [7] /
TIMA0_C1N [8] / I2C1_SCL [9]
8 11 – Standard
10 PA5 HFXIN TIMG8_C0 [2] / SPI0_PICO [3] / TIMA_FAL1 [4] /
TIMG0_C0 [5] / TIMG6_C0 [6] / FCC_IN [7] 9 12 8 Standard
11
PA6
HFXOUT
TIMG8_C1 [2] / SPI0_SCK [3] / TIMA_FAL0 [4] /
TIMG0_C1 [5] / HFCLK_IN [6] / TIMG6_C1 [ 7] /
TIMA0_C2N [8]
10 13 9 Standard
12 PB0 UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] /
TIMA0_C2 [5] – – – Standard
13 PB1 UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] /
TIMA0_C2N [5] – – – Standard
14 PA7 CLK_OUT [3] / TIMG8_C0 [4] / TIMA0_C2 [5] /
TIMG8_IDX [6] / TIMG7_C1 [7] / TIMA0_C1 [8] 11 – – Standard
15
PB2 UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] /
TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] /
TIMA1_C0 [8]
– – – Standard
16
PB3 UART3_RX [2] / UART2_RTS [3] / I2C1_SDA [4] /
TIMA0_C3N[5] / UART1_RTS [6] / TIMG6_C1 [7] /
TIMA1_C1 [8]
– – – Standard
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Table 6-1. Pin Attributes (continued)
PINCMx PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTURE
ANALOG DIGITAL [PIN FUNCTION] (1)
32 VQFN
28 VSSOP 20 VSSOP
17 PB4 UART1_TX [2] / UART3_CTS [3] / TIMA1_C0 [4] /
TIMA0_C2 [5] / TIMA1_C0N [6] – – – Standard
18 PB5 UART1_RX [2] / UART3_RTS [3] / TIMA1_C1 [4] /
TIMA0_C2N [5] / TIMA1_C1N [6] – – – Standard
19 PA8 UART1_TX [2] / SPI0_CS0 [3] / UART0_RTS [4] /
TIMA0_C0 [5] / TIMA1_C0N [6] 12 – – Standard
20
PA9 UART1_RX [2] / SPI0_PICO [3] / UART0_CTS [4] /
TIMA0_C1 [5] / RTC_OUT [6] / TIMA0_C0N [7] /
TIMA1_C1N [8] / CLK_OUT [9]
13 14 10 High-Speed
21
PA10 UART0_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] /
TIMA1_C0 [5] / TIMG12_C0 [6] / TIMA0_C2 [7] /
I2C1_SDA [8] / CLK_OUT [9]
14 15 11 High-Drive
22 PA11 UART0_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] /
TIMA1_C1 [5] / TIMA0_C2N [7] / I2C1_SCL [8] 15 16 12 High-Drive
23
PB6 UART1_TX [2] / SPI1_CS0 [3] / SPI0_CS1 [4] /
TIMG8_C0 [5] / UART2_CTS [6] / TIMG6_C0 [7] /
TIMA1_C0N [8]
– – – Standard
24
PB7 UART1_RX [2] / SPI1_POCI [3] / SPI0_CS2 [4] /
TIMG8_C1 [5] / UART2_RTS [6] / TIMG6_C1 [7] /
TIMA1_C1N [8]
– – – Standard
25 PB8 UART1_CTS [2] / SPI1_PICO [3] / TIMA0_C0 [4] – – – Standard
26 PB9 UART1_RTS [2] / SPI1_SCK [3] / TIMA0_C1 [4] /
TIMA0_C0N [5] – – – Standard
27 PB10 TIMG0_C0 [2] / TIMG8_C0 [3] / TIMG6_C0 [5] – – – Standard
28 PB11 TIMG0_C1 [2] / TIMG8_C1 [3] / CLK_OUT [4] /
TIMG6_C1 [5] – – – Standard
29 PB12 UART3_TX [2] / TIMA0_C2 [3] / TIMA_FAL1 [4] /
TIMA0_C1 [5] – – – Standard
30 PB13 UART3_RX [2] / TIMA0_C3 [3] / TIMG12_C0 [4] /
TIMA0_C1N [5] – – – Standard
31 PB14 SPI1_CS3 [2] / SPI1_POCI [3] / SPI0_CS3 [4] /
TIMG12_C1 [5] / TIMG8_IDX [6] / TIMA0_C0 [7] – – – Standard
32 PB15 UART2_TX [2] / SPI1_PICO [3] / UART3_CTS [4] /
TIMG8_C0 [5] / TIMG7_C0 [6] – – – Standard
33 PB16 UART2_RX [2] / SPI1_SCK [3] / UART3_RTS [4] /
TIMG8_C1 [5] / TIMG7_C1 [6] – – – Standard
34 PA12 UART3_CTS [2] / SPI0_SCK [3] / TIMG0_C0 [4] /
CAN_TX [5] / TIMA0_C3 [6] / FCC_IN [7] 16 – 13 High-Speed
35 PA13 UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] /
TIMG0_C1 [5] / CAN_RX [6] / TIMA0_C3N [7] 17 – – High-Speed
36 PA14 A0_12 UART0_CTS [2] / SPI0_PICO [3] / UART3_TX [4] /
TIMG12_C0 [5] / CLK_OUT [6] 18 17 – High-Speed
37
PA15
A1_0
UART0_RTS [2] / SPI1_CS2 [3] / I2C1_SCL [4] /
TIMA1_C0 [5] / TIMG8_IDX [6] / TIMA1_C0N [7] /
TIMA0_C2 [8]
19 18 – Standard
38 PA16 A1_1 SPI1_POCI [3] / I2C1_SDA [4] / TIMA1_C1 [5] /
TIMA1_C1N [6] / TIMA0_C2N [7] / FCC_IN [8] 20 19 – Standard
39 PA17 A1_2 UART1_TX [2] / SPI1_SCK [3] / I2C1_SCL [4] / TIMA0_C3
[5] / TIMG7_C0 [6] / TIMA1_C0 [7] 21 20 14 Standard with wake(2)
40 PA18 A1_3 / GPAMP_IN- UART1_RX [2] / SPI1_PICO [3] / I2C1_SDA [4] /
TIMA0_C3N [5] / TIMG7_C1 [6] / TIMA1_C1 [7] 22 21 15 Standard with wake(2)
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Table 6-1. Pin Attributes (continued)
PINCMx PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTURE
ANALOG DIGITAL [PIN FUNCTION] (1)
32 VQFN
28 VSSOP 20 VSSOP
41 PA19 SWDIO [2] 23 22 16 High-Speed
42 PA20 SWCLK [2] 24 23 17 Standard
43 PB17 A1_4 UART2_TX [2] / SPI0_PICO [3] / SPI1_CS1 [4] /
TIMA1_C0 [5] / TIMA0_C2 [6] – – – Standard
44 PB18 A1_5 UART2_RX [2] / SPI0_SCK [3] / SPI1_CS2 [4] /
TIMA1_C1 [5] / TIMA0_C2N [6] – – – Standard
45 PB19 A1_6 SPI0_POCI [3] / TIMG8_C1 [4] / UART0_CTS [5] /
TIMG7_C1 [6] – – – Standard
46 PA21 A1_7 / VREF- UART2_TX [2] / TIMG8_C0 [3] / UART1_CTS [4] /
TIMA0_C0 [5] / TIMG6_C0 [6] 25 24 – Standard
47
PA22
A0_7 / GPAMP_OUT
UART2_RX [2] / TIMG8_C1 [3] / UART1_RTS [4] /
TIMA0_C1 [5] / CLK_OUT [6] / TIMA0_C0N [7] /
TIMG6_C1 [8]
26 25 18 Standard
48
PB20
A0_6
SPI0_CS2 [2] / SPI1_CS0 [3] / TIMA0_C2 [4] /
TIMG12_C0 [5] / TIMA_FAL1 [6] / TIMA0_C1 [7] /
TIMA1_C1N [8]
– – – Standard
49 PB21 SPI1_POCI [2] / TIMG8_C0 [3] – – – Standard
50 PB22 SPI1_PICO [2] / TIMG8_C1 [3] – – – Standard
51 PB23 SPI1_SCK [2] / TIMA_FAL0 [4] – – – Standard
52 PB24 A0_5 SPI0_CS3 [2] / SPI0_CS1 [3] / TIMA0_C3 [4] /
TIMG12_C1 [5] / TIMA0_C1N [6] / TIMA1_C0N [7] – – – Standard
53
PA23
VREF+
UART2_TX [2] / SPI0_CS3 [3] / TIMA0_C3 [4] /
TIMG0_C0 [5] / UART3_CTS [6] / TIMG7_C0 [7]/
TIMG8_C0 [8]
27 26 19 Standard
54
PA24
A0_3
UART2_RX [2] / SPI0_CS2 [3] / TIMA0_C3N [4] /
TIMG0_C1 [5] / UART3_RTS [6] / TIMG7_C1 [7] /
TIMA1_C1 [8]
28 27 20 Standard
55 PA25 A0_2 UART3_RX [2] / SPI1_CS3 [3] / TIMG12_C1 [4] /
TIMA0_C3 [5] / TIMA0_C1N [6] 29 28 – Standard
56 PB25 A0_4 UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4] – – – Standard
57 PB26 UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] /
TIMG6_C0 [5] / TIMA1_C0 [6] – – – Standard
58 PB27 SPI1_CS1 [3] / TIMA0_C3N [4] / TIMG6_C1 [5] /
TIMA1_C1 [6] – – – Standard
59 PA26 A0_1 / GPAMP_IN+ UART3_TX [2] / SPI1_CS0 [3] / TIMG8_C0 [4] /
TIMA_FAL0 [5] / CAN_TX [6] / TIMG7_C0 [7] 30 1 1 Standard
60 PA27 A0_0 RTC_OUT [2] / SPI1_CS1 [3] / TIMG8_C1 [4] /
TIMA_FAL2 [5] / CAN_RX [6] / TIMG7_C1 [7] 31 2 2 Standard
(1) PINCM.PF and PINCM.PC in IOMUX should be set to 0 for analog functions (i.e. OPA inputs/outputs, COMP inputs, etc.). Each digital
I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin
Function using the PINCM.PF control bits.
(2) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured
to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80-MHz Microcontrollers
Technical Reference Manual for details.
Table 6-2. Digital IO Features by IO Type
IO STRUCTURE INVERSION
CONTROL
DRIVE
STRENGTH
CONTROL
HYSTERESIS
CONTROL
PULLUP
RESISTOR
PULLDOWN
RESISTOR
WAKEUP
LOGIC
Standard drive Y Y Y
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Table 6-2. Digital IO Features by IO Type (continued)
IO STRUCTURE INVERSION
CONTROL
DRIVE
STRENGTH
CONTROL
HYSTERESIS
CONTROL
PULLUP
RESISTOR
PULLDOWN
RESISTOR
WAKEUP
LOGIC
Standard drive with wake(2) Y Y Y Y
High drive Y Y Y Y Y
High speed Y Y Y Y
5-V tolerant open drain Y Y Y Y
6.3 Signal Descriptions
Table 6-3. Signal Descriptions
FUNCTION SIGNAL NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
32
RHB
28
DGS28
20
DGS20
ADC
A0_0 31 2 2 I ADC0 analog input 0
A0_1 30 1 1 I ADC0 analog input 1
A0_2 29 28 – I ADC0 analog input 2
A0_3 28 27 20 I ADC0 analog input 3
A0_4 – – – I ADC0 analog input 4
A0_5 – – – I ADC0 analog input 5
A0_6 – – – I ADC0 analog input 6
A0_7 26 25 18 I ADC0 analog input 7
A0_12 18 17 – I ADC0 analog input 12
A1_0 19 18 – I ADC1 analog input 0
A1_1 20 19 – I ADC1 analog input 1
A1_2 21 20 14 I ADC1 analog input 2
A1_3 22 21 15 I ADC1 analog input 3
A1_4 – – – I ADC1 analog input 4
A1_5 – – – I ADC1 analog input 5
A1_6 – – – I ADC1 analog input 6
A1_7 25 24 – I ADC1 analog input 7
BSL BSL_invoke 22 21 15 I Input pin used to invoke bootloader
BSL (I2C) BSLSCL 2 5 – I/O Default I2C BSL clock
BSLSDA 1 4 – I/O Default I2C BSL data
BSL (UART) BSLRX 15 16 12 I Default UART BSL receive
BSLTX 14 15 11 O Default UART BSL transmit
CAN
CAN_TX 16
30 11 13 O CAN-FD transmit data
CAN_RX 17
31 2 2 I CAN-FD receive data
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
32
RHB
28
DGS28
20
DGS20
Clock
CLK_OUT
11
13
14
18
26
14
15
17
25
10
11
18
O Configurable clock output
HFCLK_IN 10 13 9 I Digital high-frequency clock input
HFXIN 9 12 8 I Input for high-frequency crystal oscillator HFXT
HFXOUT 10 13 9 O Output for high-frequency crystal oscillator HFXT
LFCLK_IN 8 11 – I Digital low-frequency clock input
LFXIN 7 10 – I Input for low-frequency crystal oscillator LFXT
LFXOUT 8 11 – O Output of low-frequency crystal oscillator LFXT
ROSC 6 9 7 I External resistor used for improving oscillator accuracy
Debug SWCLK 24 23 17 I Serial wire debug input clock
SWDIO 23 22 16 I/O Serial wire debug data input/output
FCC FCC_IN
1
9
16
20
4
12
19
8
13 I Frequency clock counter input
General-
Purpose
Amplifier
GPAMP_IN+ 30 1 1 I GPAMP non-inverting terminal input
GPAMP_IN- 22 21 15 I GPAMP inverting terminal input
GPAMP_OUT 26 25 18 O GPAMP output
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
32
RHB
28
DGS28
20
DGS20
GPIO
PA0 1 4 – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA1 2 5 – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA2 6 9 7 I/O General-purpose digital I/O
PA3 7 10 – I/O General-purpose digital I/O
PA4 8 11 – I/O General-purpose digital I/O
PA5 9 12 8 I/O General-purpose digital I/O
PA6 10 13 9 I/O General-purpose digital I/O
PA7 11 – – I/O General-purpose digital I/O
PA8 12 – – I/O General-purpose digital I/O
PA9 13 14 10 I/O General-purpose digital I/O
PA10 14 15 11 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA11 15 16 12 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA12 16 – 13 I/O General-purpose digital I/O
PA13 17 – – I/O General-purpose digital I/O
PA14 18 17 – I/O General-purpose digital I/O
PA15 19 18 – I/O General-purpose digital I/O
PA16 20 19 – I/O General-purpose digital I/O
PA17 21 20 14 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA18 22 21 15 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA19 23 22 16 I/O General-purpose digital I/O
PA20 24 23 17 I/O General-purpose digital I/O
PA21 25 24 – I/O General-purpose digital I/O
PA22 26 25 18 I/O General-purpose digital I/O
PA23 27 26 19 I/O General-purpose digital I/O
PA24 28 27 20 I/O General-purpose digital I/O
PA25 29 28 – I/O General-purpose digital I/O
PA26 30 1 1 I/O General-purpose digital I/O
PA27 31 2 2 I/O General-purpose digital I/O
PA28 – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
PA29 – – – I/O General-purpose digital I/O
PA30 – – – I/O General-purpose digital I/O
PA31 – – – I/O General-purpose digital I/O with wake up from SHUTDOWN
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
32
RHB
28
DGS28
20
DGS20
GPIO
PB0 – – – I/O General-purpose digital I/O
PB1 – – – I/O General-purpose digital I/O
PB2 – – – I/O General-purpose digital I/O
PB3 – – – I/O General-purpose digital I/O
PB4 – – – I/O General-purpose digital I/O
PB5 – – – I/O General-purpose digital I/O
PB6 – – – I/O General-purpose digital I/O
PB7 – – – I/O General-purpose digital I/O
PB8 – – – I/O General-purpose digital I/O
PB9 – – – I/O General-purpose digital I/O
PB10 – – – I/O General-purpose digital I/O
PB11 – – – I/O General-purpose digital I/O
PB12 – – – I/O General-purpose digital I/O
PB13 – – – I/O General-purpose digital I/O
PB14 – – – I/O General-purpose digital I/O
PB15 – – – I/O General-purpose digital I/O
PB16 – – – I/O General-purpose digital I/O
PB17 – – – I/O General-purpose digital I/O
PB18 – – – I/O General-purpose digital I/O
PB19 – – – I/O General-purpose digital I/O
PB20 – – – I/O General-purpose digital I/O
PB21 – – – I/O General-purpose digital I/O
PB22 – – – I/O General-purpose digital I/O
PB23 – – – I/O General-purpose digital I/O
PB24 – – – I/O General-purpose digital I/O
PB25 – – – I/O General-purpose digital I/O
PB26 – – – I/O General-purpose digital I/O
PB27 – – – I/O General-purpose digital I/O
I2C
I2C0_SCL 2
15
5
16 12 I/O I2C0 serial clock
I2C0_SDA 1
14
4
15 11 I/O I2C0 serial data
I2C1_SCL
8
15
19
21
11
16
18
20
12
14 I/O I2C1 serial clock
I2C1_SDA
7
14
20
22
10
15
19
21
11
15 I/O I2C1 serial data
Power
VSS 5 8 6 P Ground supply
VDD 4 7 5 P Power supply
VCORE 32 3 3 P Regulated core power supply output
QFN Pad Pad – – P QFN package exposed thermal pad. TI recommends
connection to VSS.
RTC RTC_OUT 13
31
2
14
2
10 O RTC clock output
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
32
RHB
28
DGS28
20
DGS20
SPI
SPI0_CS0 6
12 9 7 I/O SPI0 chip-select 0
SPI0_CS1 7 10 – I/O SPI0 chip-select 1
SPI0_CS2 28 27 20 I/O SPI0 chip-select 2
SPI0_CS3 27 26 19 I/O SPI0 chip-select 3
SPI0_SCK
10
15
16
13
16
9
12
13
I/O SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI
8
14
17
11
15 11 I/O SPI0 controller in/peripheral out
SPI0_PICO
9
13
18
12
14
17
8
10 I/O SPI0 controller out/peripheral in
SPI1_CS0 6
30
1
9
1
7I/O SPI1 chip-select 0
SPI1_CS1 31 2 2 I/O SPI1 chip-select 1
SPI1_CS2 19 18 – I/O SPI1 chip-select 2
SPI1_CS3 29 28 – I/O SPI1 chip-select 3
SPI1_SCK 21 20 14 I/O SPI1 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI1_POCI 20 19 – I/O SPI1 controller in/peripheral out
SPI1_PICO 22 21 15 I/O SPI1 controller out/peripheral in
System NRST 3 6 4 I Reset input active low
Timer
TIMG0_C0
9
16
27
12
26
8
13
19
I/O General purpose timer 0 CCR0 capture input/ compare output
TIMG0_C1
10
17
28
13
27
9
20 I/O General purpose timer 0 CCR1 capture input/ compare output
TIMG6_C0 9
25
12
24 8 I/O General purpose timer 6 CCR0 capture input/ compare output
TIMG6_C1 10
26
13
25
9
18 I/O General purpose timer 6 CCR1 capture input/ compare output
TIMG7_C0
7
21
27
30
1
10
20
26
1
14
19
I/O General purpose timer 7 CCR1 capture input/ compare output
TIMG7_C1
6
8
11
22
28
31
2
9
11
21
27
2
7
15
20
I/O General purpose timer 7 CCR1 capture input/ compare output
TIMG8_C0
2
7
9
11
25
27
30
1
5
10
12
24
26
1
8
19
I/O General purpose timer 8 CCR0 capture input/ compare output
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
32
RHB
28
DGS28
20
DGS20
Timer
(continued)
TIMG8_C1
1
6
8
10
26
31
2
4
9
11
13
25
2
7
9
18
I/O General purpose timer 8 CCR1 capture input/ compare output
TIMG8_IDX
2
11
19
5
18 – I General purpose timer 8 quadrature encoder index pulse input
TIMG12_C0 14
18
15
17 11 I/O 32-bit general purpose timer 0 CCR0 capture input/ compare output
TIMG12_C1 29 28 – I/O 32-bit general purpose timer 0 CCR1 capture input/ compare
output
TIMA0_C0
1
12
25
4
24 – I/O Advanced control timer 0 CCR0 capture input/compare output
TIMA0_C0N 13
26
14
25
10
18 I/O Advanced control timer 0 CCR0 capture input/compare output (inverting)
TIMA0_C1
2
7
11
13
26
5
10
14
25
10
18 I/O Advanced control timer 0 CCR1 capture input/ compare output
TIMA0_C1N
8
13
29
11
14
28
10 I/O Advanced control timer 0 CCR1 capture input/ compare
output (inverting)
Timer
(continued)
TIMA0_C2
7
11
14
19
10
15
18
11 I/O Advanced control timer 0 CCR2 capture input/ compare
output
TIMA0_C2N
10
15
20
13
16
19
9
12 I/O Advanced control timer 0 CCR2 capture input/ compare output (inverting)
TIMA0_C3
8
16
21
27
29
11
20
26
28
13
14
19
I/O Advanced control timer 0 CCR3 capture input/ compare
output
TIMA0_C3N
17
22
28
21
27
15
20 I/O Advanced control timer 0 CCR3 capture input/ compare output (inverting)
TIMA1_C0
14
19
21
15
18
20
11
14 I/O Advanced control timer 1 CCR0 capture input/ compare output
TIMA1_C0N 12
19 18 – I/O Advanced control timer 0 CCR3 capture input/ compare output (inverting)
TIMA1_C1
15
20
22
28
16
19
21
27
12
15
20
I/O Advanced control timer 1 CCR1 capture input/ compare
output
TIMA1_C1N 13
20
14
19 10 I/O Advanced control timer 1 CCR1 capture input/ compare output (inverting)
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
32
RHB
28
DGS28
20
DGS20
Timer
(continued)
TIMA_FAL0 10
30
1
13
1
9I Advanced control timer 0 fault handling input
TIMA_FAL1 1
9
4
12 8 I Advanced control timer 1 fault handling input
TIMA_FAL2 2
31
2
52 I Advanced control timer 2 fault handling input
UART
UART0_TX 1
14
4
15 11 O UART0 transmit data
UART0_RX 2
15
5
16 12 I UART0 receive data
UART0_CTS 13
18
14
17 10 I UART0 "clear to send" flow control input
UART0_RTS 12
19 18 – O UART0 "request to send" flow control output
UART1_TX 12
21 20 14 O UART1 transmit data
UART1_RX 13
22
14
21
10
15 I UART1 receive data
UART1_CTS 25 24 – I UART1 "clear to send" flow control input
UART1_RTS 26 25 18 O UART1 "request to send" flow control output
UART2_TX 25
27
24
26 19 O UART2 transmit data
UART2_RX 26
28
25
27
18
20 I UART2 receive data
UART2_CTS 7 10 – I UART2 "clear to send" flow control input
UART2_RTS 8 11 – O UART2 "request to send" flow control output
UART
UART3_TX 18
30
1
17 1 O UART3 transmit data
UART3_RX 17
29 28 – I UART3 receive data
UART3_CTS 16
27 26 13 19 I UART3 "clear to send" flow control input
UART3_RTS 17
28 27 20 O UART3 "request to send" flow control output
Voltage
Reference (3)
VREF+ 27 26 19 I/O Voltage reference (VREF) power supply - external reference
input / internal reference output
VREF- 25 24 – I/O Voltage reference (VREF) ground supply - external reference
input / internal reference output
(1) – = not available
(2) I = input, O = output, I/O = input or output, P = power
(3) When using VREF+/- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be
placed on VREF+ to VREF-/GND with a capacitance based on the external reference source
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6.4 Connections for Unused Pins
Table 6-4 lists the correct termination of unused pins.
Table 6-4. Connection of Unused Pins
PIN (1) POTENTIAL COMMENT
PAx and PBx Open
Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and
configure unused pins to output low or input with internal pullup/
pulldown resistor.
NRST VCC NRST is an active-low reset signal; it must be pulled high to VCC
or the device will not start, for more information refer to Section 9.1
(1) Any unused pin with a function that is shared with general-purpose I/O should follow the "PAx and PBx" unused pin connection
guidelines.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage At VDD pin –0.3 4.1 V
VIInput voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V
VIInput voltage Applied to any common tolerance pins –0.3 VDD + 0.3
(4.1 MAX) V
IVDD Current of VDD pin Current into VDD pin (source) 80 mA
IVDD Current of VDD pin Current into VDD pin (source) 100 mA
IVSS Current of VSS pin Current out of VSS pin (sink) 80 mA
IVSS Current of VSS pin Current out of VSS pin (sink) 100 mA
IIO
Current of SDIO pin Current sunk or sourced by SDIO pin 6 mA
Current of HS_IO pin Current sunk or sourced by HSIO pin 6 mA
Current of HDIO pin Current sunk or sourced by HDIO pin 20 mA
Current of ODIO pin Current sunk by ODIO pin 20 mA
IDSupported diode current Diode current at any device pin ±2 mA
TJJunction temperature Junction temperature -40 130 °C
Tstg Storage temperature Storage temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1) ±2000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage 1.62 3.6 V
VCORE Voltage on VCORE pin (2) 1.35 V
CVDD Capacitor connected between VDD and VSS (1) 10 uF
CVCORE Capacitor connected between VCORE and VSS (1) (2) 470 nF
TA
Ambient temperature, T version –40 105 °C
Ambient temperature, S version –40 125
TJMax junction temperature, T version 125 °C
TJMax junction temperature, S version 130 °C
fMCLK (PD1 bus clock)
MCLK, CPUCLK frequency with 2 flash wait states (3) 80
MHzMCLK, CPUCLK frequency with 1 flash wait state (3) 48
MCLK, CPUCLK frequency with 0 flash wait states (3) 24
MSPM0G3107, MSPM0G3106, MSPM0G3105
SLASF12A – FEBRUARY 2023 – REVISED JUNE 2023 www.ti.com
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