Texas Instruments Concerto F28M36 Series Product manual

Concerto F28M36x
Technical Reference Manual
Literature Number: SPRUHE8E
October 2012–Revised November 2019

2SPRUHE8E–October 2012–Revised November 2019
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Contents
Contents
Preface....................................................................................................................................... 79
1 System Control and Interrupts............................................................................................. 80
1.1 Signal Description.......................................................................................................... 81
1.2 System Control Functional Description.................................................................................. 82
1.2.1 Device Identification............................................................................................... 82
1.2.2 Device Configuration Registers ................................................................................. 83
1.3 Reset Control ............................................................................................................... 83
1.3.1 Device Level Reset Sources..................................................................................... 83
1.3.2 Handling of Resets at System Level............................................................................ 90
1.4 WIR Mode................................................................................................................... 93
1.4.1 Entering WIR Mode ............................................................................................... 94
1.4.2 Exiting WIR Mode................................................................................................. 95
1.5 Exceptions and Interrupts Control........................................................................................ 96
1.5.1 Master Subsystem Nested Vectored Interrupt Controller.................................................... 96
1.5.2 Master Subsystem Exceptions Handling....................................................................... 97
1.5.3 Master Subsystem Non-Maskable Interrupt (MNMI) Module................................................ 98
1.5.4 Control Subsystem PIE ......................................................................................... 101
1.5.5 Control Subsystem Exceptions Handling..................................................................... 117
1.5.6 Control Subsystem NMI (CNMI) Module...................................................................... 117
1.6 Safety Features ........................................................................................................... 120
1.6.1 Write Protection on Registers.................................................................................. 120
1.6.2 Missing Clock Detection Logic ................................................................................. 121
1.6.3 PLLSLIP Detection .............................................................................................. 124
1.6.4 Control Subsystem PIE Vector Address Validity Check.................................................... 124
1.6.5 NMIWDs .......................................................................................................... 125
1.6.6 Watchdog Timers................................................................................................ 125
1.6.7 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 126
1.6.8 ECC Enabled Flash Memory................................................................................... 126
1.7 Power Control ............................................................................................................. 126
1.8 Clock Control.............................................................................................................. 126
1.8.1 Clock Sources.................................................................................................... 127
1.8.2 PLLs ............................................................................................................... 128
1.8.3 Master Subsystem Clocking.................................................................................... 129
1.8.4 Control Subsystem Clocking ................................................................................... 131
1.8.5 Clocking Control Semaphore Functionality................................................................... 135
1.8.6 ACIB and Analog Peripherals Clocking....................................................................... 136
1.8.7 Configuring XCLKOUT.......................................................................................... 136
1.8.8 32-Bit CPU Timers 0/1/2........................................................................................ 137
1.9 Low Power Modes........................................................................................................ 141
1.9.1 Low-Power Modes............................................................................................... 141
1.10 Code Security Module (CSM)........................................................................................... 145
1.10.1 Functional Description ......................................................................................... 145
1.10.2 CSM Impact on Other On-Chip Resources ................................................................. 148
1.10.3 Incorporating Code Security in User Applications.......................................................... 148
1.10.4 Do's and Don'ts to Protect Security Logic................................................................... 156

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1.11 µCRC Module ............................................................................................................. 156
1.11.1 Functional Description ......................................................................................... 156
1.11.2 CRC Polynomials............................................................................................... 157
1.11.3 CRC Calculation Procedure................................................................................... 157
1.11.4 CRC Calculation For Data Stored In Secure Memory ..................................................... 157
1.12 Inter Processor Communications (IPC)................................................................................ 157
1.12.1 MSGRAMs....................................................................................................... 158
1.12.2 IPC Flags and Interrupts....................................................................................... 158
1.12.3 MTOCIPC Communication ................................................................................... 159
1.12.4 CTOMIPC Communication .................................................................................... 160
1.12.5 Examples for Software IPC Procedure ...................................................................... 161
1.12.6 IPC Message Registers........................................................................................ 161
1.12.7 Flash Pump Semaphore....................................................................................... 162
1.12.8 Clock Configuration Semaphore.............................................................................. 163
1.12.9 Free Running Counter ......................................................................................... 165
1.13 System Control Registers................................................................................................ 166
1.13.1 System Control, Configuration Register Map ............................................................... 166
1.13.2 Device Identification and Device Configuration............................................................. 174
1.13.3 Reset Control and Status Registers.......................................................................... 191
1.13.4 WIRMODE Registers........................................................................................... 201
1.13.5 Exception and Interrupts....................................................................................... 202
1.13.6 Safety Control Registers....................................................................................... 222
1.13.7 Clocking Control Registers .................................................................................... 226
1.13.8 Master Subsystem Code Security Module (CSM) Registers.............................................. 255
1.13.9 Control Subsystem Code Security Module (CSM) Registers............................................. 271
1.13.10 µCRC Register Description .................................................................................. 275
1.13.11 Master Subsystem IPC Registers........................................................................... 277
1.13.12 Control Subsystem IPC Registers .......................................................................... 288
1.13.13 Master and Control Subsystem IPC Registers............................................................ 300
2 M3 General-Purpose Timers............................................................................................... 305
2.1 GPTM Features........................................................................................................... 306
2.2 Block Diagram............................................................................................................. 306
2.3 Functional Description.................................................................................................... 307
2.3.1 GPTM Reset Conditions........................................................................................ 307
2.3.2 Timer Modes ..................................................................................................... 308
2.3.3 DMA Operation................................................................................................... 312
2.3.4 Accessing Concatenated Register Values ................................................................... 313
2.4 Initialization and Configuration.......................................................................................... 313
2.4.1 One-Shot/Periodic Timer Mode................................................................................ 313
2.4.2 Real-Time Clock (RTC) Mode.................................................................................. 314
2.4.3 Input Edge-Count Mode......................................................................................... 314
2.4.4 Input Edge Timing Mode........................................................................................ 314
2.4.5 16-Bit PWM Mode ............................................................................................... 315
2.5 Register Map .............................................................................................................. 315
2.6 Register Descriptions..................................................................................................... 316
2.6.1 GPTM Configuration (GPTMCFG) Register, offset 0x000 ................................................. 316
2.6.2 GPTM Timer A Mode (GPTMTAMR) Register, offset 0x004 .............................................. 316
2.6.3 GPTM Timer B Mode (GPTMTBMR) Register, offset 0x008 .............................................. 318
2.6.4 GPTM Control (GPTMCTL) Register, offset 0x00C......................................................... 319
2.6.5 GPTM Interrupt Mask (GPTMIMR) Register, offset 0x018................................................. 320
2.6.6 GPTM Raw Interrupt Status (GPTMRIS) Register, offset 0x01C ......................................... 321
2.6.7 GPTM Masked Interrupt Status (GPTMMIS) Register, offset 0x020...................................... 322
2.6.8 GPTM Interrupt Clear (GPTMICR) Register, offset 0x024 ................................................. 323

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2.6.9 GPTM Timer A Interval Load (GPTMTAILR) Register, offset 0x028 ..................................... 324
2.6.10 GPTM Timer B Interval Load (GPTMTBILR) Register, offset 0x02C.................................... 325
2.6.11 GPTM Timer A Match (GPTMTAMATCHR) Register, offset 0x030 ..................................... 325
2.6.12 GPTM Timer B Match (GPTMTBMATCHR) Register, offset 0x034 ..................................... 326
2.6.13 GPTM Timer A Prescale (GPTMTAPR) Register, offset 0x038.......................................... 326
2.6.14 GPTM Timer B Prescale (GPTMTBPR) Register, offset 0x03C.......................................... 327
2.6.15 GPTM Timer A Prescale Match (GPTMTAPMR) Register, offset 0x040................................ 327
2.6.16 GPTM Timer B Prescale Match (GPTMTBPMR) Register, offset 0x044................................ 327
2.6.17 GPTM Timer A (GPTMTAR) Register, offset 0x048 ....................................................... 328
2.6.18 GPTM Timer B (GPTMTBR) Register, offset 0x04C....................................................... 328
2.6.19 GPTM Timer A Value (GPTMTAV) Register, offset 0x050................................................ 329
2.6.20 GPTM Timer B Value (GPTMTBV) Register, offset 0x054................................................ 329
3 M3 Watchdog Timers ........................................................................................................ 331
3.1 Introduction ................................................................................................................ 332
3.1.1 Block Diagram.................................................................................................... 332
3.1.2 Functional Description........................................................................................... 333
3.1.3 Initialization and Configuration................................................................................. 333
3.2 Register Map .............................................................................................................. 333
3.3 Register Descriptions..................................................................................................... 334
3.3.1 Watchdog Load (WDTLOAD) Register, offset 0x000....................................................... 334
3.3.2 Watchdog Value (WDTVALUE) Register, offset 0x004..................................................... 335
3.3.3 Watchdog Control (WDTCTL) Register, offset 0x008....................................................... 336
3.3.4 Watchdog Interrupt Clear (WDTICR) Register, offset 0x00C.............................................. 336
3.3.5 Watchdog Raw Interrupt Status (WDTRIS) Register, offset 0x010 ....................................... 337
3.3.6 Watchdog Masked Interrupt Status (WDTMIS) Register, offset 0x014................................... 337
3.3.7 Watchdog Test (WDTTEST) Register, offset 0x418 ........................................................ 338
3.3.8 Watchdog Lock (WDTLOCK) Register, offset 0xC00....................................................... 338
3.3.9 Watchdog Peripheral Identification 4 (WDTPeriphID4) Register, offset 0xFD0 ......................... 339
3.3.10 Watchdog Peripheral Identification 5 (WDTPeriphID5) Register, offset 0xFD4 ........................ 339
3.3.11 Watchdog Peripheral Identification 6 (WDTPeriphID6) Register, offset 0xFD8 ........................ 339
3.3.12 Watchdog Peripheral Identification 7 (WDTPeriphID7) Register, offset 0xFDC........................ 340
3.3.13 Watchdog Peripheral Identification 0 (WDTPeriphID0) Register, offset 0xFE0 ........................ 340
3.3.14 Watchdog Peripheral Identification 1 (WDTPeriphID1) Register, offset 0xFE4 ........................ 340
3.3.15 Watchdog Peripheral Identification 2 (WDTPeriphID2) Register, offset 0xFE8 ........................ 341
3.3.16 Watchdog Peripheral Identification 3 (WDTPeriphID3) Register, offset 0xFEC........................ 341
3.3.17 Watchdog PrimeCell Identification 0 (WDTPCellID0) Register, offset 0xFF0 .......................... 341
3.3.18 Watchdog PrimeCell Identification 1 (WDTPCellID1) Register, offset 0xFF4 .......................... 342
3.3.19 Watchdog PrimeCell Identification 2 (WDTPCellID2) Register, offset 0xFF8 .......................... 342
3.3.20 Watchdog PrimeCell Identification 3 (WDTPCellID3) Register, offset 0xFFC.......................... 342
4 General-Purpose Input/Output (GPIO) ................................................................................. 343
4.1 General-Purpose Input/Output (GPIO)................................................................................. 344
4.1.1 Introduction ....................................................................................................... 344
4.1.2 Signal Description ............................................................................................... 344
4.1.3 Functional Description........................................................................................... 351
4.1.4 Initialization and Configuration................................................................................. 354
4.1.5 Register Map ..................................................................................................... 355
4.1.6 Register Descriptions............................................................................................ 357
4.2 C28 General-Purpose Input/Output (GPIO)........................................................................... 378
4.2.1 Introduction ....................................................................................................... 378
4.2.2 GPIO Module Overview......................................................................................... 378
4.2.3 Configuration Overview ......................................................................................... 384
4.2.4 Digital General Purpose I/O Control........................................................................... 387
4.2.5 Input Qualification................................................................................................ 389

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4.2.6 GPIO and Peripheral Multiplexing (MUX) .................................................................... 393
4.2.7 Register Bit Definitions.......................................................................................... 402
5 Internal Memory................................................................................................................ 462
5.1 RAM Control Module ..................................................................................................... 463
5.1.1 Functional Description........................................................................................... 463
5.2 RAM Control Module Registers......................................................................................... 472
5.2.1 M3 RAM Configuration Registers.............................................................................. 475
5.2.2 M3 RAM Error Registers........................................................................................ 494
5.2.3 C28x RAM Configuration Registers ........................................................................... 507
5.2.4 C28x RAM Error Registers ..................................................................................... 522
5.3 Flash Controller Memory Module....................................................................................... 535
5.3.1 Features........................................................................................................... 535
5.3.2 Flash Tools ....................................................................................................... 535
5.3.3 Default Flash Configuration .................................................................................... 536
5.3.4 Flash Bank, OTP and Pump ................................................................................... 536
5.3.5 Flash Module Controller (FMC)................................................................................ 537
5.3.6 Flash and OTP Automatic Power-Down Modes............................................................. 537
5.3.7 Flash and OTP Performance................................................................................... 539
5.3.8 Flash Read Interface ............................................................................................ 539
5.3.9 Erase/Program Flash............................................................................................ 544
5.3.10 Error Correction Code (ECC) Protection .................................................................... 545
5.3.11 Reserved Locations Within Flash and OTP................................................................. 549
5.3.12 Procedure to Change the Flash Control Registers......................................................... 549
5.4 Flash Registers ........................................................................................................... 550
5.4.1 Master Subsystem Flash Control Registers.................................................................. 554
5.4.2 Master Subsystem Flash ECC/Error Log Registers......................................................... 560
5.4.3 Control Subsystem Flash Control Registers ................................................................. 567
5.4.4 Control Subsystem Flash ECC/Error Log Registers ........................................................ 571
6 ROM Code and Peripheral Booting ..................................................................................... 578
6.1 Introduction ................................................................................................................ 579
6.2 Device Boot Sequence................................................................................................... 579
6.3 Device Boot Modes....................................................................................................... 580
6.4 Device Boot Flow Diagram .............................................................................................. 581
6.5 M-Boot ROM Description ................................................................................................ 582
6.5.1 M-Boot ROM Memory Map..................................................................................... 582
6.5.2 M-Boot ROM Vector Table ..................................................................................... 582
6.5.3 M-Boot ROM Version and Checksum Information .......................................................... 583
6.5.4 M-Boot ROM RAM Initialization................................................................................ 583
6.5.5 M-Boot ROM RAM Usage...................................................................................... 584
6.5.6 M-Boot ROM User OTP......................................................................................... 584
6.5.7 M-Boot ROM Entry Points...................................................................................... 585
6.5.8 M-Boot ROM Clock Initialization............................................................................... 586
6.5.9 M-Boot ROM GPIO Assignments for Each Boot Mode..................................................... 587
6.5.10 M-Boot ROM Functional Flow................................................................................. 589
6.5.11 M-Boot ROM Flow Diagram................................................................................... 591
6.5.12 M-Boot ROM Boot Status in RAM for Applications......................................................... 595
6.5.13 M-Boot ROM Reset Cause Handling ........................................................................ 596
6.5.14 M-Boot ROM Exceptions Handling........................................................................... 596
6.5.15 M-Boot ROM Boot Modes ..................................................................................... 597
6.6 C-Boot ROM Description ................................................................................................ 613
6.6.1 C-Boot ROM Memory Map ..................................................................................... 613
6.6.2 C-Boot ROM RAM Initialization................................................................................ 620
6.6.3 C-Boot ROM RAM Usage ...................................................................................... 620

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6.6.4 C-Boot ROM Boot Modes....................................................................................... 621
6.6.5 C-Boot ROM Entry Points ...................................................................................... 622
6.6.6 C-Boot ROM GPIO Assignment for Boot Modes............................................................ 623
6.6.7 C-Boot ROM Clock Initializations.............................................................................. 624
6.6.8 C-Boot ROM Functional Flow.................................................................................. 624
6.6.9 C-Boot ROM MTOC IPC Commands ......................................................................... 627
6.6.10 C-Boot ROM Health Status.................................................................................... 633
6.6.11 C-Boot ROM Boot Status...................................................................................... 634
6.6.12 C-Boot ROM CTOM IPC Messages.......................................................................... 635
6.6.13 C-Boot Reset Cause Handling................................................................................ 636
6.6.14 C-Boot ROM Handling of Exceptions and PIE Interrupts.................................................. 636
6.6.15 C-Boot ROM Bootloader Functionality ...................................................................... 638
6.7 Guidelines for Boot ROM Application Writers......................................................................... 657
6.7.1 Master Subsystem Application Procedure to Start C-Boot ROM Bootloaders........................... 657
6.8 Application Notes to Use Boot ROM ................................................................................... 659
6.8.1 How to Send Boot Data to M-Boot ROM ..................................................................... 659
6.8.2 C-Boot ROM: Building the Boot Table ........................................................................ 665
7 C28 Enhanced Pulse Width Modulator (ePWM) Module ......................................................... 667
7.1 Introduction ................................................................................................................ 668
7.1.1 Submodule Overview............................................................................................ 669
7.1.2 Register Mapping................................................................................................ 673
7.2 ePWM Submodules ...................................................................................................... 678
7.2.1 Overview.......................................................................................................... 678
7.2.2 Time-Base (TB) Submodule.................................................................................... 680
7.2.3 Counter-Compare (CC) Submodule........................................................................... 690
7.2.4 Action-Qualifier (AQ) Submodule.............................................................................. 697
7.2.5 Dead-Band Generator (DB) Submodule...................................................................... 713
7.2.6 PWM-Chopper (PC) Submodule............................................................................... 720
7.2.7 Trip-Zone (TZ) Submodule ..................................................................................... 724
7.2.8 Event-Trigger (ET) Submodule ................................................................................ 729
7.2.9 Digital Compare (DC) Submodule............................................................................. 736
7.3 Applications to Power Topologies ...................................................................................... 744
7.3.1 Overview of Multiple Modules ................................................................................. 744
7.3.2 Key Configuration Capabilities................................................................................. 744
7.3.3 Controlling Multiple Buck Converters With Independent Frequencies.................................... 745
7.3.4 Controlling Multiple Buck Converters With Same Frequencies............................................ 749
7.3.5 Controlling Multiple Half H-Bridge (HHB) Converters....................................................... 752
7.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM).......................................... 754
7.3.7 Practical Applications Using Phase Control Between PWM Modules .................................... 758
7.3.8 Controlling a 3-Phase Interleaved DC/DC Converter....................................................... 759
7.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter....................................... 763
7.3.10 Controlling a Peak Current Mode Controlled Buck Module ............................................... 765
7.3.11 Controlling H-Bridge LLC Resonant Converter............................................................. 767
7.4 Registers................................................................................................................... 770
7.4.1 Time-Base Submodule Registers.............................................................................. 770
7.4.2 Counter-Compare Submodule Registers..................................................................... 779
7.4.3 Action-Qualifier Submodule Registers ........................................................................ 786
7.4.4 Dead-Band Submodule Registers............................................................................. 791
7.4.5 PWM-Chopper Submodule Control Register................................................................. 795
7.4.6 Trip-Zone Submodule Control and Status Registers........................................................ 797
7.4.7 Digital Compare Submodule Registers ....................................................................... 804
7.4.8 GPTRIP Input Select Registers................................................................................ 815
7.4.9 Event-Trigger Submodule Registers .......................................................................... 817

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7.4.10 Proper Interrupt Initialization Procedure..................................................................... 826
8 C28 Enhanced Capture (eCAP) Module................................................................................ 827
8.1 Introduction ................................................................................................................ 828
8.2 Description................................................................................................................. 828
8.3 Capture and APWM Operating Mode.................................................................................. 829
8.4 Capture Mode Description............................................................................................... 830
8.4.1 Event Prescaler .................................................................................................. 831
8.4.2 Edge Polarity Select and Qualifier............................................................................. 832
8.4.3 Continuous/One-Shot Control.................................................................................. 832
8.4.4 32-Bit Counter and Phase Control............................................................................. 833
8.4.5 CAP1-CAP4 Registers.......................................................................................... 834
8.4.6 Interrupt Control.................................................................................................. 834
8.4.7 Shadow Load and Lockout Control............................................................................ 835
8.4.8 APWM Mode Operation......................................................................................... 836
8.5 Capture Module - Control and Status Registers...................................................................... 838
8.6 Register Mapping......................................................................................................... 846
8.7 Application of the ECAP Module ....................................................................................... 846
8.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger....................................... 847
8.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ........................ 849
8.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger..................................... 851
8.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger ...................... 853
8.8 Application of the APWM Mode......................................................................................... 855
8.8.1 Example 1 - Simple PWM Generation (Independent Channel/s).......................................... 855
9 C28 Enhanced QEP (eQEP) Module..................................................................................... 857
9.1 Introduction ................................................................................................................ 858
9.2 Description................................................................................................................. 860
9.2.1 EQEP Inputs...................................................................................................... 860
9.2.2 Functional Description........................................................................................... 861
9.2.3 eQEP Memory Map ............................................................................................. 861
9.3 Quadrature Decoder Unit (QDU) ....................................................................................... 863
9.3.1 Position Counter Input Modes.................................................................................. 863
9.3.2 eQEP Input Polarity Selection.................................................................................. 866
9.3.3 Position-Compare Sync Output................................................................................ 866
9.4 Position Counter and Control Unit (PCCU)............................................................................ 866
9.4.1 Position Counter Operating Modes............................................................................ 866
9.4.2 Position Counter Latch.......................................................................................... 868
9.4.3 Position Counter Initialization .................................................................................. 870
9.4.4 eQEP Position-compare Unit................................................................................... 871
9.5 eQEP Edge Capture Unit................................................................................................ 872
9.6 eQEP Watchdog .......................................................................................................... 876
9.7 Unit Timer Base........................................................................................................... 876
9.8 eQEP Interrupt Structure ................................................................................................ 877
9.9 eQEP Registers........................................................................................................... 877
10 Analog Subsystem............................................................................................................ 891
10.1 Overview................................................................................................................... 892
10.2 Analog Common Interface Bus (ACIB) ................................................................................ 892
10.3 Analog-to-Digital Converter (ADC) ..................................................................................... 896
10.3.1 Features.......................................................................................................... 896
10.3.2 Block Diagram................................................................................................... 897
10.3.3 SOC Principle of Operation ................................................................................... 897
10.3.4 ONESHOT Single Conversion Support...................................................................... 901
10.3.5 ADC Conversion Priority....................................................................................... 902
10.3.6 Simultaneous Sampling Mode ................................................................................ 905

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10.3.7 EOC and Interrupt Operation.................................................................................. 905
10.3.8 Power Up Sequence ........................................................................................... 906
10.3.9 ADC Calibration................................................................................................. 906
10.3.10 Internal/External Reference Voltage Selection............................................................ 908
10.3.11 ADC Registers................................................................................................. 909
10.3.12 Analog Subsystem Control Registers ...................................................................... 926
10.3.13 ADC Timings................................................................................................... 935
10.4 Comparator Block......................................................................................................... 938
10.4.1 Features......................................................................................................... 938
10.4.2 Comparator Block Diagram.................................................................................... 939
10.4.3 Comparator Function........................................................................................... 939
10.4.4 DAC Reference ................................................................................................. 939
10.4.5 Initialization ...................................................................................................... 940
10.4.6 Digital Domain Manipulation .................................................................................. 940
10.4.7 Comparator Registers.......................................................................................... 941
10.5 Analog Subsystem Software ............................................................................................ 943
10.5.1 C28 Analog Subsystem Functions ........................................................................... 943
10.5.2 C28 Analog Subsystem Software Example ................................................................. 945
10.5.3 M3 Analog Subsystem Functions............................................................................. 945
10.5.4 M3 Analog Subsystem Software Example .................................................................. 946
11 C28 Direct Memory Access (DMA) Module .......................................................................... 948
11.1 Introduction ................................................................................................................ 949
11.2 Architecture................................................................................................................ 949
11.2.1 Block Diagram................................................................................................... 949
11.2.2 Peripheral Interrupt Event Trigger Sources ................................................................. 950
11.2.3 DMA Bus......................................................................................................... 952
11.3 Pipeline Timing and Throughput........................................................................................ 953
11.3.1 DMA Read Access of ADC Registers........................................................................ 954
11.4 CPU Arbitration ........................................................................................................... 954
11.4.1 Arbitration when Accessing the Analog Subsystem........................................................ 955
11.5 Channel Priority........................................................................................................... 955
11.5.1 Round-Robin Mode............................................................................................. 955
11.5.2 Channel 1 High Priority Mode................................................................................. 956
11.6 Address Pointer and Transfer Control ................................................................................. 957
11.7 Overrun Detection Feature .............................................................................................. 961
11.8 Register Descriptions..................................................................................................... 963
11.8.1 DMA Control Register (DMACTRL) — EALLOW Protected .............................................. 964
11.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected......................................... 966
11.8.3 Revision Register (REVISION) ............................................................................... 966
11.8.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected ................................. 967
11.8.5 Priority Status Register (PRIORITYSTAT) .................................................................. 968
11.8.6 Mode Register (MODE) — EALLOW Protected............................................................ 969
11.8.7 Control Register (CONTROL) — EALLOW Protected..................................................... 971
11.8.8 Burst Size Register (BURST_SIZE) — EALLOW Protected.............................................. 973
11.8.9 BURST_COUNT Register ..................................................................................... 973
11.8.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected .................... 974
11.8.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected................ 975
11.8.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected ................................... 975
11.8.13 Transfer Count Register (TRANSFER_COUNT) ......................................................... 976
11.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected ........... 976
11.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected....... 977
11.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)........ 977
11.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) .............................. 978

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11.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected 978
11.8.19 Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected............ 979
11.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR)....................................................................... 979
11.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected .......................... 980
11.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) ..... 980
12 C28 Serial Peripheral Interface (SPI).................................................................................... 981
12.1 Enhanced SPI Module Overview ....................................................................................... 982
12.1.1 SPI Block Diagram ............................................................................................. 983
12.1.2 SPI Module Signal Summary.................................................................................. 985
12.1.3 Overview of SPI Module Registers........................................................................... 985
12.1.4 SPI Operation ................................................................................................... 986
12.1.5 SPI Interrupts.................................................................................................... 988
12.1.6 SPI FIFO Description........................................................................................... 993
12.1.7 SPI 3-Wire Mode Description ................................................................................. 995
12.1.8 SPI STEINV Bit in Digital Audio Transfers .................................................................. 997
12.2 C28 SPI-A to M3 SSI3 Internal Loopback............................................................................. 998
12.2.1 Loopback Initialization and Configuration ................................................................... 999
12.3 SPI Registers and Waveforms ........................................................................................ 1001
12.3.1 SPI Control Registers......................................................................................... 1001
12.3.2 SPI Example Waveforms..................................................................................... 1010
13 C28 Serial Communications Interface (SCI)........................................................................ 1016
13.1 Enhanced SCI Module Overview...................................................................................... 1017
13.1.1 Architecture .................................................................................................... 1019
13.2 C28 SCI-A to M3 UART4 Internal Loopback ........................................................................ 1029
13.2.1 Loopback Initialization and Configuration.................................................................. 1030
13.3 SCI Registers............................................................................................................ 1031
13.3.1 SCI Module Register Summary ............................................................................. 1031
13.3.2 SCI Communication Control Register (SCICCR) ......................................................... 1032
13.3.3 SCI Control Register 1 (SCICTL1).......................................................................... 1033
13.3.4 SCI Baud-Select Registers (SCIHBAUD, SCILBAUD)................................................... 1035
13.3.5 SCI Control Register 2 (SCICTL2).......................................................................... 1036
13.3.6 SCI Receiver Status Register (SCIRXST) ................................................................. 1036
13.3.7 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF) ............................................. 1038
13.3.8 SCI Transmit Data Buffer Register (SCITXBUF).......................................................... 1039
13.3.9 SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT) ................................................... 1039
13.3.10 Priority Control Register (SCIPRI)......................................................................... 1043
14 C28 Inter-Integrated Circuit Module................................................................................... 1044
14.1 Introduction to the I2C Module ........................................................................................ 1045
14.1.1 Features........................................................................................................ 1046
14.1.2 Features Not Supported...................................................................................... 1046
14.1.3 Functional Overview .......................................................................................... 1046
14.1.4 Clock Generation.............................................................................................. 1047
14.2 I2C Module Operational Details ....................................................................................... 1048
14.2.1 Input and Output Voltage Levels............................................................................ 1048
14.2.2 Data Validity ................................................................................................... 1048
14.2.3 Operating Modes.............................................................................................. 1049
14.2.4 I2C Module START and STOP Conditions ................................................................ 1050
14.2.5 Serial Data Formats........................................................................................... 1050
14.2.6 NACK Bit Generation......................................................................................... 1052
14.2.7 Clock Synchronization........................................................................................ 1053

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10 SPRUHE8E–October 2012–Revised November 2019
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Contents
14.2.8 Arbitration ...................................................................................................... 1053
14.3 Interrupt Requests Generated by the I2C Module.................................................................. 1054
14.3.1 Basic I2C Interrupt Requests................................................................................ 1054
14.3.2 I2C FIFO Interrupts ........................................................................................... 1055
14.4 Resetting/Disabling the I2C Module .................................................................................. 1055
14.5 I2C Module Registers................................................................................................... 1056
14.5.1 I2C Mode Register (I2CMDR) ............................................................................... 1057
14.5.2 I2C Extended Mode Register (I2CEMDR) ................................................................. 1060
14.5.3 I2C Interrupt Enable Register (I2CIER) .................................................................... 1062
14.5.4 I2C Status Register (I2CSTR)............................................................................... 1062
14.5.5 I2C Interrupt Source Register (I2CISRC) .................................................................. 1065
14.5.6 I2C Prescaler Register (I2CPSC)........................................................................... 1066
14.5.7 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 1066
14.5.8 I2C Slave Address Register (I2CSAR)..................................................................... 1068
14.5.9 I2C Own Address Register (I2COAR)...................................................................... 1068
14.5.10 I2C Data Count Register (I2CCNT) ....................................................................... 1069
14.5.11 I2C Data Receive Register (I2CDRR) .................................................................... 1069
14.5.12 I2C Data Transmit Register (I2CDXR).................................................................... 1069
14.5.13 I2C Transmit FIFO Register (I2CFFTX) .................................................................. 1070
14.5.14 I2C Receive FIFO Register (I2CFFRX)................................................................... 1071
15 C28 Multichannel Buffered Serial Port (McBSP).................................................................. 1073
15.1 Overview.................................................................................................................. 1074
15.1.1 Features of the McBSP....................................................................................... 1074
15.1.2 McBSP Pins/Signals.......................................................................................... 1075
15.1.3 McBSP Operation............................................................................................. 1076
15.1.4 Data Transfer Process of McBSP........................................................................... 1077
15.1.5 Companding (Compressing and Expanding) Data........................................................ 1077
15.2 Clocking and Framing Data............................................................................................ 1079
15.2.1 Clocking ........................................................................................................ 1079
15.2.2 Serial Words ................................................................................................... 1079
15.2.3 Frames and Frame Synchronization........................................................................ 1080
15.2.4 Generating Transmit and Receive Interrupts.............................................................. 1080
15.2.5 Ignoring Frame-Synchronization Pulses ................................................................... 1080
15.2.6 Frame Frequency ............................................................................................. 1081
15.2.7 Maximum Frame Frequency................................................................................. 1081
15.3 Frame Phases ........................................................................................................... 1081
15.3.1 Number of Phases, Words, and Bits Per Frame.......................................................... 1082
15.3.2 Single-Phase Frame Example............................................................................... 1082
15.3.3 Dual-Phase Frame Example................................................................................. 1082
15.3.4 Implementing the AC97 Standard With a Dual-Phase Frame........................................... 1083
15.3.5 McBSP Reception............................................................................................. 1083
15.3.6 McBSP Transmission......................................................................................... 1085
15.3.7 Interrupts and DMA Events Generated by a McBSP..................................................... 1086
15.4 McBSP Sample Rate Generator ...................................................................................... 1086
15.4.1 Block Diagram................................................................................................. 1087
15.4.2 Frame Synchronization Generation in the Sample Rate Generator.................................... 1090
15.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock................................. 1090
15.4.4 Reset and Initialization Procedure for the Sample Rate Generator .................................... 1092
15.5 McBSP Exception/Error Conditions................................................................................... 1093
15.5.1 Types of Errors ................................................................................................ 1093
15.5.2 Overrun in the Receiver...................................................................................... 1093
15.5.3 Unexpected Receive Frame-Synchronization Pulse ..................................................... 1095
15.5.4 Overwrite in the Transmitter ................................................................................. 1097