Texas Instruments Concerto F28M36 Series Product manual

Concerto F28M36x
Technical Reference Manual
Literature Number: SPRUHE8E
October 2012–Revised November 2019

2SPRUHE8E–October 2012–Revised November 2019
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Contents
Contents
Preface....................................................................................................................................... 79
1 System Control and Interrupts............................................................................................. 80
1.1 Signal Description.......................................................................................................... 81
1.2 System Control Functional Description.................................................................................. 82
1.2.1 Device Identification............................................................................................... 82
1.2.2 Device Configuration Registers ................................................................................. 83
1.3 Reset Control ............................................................................................................... 83
1.3.1 Device Level Reset Sources..................................................................................... 83
1.3.2 Handling of Resets at System Level............................................................................ 90
1.4 WIR Mode................................................................................................................... 93
1.4.1 Entering WIR Mode ............................................................................................... 94
1.4.2 Exiting WIR Mode................................................................................................. 95
1.5 Exceptions and Interrupts Control........................................................................................ 96
1.5.1 Master Subsystem Nested Vectored Interrupt Controller.................................................... 96
1.5.2 Master Subsystem Exceptions Handling....................................................................... 97
1.5.3 Master Subsystem Non-Maskable Interrupt (MNMI) Module................................................ 98
1.5.4 Control Subsystem PIE ......................................................................................... 101
1.5.5 Control Subsystem Exceptions Handling..................................................................... 117
1.5.6 Control Subsystem NMI (CNMI) Module...................................................................... 117
1.6 Safety Features ........................................................................................................... 120
1.6.1 Write Protection on Registers.................................................................................. 120
1.6.2 Missing Clock Detection Logic ................................................................................. 121
1.6.3 PLLSLIP Detection .............................................................................................. 124
1.6.4 Control Subsystem PIE Vector Address Validity Check.................................................... 124
1.6.5 NMIWDs .......................................................................................................... 125
1.6.6 Watchdog Timers................................................................................................ 125
1.6.7 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 126
1.6.8 ECC Enabled Flash Memory................................................................................... 126
1.7 Power Control ............................................................................................................. 126
1.8 Clock Control.............................................................................................................. 126
1.8.1 Clock Sources.................................................................................................... 127
1.8.2 PLLs ............................................................................................................... 128
1.8.3 Master Subsystem Clocking.................................................................................... 129
1.8.4 Control Subsystem Clocking ................................................................................... 131
1.8.5 Clocking Control Semaphore Functionality................................................................... 135
1.8.6 ACIB and Analog Peripherals Clocking....................................................................... 136
1.8.7 Configuring XCLKOUT.......................................................................................... 136
1.8.8 32-Bit CPU Timers 0/1/2........................................................................................ 137
1.9 Low Power Modes........................................................................................................ 141
1.9.1 Low-Power Modes............................................................................................... 141
1.10 Code Security Module (CSM)........................................................................................... 145
1.10.1 Functional Description ......................................................................................... 145
1.10.2 CSM Impact on Other On-Chip Resources ................................................................. 148
1.10.3 Incorporating Code Security in User Applications.......................................................... 148
1.10.4 Do's and Don'ts to Protect Security Logic................................................................... 156

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1.11 µCRC Module ............................................................................................................. 156
1.11.1 Functional Description ......................................................................................... 156
1.11.2 CRC Polynomials............................................................................................... 157
1.11.3 CRC Calculation Procedure................................................................................... 157
1.11.4 CRC Calculation For Data Stored In Secure Memory ..................................................... 157
1.12 Inter Processor Communications (IPC)................................................................................ 157
1.12.1 MSGRAMs....................................................................................................... 158
1.12.2 IPC Flags and Interrupts....................................................................................... 158
1.12.3 MTOCIPC Communication ................................................................................... 159
1.12.4 CTOMIPC Communication .................................................................................... 160
1.12.5 Examples for Software IPC Procedure ...................................................................... 161
1.12.6 IPC Message Registers........................................................................................ 161
1.12.7 Flash Pump Semaphore....................................................................................... 162
1.12.8 Clock Configuration Semaphore.............................................................................. 163
1.12.9 Free Running Counter ......................................................................................... 165
1.13 System Control Registers................................................................................................ 166
1.13.1 System Control, Configuration Register Map ............................................................... 166
1.13.2 Device Identification and Device Configuration............................................................. 174
1.13.3 Reset Control and Status Registers.......................................................................... 191
1.13.4 WIRMODE Registers........................................................................................... 201
1.13.5 Exception and Interrupts....................................................................................... 202
1.13.6 Safety Control Registers....................................................................................... 222
1.13.7 Clocking Control Registers .................................................................................... 226
1.13.8 Master Subsystem Code Security Module (CSM) Registers.............................................. 255
1.13.9 Control Subsystem Code Security Module (CSM) Registers............................................. 271
1.13.10 µCRC Register Description .................................................................................. 275
1.13.11 Master Subsystem IPC Registers........................................................................... 277
1.13.12 Control Subsystem IPC Registers .......................................................................... 288
1.13.13 Master and Control Subsystem IPC Registers............................................................ 300
2 M3 General-Purpose Timers............................................................................................... 305
2.1 GPTM Features........................................................................................................... 306
2.2 Block Diagram............................................................................................................. 306
2.3 Functional Description.................................................................................................... 307
2.3.1 GPTM Reset Conditions........................................................................................ 307
2.3.2 Timer Modes ..................................................................................................... 308
2.3.3 DMA Operation................................................................................................... 312
2.3.4 Accessing Concatenated Register Values ................................................................... 313
2.4 Initialization and Configuration.......................................................................................... 313
2.4.1 One-Shot/Periodic Timer Mode................................................................................ 313
2.4.2 Real-Time Clock (RTC) Mode.................................................................................. 314
2.4.3 Input Edge-Count Mode......................................................................................... 314
2.4.4 Input Edge Timing Mode........................................................................................ 314
2.4.5 16-Bit PWM Mode ............................................................................................... 315
2.5 Register Map .............................................................................................................. 315
2.6 Register Descriptions..................................................................................................... 316
2.6.1 GPTM Configuration (GPTMCFG) Register, offset 0x000 ................................................. 316
2.6.2 GPTM Timer A Mode (GPTMTAMR) Register, offset 0x004 .............................................. 316
2.6.3 GPTM Timer B Mode (GPTMTBMR) Register, offset 0x008 .............................................. 318
2.6.4 GPTM Control (GPTMCTL) Register, offset 0x00C......................................................... 319
2.6.5 GPTM Interrupt Mask (GPTMIMR) Register, offset 0x018................................................. 320
2.6.6 GPTM Raw Interrupt Status (GPTMRIS) Register, offset 0x01C ......................................... 321
2.6.7 GPTM Masked Interrupt Status (GPTMMIS) Register, offset 0x020...................................... 322
2.6.8 GPTM Interrupt Clear (GPTMICR) Register, offset 0x024 ................................................. 323

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2.6.9 GPTM Timer A Interval Load (GPTMTAILR) Register, offset 0x028 ..................................... 324
2.6.10 GPTM Timer B Interval Load (GPTMTBILR) Register, offset 0x02C.................................... 325
2.6.11 GPTM Timer A Match (GPTMTAMATCHR) Register, offset 0x030 ..................................... 325
2.6.12 GPTM Timer B Match (GPTMTBMATCHR) Register, offset 0x034 ..................................... 326
2.6.13 GPTM Timer A Prescale (GPTMTAPR) Register, offset 0x038.......................................... 326
2.6.14 GPTM Timer B Prescale (GPTMTBPR) Register, offset 0x03C.......................................... 327
2.6.15 GPTM Timer A Prescale Match (GPTMTAPMR) Register, offset 0x040................................ 327
2.6.16 GPTM Timer B Prescale Match (GPTMTBPMR) Register, offset 0x044................................ 327
2.6.17 GPTM Timer A (GPTMTAR) Register, offset 0x048 ....................................................... 328
2.6.18 GPTM Timer B (GPTMTBR) Register, offset 0x04C....................................................... 328
2.6.19 GPTM Timer A Value (GPTMTAV) Register, offset 0x050................................................ 329
2.6.20 GPTM Timer B Value (GPTMTBV) Register, offset 0x054................................................ 329
3 M3 Watchdog Timers ........................................................................................................ 331
3.1 Introduction ................................................................................................................ 332
3.1.1 Block Diagram.................................................................................................... 332
3.1.2 Functional Description........................................................................................... 333
3.1.3 Initialization and Configuration................................................................................. 333
3.2 Register Map .............................................................................................................. 333
3.3 Register Descriptions..................................................................................................... 334
3.3.1 Watchdog Load (WDTLOAD) Register, offset 0x000....................................................... 334
3.3.2 Watchdog Value (WDTVALUE) Register, offset 0x004..................................................... 335
3.3.3 Watchdog Control (WDTCTL) Register, offset 0x008....................................................... 336
3.3.4 Watchdog Interrupt Clear (WDTICR) Register, offset 0x00C.............................................. 336
3.3.5 Watchdog Raw Interrupt Status (WDTRIS) Register, offset 0x010 ....................................... 337
3.3.6 Watchdog Masked Interrupt Status (WDTMIS) Register, offset 0x014................................... 337
3.3.7 Watchdog Test (WDTTEST) Register, offset 0x418 ........................................................ 338
3.3.8 Watchdog Lock (WDTLOCK) Register, offset 0xC00....................................................... 338
3.3.9 Watchdog Peripheral Identification 4 (WDTPeriphID4) Register, offset 0xFD0 ......................... 339
3.3.10 Watchdog Peripheral Identification 5 (WDTPeriphID5) Register, offset 0xFD4 ........................ 339
3.3.11 Watchdog Peripheral Identification 6 (WDTPeriphID6) Register, offset 0xFD8 ........................ 339
3.3.12 Watchdog Peripheral Identification 7 (WDTPeriphID7) Register, offset 0xFDC........................ 340
3.3.13 Watchdog Peripheral Identification 0 (WDTPeriphID0) Register, offset 0xFE0 ........................ 340
3.3.14 Watchdog Peripheral Identification 1 (WDTPeriphID1) Register, offset 0xFE4 ........................ 340
3.3.15 Watchdog Peripheral Identification 2 (WDTPeriphID2) Register, offset 0xFE8 ........................ 341
3.3.16 Watchdog Peripheral Identification 3 (WDTPeriphID3) Register, offset 0xFEC........................ 341
3.3.17 Watchdog PrimeCell Identification 0 (WDTPCellID0) Register, offset 0xFF0 .......................... 341
3.3.18 Watchdog PrimeCell Identification 1 (WDTPCellID1) Register, offset 0xFF4 .......................... 342
3.3.19 Watchdog PrimeCell Identification 2 (WDTPCellID2) Register, offset 0xFF8 .......................... 342
3.3.20 Watchdog PrimeCell Identification 3 (WDTPCellID3) Register, offset 0xFFC.......................... 342
4 General-Purpose Input/Output (GPIO) ................................................................................. 343
4.1 General-Purpose Input/Output (GPIO)................................................................................. 344
4.1.1 Introduction ....................................................................................................... 344
4.1.2 Signal Description ............................................................................................... 344
4.1.3 Functional Description........................................................................................... 351
4.1.4 Initialization and Configuration................................................................................. 354
4.1.5 Register Map ..................................................................................................... 355
4.1.6 Register Descriptions............................................................................................ 357
4.2 C28 General-Purpose Input/Output (GPIO)........................................................................... 378
4.2.1 Introduction ....................................................................................................... 378
4.2.2 GPIO Module Overview......................................................................................... 378
4.2.3 Configuration Overview ......................................................................................... 384
4.2.4 Digital General Purpose I/O Control........................................................................... 387
4.2.5 Input Qualification................................................................................................ 389

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4.2.6 GPIO and Peripheral Multiplexing (MUX) .................................................................... 393
4.2.7 Register Bit Definitions.......................................................................................... 402
5 Internal Memory................................................................................................................ 462
5.1 RAM Control Module ..................................................................................................... 463
5.1.1 Functional Description........................................................................................... 463
5.2 RAM Control Module Registers......................................................................................... 472
5.2.1 M3 RAM Configuration Registers.............................................................................. 475
5.2.2 M3 RAM Error Registers........................................................................................ 494
5.2.3 C28x RAM Configuration Registers ........................................................................... 507
5.2.4 C28x RAM Error Registers ..................................................................................... 522
5.3 Flash Controller Memory Module....................................................................................... 535
5.3.1 Features........................................................................................................... 535
5.3.2 Flash Tools ....................................................................................................... 535
5.3.3 Default Flash Configuration .................................................................................... 536
5.3.4 Flash Bank, OTP and Pump ................................................................................... 536
5.3.5 Flash Module Controller (FMC)................................................................................ 537
5.3.6 Flash and OTP Automatic Power-Down Modes............................................................. 537
5.3.7 Flash and OTP Performance................................................................................... 539
5.3.8 Flash Read Interface ............................................................................................ 539
5.3.9 Erase/Program Flash............................................................................................ 544
5.3.10 Error Correction Code (ECC) Protection .................................................................... 545
5.3.11 Reserved Locations Within Flash and OTP................................................................. 549
5.3.12 Procedure to Change the Flash Control Registers......................................................... 549
5.4 Flash Registers ........................................................................................................... 550
5.4.1 Master Subsystem Flash Control Registers.................................................................. 554
5.4.2 Master Subsystem Flash ECC/Error Log Registers......................................................... 560
5.4.3 Control Subsystem Flash Control Registers ................................................................. 567
5.4.4 Control Subsystem Flash ECC/Error Log Registers ........................................................ 571
6 ROM Code and Peripheral Booting ..................................................................................... 578
6.1 Introduction ................................................................................................................ 579
6.2 Device Boot Sequence................................................................................................... 579
6.3 Device Boot Modes....................................................................................................... 580
6.4 Device Boot Flow Diagram .............................................................................................. 581
6.5 M-Boot ROM Description ................................................................................................ 582
6.5.1 M-Boot ROM Memory Map..................................................................................... 582
6.5.2 M-Boot ROM Vector Table ..................................................................................... 582
6.5.3 M-Boot ROM Version and Checksum Information .......................................................... 583
6.5.4 M-Boot ROM RAM Initialization................................................................................ 583
6.5.5 M-Boot ROM RAM Usage...................................................................................... 584
6.5.6 M-Boot ROM User OTP......................................................................................... 584
6.5.7 M-Boot ROM Entry Points...................................................................................... 585
6.5.8 M-Boot ROM Clock Initialization............................................................................... 586
6.5.9 M-Boot ROM GPIO Assignments for Each Boot Mode..................................................... 587
6.5.10 M-Boot ROM Functional Flow................................................................................. 589
6.5.11 M-Boot ROM Flow Diagram................................................................................... 591
6.5.12 M-Boot ROM Boot Status in RAM for Applications......................................................... 595
6.5.13 M-Boot ROM Reset Cause Handling ........................................................................ 596
6.5.14 M-Boot ROM Exceptions Handling........................................................................... 596
6.5.15 M-Boot ROM Boot Modes ..................................................................................... 597
6.6 C-Boot ROM Description ................................................................................................ 613
6.6.1 C-Boot ROM Memory Map ..................................................................................... 613
6.6.2 C-Boot ROM RAM Initialization................................................................................ 620
6.6.3 C-Boot ROM RAM Usage ...................................................................................... 620

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6.6.4 C-Boot ROM Boot Modes....................................................................................... 621
6.6.5 C-Boot ROM Entry Points ...................................................................................... 622
6.6.6 C-Boot ROM GPIO Assignment for Boot Modes............................................................ 623
6.6.7 C-Boot ROM Clock Initializations.............................................................................. 624
6.6.8 C-Boot ROM Functional Flow.................................................................................. 624
6.6.9 C-Boot ROM MTOC IPC Commands ......................................................................... 627
6.6.10 C-Boot ROM Health Status.................................................................................... 633
6.6.11 C-Boot ROM Boot Status...................................................................................... 634
6.6.12 C-Boot ROM CTOM IPC Messages.......................................................................... 635
6.6.13 C-Boot Reset Cause Handling................................................................................ 636
6.6.14 C-Boot ROM Handling of Exceptions and PIE Interrupts.................................................. 636
6.6.15 C-Boot ROM Bootloader Functionality ...................................................................... 638
6.7 Guidelines for Boot ROM Application Writers......................................................................... 657
6.7.1 Master Subsystem Application Procedure to Start C-Boot ROM Bootloaders........................... 657
6.8 Application Notes to Use Boot ROM ................................................................................... 659
6.8.1 How to Send Boot Data to M-Boot ROM ..................................................................... 659
6.8.2 C-Boot ROM: Building the Boot Table ........................................................................ 665
7 C28 Enhanced Pulse Width Modulator (ePWM) Module ......................................................... 667
7.1 Introduction ................................................................................................................ 668
7.1.1 Submodule Overview............................................................................................ 669
7.1.2 Register Mapping................................................................................................ 673
7.2 ePWM Submodules ...................................................................................................... 678
7.2.1 Overview.......................................................................................................... 678
7.2.2 Time-Base (TB) Submodule.................................................................................... 680
7.2.3 Counter-Compare (CC) Submodule........................................................................... 690
7.2.4 Action-Qualifier (AQ) Submodule.............................................................................. 697
7.2.5 Dead-Band Generator (DB) Submodule...................................................................... 713
7.2.6 PWM-Chopper (PC) Submodule............................................................................... 720
7.2.7 Trip-Zone (TZ) Submodule ..................................................................................... 724
7.2.8 Event-Trigger (ET) Submodule ................................................................................ 729
7.2.9 Digital Compare (DC) Submodule............................................................................. 736
7.3 Applications to Power Topologies ...................................................................................... 744
7.3.1 Overview of Multiple Modules ................................................................................. 744
7.3.2 Key Configuration Capabilities................................................................................. 744
7.3.3 Controlling Multiple Buck Converters With Independent Frequencies.................................... 745
7.3.4 Controlling Multiple Buck Converters With Same Frequencies............................................ 749
7.3.5 Controlling Multiple Half H-Bridge (HHB) Converters....................................................... 752
7.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM).......................................... 754
7.3.7 Practical Applications Using Phase Control Between PWM Modules .................................... 758
7.3.8 Controlling a 3-Phase Interleaved DC/DC Converter....................................................... 759
7.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter....................................... 763
7.3.10 Controlling a Peak Current Mode Controlled Buck Module ............................................... 765
7.3.11 Controlling H-Bridge LLC Resonant Converter............................................................. 767
7.4 Registers................................................................................................................... 770
7.4.1 Time-Base Submodule Registers.............................................................................. 770
7.4.2 Counter-Compare Submodule Registers..................................................................... 779
7.4.3 Action-Qualifier Submodule Registers ........................................................................ 786
7.4.4 Dead-Band Submodule Registers............................................................................. 791
7.4.5 PWM-Chopper Submodule Control Register................................................................. 795
7.4.6 Trip-Zone Submodule Control and Status Registers........................................................ 797
7.4.7 Digital Compare Submodule Registers ....................................................................... 804
7.4.8 GPTRIP Input Select Registers................................................................................ 815
7.4.9 Event-Trigger Submodule Registers .......................................................................... 817

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7.4.10 Proper Interrupt Initialization Procedure..................................................................... 826
8 C28 Enhanced Capture (eCAP) Module................................................................................ 827
8.1 Introduction ................................................................................................................ 828
8.2 Description................................................................................................................. 828
8.3 Capture and APWM Operating Mode.................................................................................. 829
8.4 Capture Mode Description............................................................................................... 830
8.4.1 Event Prescaler .................................................................................................. 831
8.4.2 Edge Polarity Select and Qualifier............................................................................. 832
8.4.3 Continuous/One-Shot Control.................................................................................. 832
8.4.4 32-Bit Counter and Phase Control............................................................................. 833
8.4.5 CAP1-CAP4 Registers.......................................................................................... 834
8.4.6 Interrupt Control.................................................................................................. 834
8.4.7 Shadow Load and Lockout Control............................................................................ 835
8.4.8 APWM Mode Operation......................................................................................... 836
8.5 Capture Module - Control and Status Registers...................................................................... 838
8.6 Register Mapping......................................................................................................... 846
8.7 Application of the ECAP Module ....................................................................................... 846
8.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger....................................... 847
8.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ........................ 849
8.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger..................................... 851
8.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger ...................... 853
8.8 Application of the APWM Mode......................................................................................... 855
8.8.1 Example 1 - Simple PWM Generation (Independent Channel/s).......................................... 855
9 C28 Enhanced QEP (eQEP) Module..................................................................................... 857
9.1 Introduction ................................................................................................................ 858
9.2 Description................................................................................................................. 860
9.2.1 EQEP Inputs...................................................................................................... 860
9.2.2 Functional Description........................................................................................... 861
9.2.3 eQEP Memory Map ............................................................................................. 861
9.3 Quadrature Decoder Unit (QDU) ....................................................................................... 863
9.3.1 Position Counter Input Modes.................................................................................. 863
9.3.2 eQEP Input Polarity Selection.................................................................................. 866
9.3.3 Position-Compare Sync Output................................................................................ 866
9.4 Position Counter and Control Unit (PCCU)............................................................................ 866
9.4.1 Position Counter Operating Modes............................................................................ 866
9.4.2 Position Counter Latch.......................................................................................... 868
9.4.3 Position Counter Initialization .................................................................................. 870
9.4.4 eQEP Position-compare Unit................................................................................... 871
9.5 eQEP Edge Capture Unit................................................................................................ 872
9.6 eQEP Watchdog .......................................................................................................... 876
9.7 Unit Timer Base........................................................................................................... 876
9.8 eQEP Interrupt Structure ................................................................................................ 877
9.9 eQEP Registers........................................................................................................... 877
10 Analog Subsystem............................................................................................................ 891
10.1 Overview................................................................................................................... 892
10.2 Analog Common Interface Bus (ACIB) ................................................................................ 892
10.3 Analog-to-Digital Converter (ADC) ..................................................................................... 896
10.3.1 Features.......................................................................................................... 896
10.3.2 Block Diagram................................................................................................... 897
10.3.3 SOC Principle of Operation ................................................................................... 897
10.3.4 ONESHOT Single Conversion Support...................................................................... 901
10.3.5 ADC Conversion Priority....................................................................................... 902
10.3.6 Simultaneous Sampling Mode ................................................................................ 905

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10.3.7 EOC and Interrupt Operation.................................................................................. 905
10.3.8 Power Up Sequence ........................................................................................... 906
10.3.9 ADC Calibration................................................................................................. 906
10.3.10 Internal/External Reference Voltage Selection............................................................ 908
10.3.11 ADC Registers................................................................................................. 909
10.3.12 Analog Subsystem Control Registers ...................................................................... 926
10.3.13 ADC Timings................................................................................................... 935
10.4 Comparator Block......................................................................................................... 938
10.4.1 Features......................................................................................................... 938
10.4.2 Comparator Block Diagram.................................................................................... 939
10.4.3 Comparator Function........................................................................................... 939
10.4.4 DAC Reference ................................................................................................. 939
10.4.5 Initialization ...................................................................................................... 940
10.4.6 Digital Domain Manipulation .................................................................................. 940
10.4.7 Comparator Registers.......................................................................................... 941
10.5 Analog Subsystem Software ............................................................................................ 943
10.5.1 C28 Analog Subsystem Functions ........................................................................... 943
10.5.2 C28 Analog Subsystem Software Example ................................................................. 945
10.5.3 M3 Analog Subsystem Functions............................................................................. 945
10.5.4 M3 Analog Subsystem Software Example .................................................................. 946
11 C28 Direct Memory Access (DMA) Module .......................................................................... 948
11.1 Introduction ................................................................................................................ 949
11.2 Architecture................................................................................................................ 949
11.2.1 Block Diagram................................................................................................... 949
11.2.2 Peripheral Interrupt Event Trigger Sources ................................................................. 950
11.2.3 DMA Bus......................................................................................................... 952
11.3 Pipeline Timing and Throughput........................................................................................ 953
11.3.1 DMA Read Access of ADC Registers........................................................................ 954
11.4 CPU Arbitration ........................................................................................................... 954
11.4.1 Arbitration when Accessing the Analog Subsystem........................................................ 955
11.5 Channel Priority........................................................................................................... 955
11.5.1 Round-Robin Mode............................................................................................. 955
11.5.2 Channel 1 High Priority Mode................................................................................. 956
11.6 Address Pointer and Transfer Control ................................................................................. 957
11.7 Overrun Detection Feature .............................................................................................. 961
11.8 Register Descriptions..................................................................................................... 963
11.8.1 DMA Control Register (DMACTRL) — EALLOW Protected .............................................. 964
11.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected......................................... 966
11.8.3 Revision Register (REVISION) ............................................................................... 966
11.8.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected ................................. 967
11.8.5 Priority Status Register (PRIORITYSTAT) .................................................................. 968
11.8.6 Mode Register (MODE) — EALLOW Protected............................................................ 969
11.8.7 Control Register (CONTROL) — EALLOW Protected..................................................... 971
11.8.8 Burst Size Register (BURST_SIZE) — EALLOW Protected.............................................. 973
11.8.9 BURST_COUNT Register ..................................................................................... 973
11.8.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected .................... 974
11.8.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected................ 975
11.8.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected ................................... 975
11.8.13 Transfer Count Register (TRANSFER_COUNT) ......................................................... 976
11.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected ........... 976
11.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected....... 977
11.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)........ 977
11.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) .............................. 978

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11.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected 978
11.8.19 Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected............ 979
11.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR)....................................................................... 979
11.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected .......................... 980
11.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) ..... 980
12 C28 Serial Peripheral Interface (SPI).................................................................................... 981
12.1 Enhanced SPI Module Overview ....................................................................................... 982
12.1.1 SPI Block Diagram ............................................................................................. 983
12.1.2 SPI Module Signal Summary.................................................................................. 985
12.1.3 Overview of SPI Module Registers........................................................................... 985
12.1.4 SPI Operation ................................................................................................... 986
12.1.5 SPI Interrupts.................................................................................................... 988
12.1.6 SPI FIFO Description........................................................................................... 993
12.1.7 SPI 3-Wire Mode Description ................................................................................. 995
12.1.8 SPI STEINV Bit in Digital Audio Transfers .................................................................. 997
12.2 C28 SPI-A to M3 SSI3 Internal Loopback............................................................................. 998
12.2.1 Loopback Initialization and Configuration ................................................................... 999
12.3 SPI Registers and Waveforms ........................................................................................ 1001
12.3.1 SPI Control Registers......................................................................................... 1001
12.3.2 SPI Example Waveforms..................................................................................... 1010
13 C28 Serial Communications Interface (SCI)........................................................................ 1016
13.1 Enhanced SCI Module Overview...................................................................................... 1017
13.1.1 Architecture .................................................................................................... 1019
13.2 C28 SCI-A to M3 UART4 Internal Loopback ........................................................................ 1029
13.2.1 Loopback Initialization and Configuration.................................................................. 1030
13.3 SCI Registers............................................................................................................ 1031
13.3.1 SCI Module Register Summary ............................................................................. 1031
13.3.2 SCI Communication Control Register (SCICCR) ......................................................... 1032
13.3.3 SCI Control Register 1 (SCICTL1).......................................................................... 1033
13.3.4 SCI Baud-Select Registers (SCIHBAUD, SCILBAUD)................................................... 1035
13.3.5 SCI Control Register 2 (SCICTL2).......................................................................... 1036
13.3.6 SCI Receiver Status Register (SCIRXST) ................................................................. 1036
13.3.7 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF) ............................................. 1038
13.3.8 SCI Transmit Data Buffer Register (SCITXBUF).......................................................... 1039
13.3.9 SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT) ................................................... 1039
13.3.10 Priority Control Register (SCIPRI)......................................................................... 1043
14 C28 Inter-Integrated Circuit Module................................................................................... 1044
14.1 Introduction to the I2C Module ........................................................................................ 1045
14.1.1 Features........................................................................................................ 1046
14.1.2 Features Not Supported...................................................................................... 1046
14.1.3 Functional Overview .......................................................................................... 1046
14.1.4 Clock Generation.............................................................................................. 1047
14.2 I2C Module Operational Details ....................................................................................... 1048
14.2.1 Input and Output Voltage Levels............................................................................ 1048
14.2.2 Data Validity ................................................................................................... 1048
14.2.3 Operating Modes.............................................................................................. 1049
14.2.4 I2C Module START and STOP Conditions ................................................................ 1050
14.2.5 Serial Data Formats........................................................................................... 1050
14.2.6 NACK Bit Generation......................................................................................... 1052
14.2.7 Clock Synchronization........................................................................................ 1053

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14.2.8 Arbitration ...................................................................................................... 1053
14.3 Interrupt Requests Generated by the I2C Module.................................................................. 1054
14.3.1 Basic I2C Interrupt Requests................................................................................ 1054
14.3.2 I2C FIFO Interrupts ........................................................................................... 1055
14.4 Resetting/Disabling the I2C Module .................................................................................. 1055
14.5 I2C Module Registers................................................................................................... 1056
14.5.1 I2C Mode Register (I2CMDR) ............................................................................... 1057
14.5.2 I2C Extended Mode Register (I2CEMDR) ................................................................. 1060
14.5.3 I2C Interrupt Enable Register (I2CIER) .................................................................... 1062
14.5.4 I2C Status Register (I2CSTR)............................................................................... 1062
14.5.5 I2C Interrupt Source Register (I2CISRC) .................................................................. 1065
14.5.6 I2C Prescaler Register (I2CPSC)........................................................................... 1066
14.5.7 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 1066
14.5.8 I2C Slave Address Register (I2CSAR)..................................................................... 1068
14.5.9 I2C Own Address Register (I2COAR)...................................................................... 1068
14.5.10 I2C Data Count Register (I2CCNT) ....................................................................... 1069
14.5.11 I2C Data Receive Register (I2CDRR) .................................................................... 1069
14.5.12 I2C Data Transmit Register (I2CDXR).................................................................... 1069
14.5.13 I2C Transmit FIFO Register (I2CFFTX) .................................................................. 1070
14.5.14 I2C Receive FIFO Register (I2CFFRX)................................................................... 1071
15 C28 Multichannel Buffered Serial Port (McBSP).................................................................. 1073
15.1 Overview.................................................................................................................. 1074
15.1.1 Features of the McBSP....................................................................................... 1074
15.1.2 McBSP Pins/Signals.......................................................................................... 1075
15.1.3 McBSP Operation............................................................................................. 1076
15.1.4 Data Transfer Process of McBSP........................................................................... 1077
15.1.5 Companding (Compressing and Expanding) Data........................................................ 1077
15.2 Clocking and Framing Data............................................................................................ 1079
15.2.1 Clocking ........................................................................................................ 1079
15.2.2 Serial Words ................................................................................................... 1079
15.2.3 Frames and Frame Synchronization........................................................................ 1080
15.2.4 Generating Transmit and Receive Interrupts.............................................................. 1080
15.2.5 Ignoring Frame-Synchronization Pulses ................................................................... 1080
15.2.6 Frame Frequency ............................................................................................. 1081
15.2.7 Maximum Frame Frequency................................................................................. 1081
15.3 Frame Phases ........................................................................................................... 1081
15.3.1 Number of Phases, Words, and Bits Per Frame.......................................................... 1082
15.3.2 Single-Phase Frame Example............................................................................... 1082
15.3.3 Dual-Phase Frame Example................................................................................. 1082
15.3.4 Implementing the AC97 Standard With a Dual-Phase Frame........................................... 1083
15.3.5 McBSP Reception............................................................................................. 1083
15.3.6 McBSP Transmission......................................................................................... 1085
15.3.7 Interrupts and DMA Events Generated by a McBSP..................................................... 1086
15.4 McBSP Sample Rate Generator ...................................................................................... 1086
15.4.1 Block Diagram................................................................................................. 1087
15.4.2 Frame Synchronization Generation in the Sample Rate Generator.................................... 1090
15.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock................................. 1090
15.4.4 Reset and Initialization Procedure for the Sample Rate Generator .................................... 1092
15.5 McBSP Exception/Error Conditions................................................................................... 1093
15.5.1 Types of Errors ................................................................................................ 1093
15.5.2 Overrun in the Receiver...................................................................................... 1093
15.5.3 Unexpected Receive Frame-Synchronization Pulse ..................................................... 1095
15.5.4 Overwrite in the Transmitter ................................................................................. 1097

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15.5.5 Unexpected Transmit Frame-Synchronization Pulse..................................................... 1099
15.6 Multichannel Selection Modes......................................................................................... 1101
15.6.1 Channels, Blocks, and Partitions............................................................................ 1101
15.6.2 Multichannel Selection........................................................................................ 1102
15.6.3 Configuring a Frame for Multichannel Selection .......................................................... 1102
15.6.4 Using Two Partitions.......................................................................................... 1102
15.6.5 Using Eight Partitions......................................................................................... 1104
15.6.6 Receive Multichannel Selection Mode...................................................................... 1105
15.6.7 Transmit Multichannel Selection Modes ................................................................... 1105
15.7 SPI Operation Using the Clock Stop Mode.......................................................................... 1108
15.7.1 SPI Protocol.................................................................................................... 1108
15.7.2 Clock Stop Mode.............................................................................................. 1109
15.7.3 Bits Used to Enable and Configure the Clock Stop Mode............................................... 1109
15.7.4 Clock Stop Mode Timing Diagrams......................................................................... 1110
15.7.5 Procedure for Configuring a McBSP for SPI Operation.................................................. 1112
15.7.6 McBSP as the SPI Master ................................................................................... 1112
15.7.7 McBSP as an SPI Slave...................................................................................... 1114
15.8 Receiver Configuration ................................................................................................. 1115
15.8.1 Programming the McBSP Registers for the Desired Receiver Operation ............................. 1115
15.8.2 Resetting and Enabling the Receiver....................................................................... 1116
15.8.3 Set the Receiver Pins to Operate as McBSP Pins ....................................................... 1116
15.8.4 Enable/Disable the Digital Loopback Mode................................................................ 1117
15.8.5 Enable/Disable the Clock Stop Mode....................................................................... 1117
15.8.6 Enable/Disable the Receive Multichannel Selection Mode.............................................. 1118
15.8.7 Choose One or Two Phases for the Receive Frame..................................................... 1118
15.8.8 Set the Receive Word Length(s)............................................................................ 1119
15.8.9 Set the Receive Frame Length.............................................................................. 1119
15.8.10 Enable/Disable the Receive Frame-Synchronization Ignore Function................................ 1120
15.8.11 Set the Receive Companding Mode ...................................................................... 1121
15.8.12 Set the Receive Data Delay................................................................................ 1122
15.8.13 Set the Receive Sign-Extension and Justification Mode ............................................... 1124
15.8.14 Set the Receive Interrupt Mode............................................................................ 1125
15.8.15 Set the Receive Frame-Synchronization Mode.......................................................... 1125
15.8.16 Set the Receive Frame-Synchronization Polarity........................................................ 1127
15.8.17 Set the Receive Clock Mode............................................................................... 1129
15.8.18 Set the Receive Clock Polarity............................................................................. 1130
15.8.19 Set the SRG Clock Divide-Down Value................................................................... 1132
15.8.20 Set the SRG Clock Synchronization Mode............................................................... 1132
15.8.21 Set the SRG Clock Mode (Choose an Input Clock)..................................................... 1132
15.8.22 Set the SRG Input Clock Polarity.......................................................................... 1134
15.9 Transmitter Configuration .............................................................................................. 1134
15.9.1 Programming the McBSP Registers for the Desired Transmitter Operation .......................... 1134
15.9.2 Resetting and Enabling the Transmitter.................................................................... 1135
15.9.3 Set the Transmitter Pins to Operate as McBSP Pins .................................................... 1136
15.9.4 Enable/Disable the Digital Loopback Mode................................................................ 1136
15.9.5 Enable/Disable the Clock Stop Mode....................................................................... 1136
15.9.6 Enable/Disable Transmit Multichannel Selection ......................................................... 1138
15.9.7 Choose One or Two Phases for the Transmit Frame .................................................... 1138
15.9.8 Set the Transmit Word Length(s) ........................................................................... 1138
15.9.9 Set the Transmit Frame Length ............................................................................. 1140
15.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function............................... 1141
15.9.11 Set the Transmit Companding Mode...................................................................... 1142
15.9.12 Set the Transmit Data Delay............................................................................... 1143

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15.9.13 Set the Transmit DXENA Mode............................................................................ 1145
15.9.14 Set the Transmit Interrupt Mode........................................................................... 1145
15.9.15 Set the Transmit Frame-Synchronization Mode......................................................... 1146
15.9.16 Set the Transmit Frame-Synchronization Polarity....................................................... 1147
15.9.17 Set the SRG Frame-Synchronization Period and Pulse Width........................................ 1148
15.9.18 Set the Transmit Clock Mode .............................................................................. 1149
15.9.19 Set the Transmit Clock Polarity............................................................................ 1149
15.10 Emulation and Reset Considerations ................................................................................ 1151
15.10.1 McBSP Emulation Mode.................................................................................... 1151
15.10.2 Resetting and Initializing McBSP.......................................................................... 1151
15.11 Data Packing Examples................................................................................................ 1153
15.11.1 Data Packing Using Frame Length and Word Length.................................................. 1153
15.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function............... 1155
15.12 McBSP Registers ....................................................................................................... 1155
15.12.1 Register Summary........................................................................................... 1156
15.12.2 Data Receive Registers (DRR[1,2])....................................................................... 1156
15.12.3 Data Transmit Registers (DXR[1,2]) ...................................................................... 1157
15.12.4 Serial Port Control Registers (SPCR[1,2]) ............................................................... 1158
15.12.5 Receive Control Registers (RCR[1, 2]) .................................................................. 1163
15.12.6 Transmit Control Registers (XCR1 and XCR2).......................................................... 1165
15.12.7 Sample Rate Generator Registers (SRGR1 and SRGR2) ............................................. 1168
15.12.8 Multichannel Control Registers (MCR[1,2]) .............................................................. 1170
15.12.9 Pin Control Register (PCR)................................................................................. 1175
15.12.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF,
RCERG, RCERH).............................................................................................. 1177
15.12.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF,
XCERG, XCERH) .............................................................................................. 1179
15.12.12 Interrupt Generation ....................................................................................... 1181
16 M3 Micro Direct Memory Access ( µDMA)........................................................................... 1185
16.1 Overview.................................................................................................................. 1186
16.2 Block Diagram ........................................................................................................... 1186
16.3 Functional Description.................................................................................................. 1187
16.3.1 Channel Assignments ........................................................................................ 1188
16.3.2 Priority .......................................................................................................... 1189
16.3.3 Arbitration Size ................................................................................................ 1189
16.3.4 Request Types ................................................................................................ 1189
16.3.5 Channel Configuration........................................................................................ 1190
16.3.6 Transfer Modes................................................................................................ 1191
16.3.7 Transfer Size and Increment ................................................................................ 1200
16.3.8 Peripheral Interface........................................................................................... 1200
16.3.9 Software Request ............................................................................................. 1200
16.3.10 Interrupts and Errors ........................................................................................ 1201
16.4 Initialization and Configuration......................................................................................... 1201
16.4.1 Module Initialization........................................................................................... 1201
16.4.2 Configuring a Memory-to-Memory Transfer ............................................................... 1201
16.4.3 Configuring a Peripheral for Simple Transmit ............................................................. 1203
16.4.4 Configuring a Peripheral for Ping-Pong Receive.......................................................... 1204
16.5 Register Map............................................................................................................. 1206
16.6 µDMA Channel Control Structure ..................................................................................... 1208
16.6.1 DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000......................... 1208
16.6.2 DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004.................... 1208
16.6.3 DMA Channel Control Word (DMACHCTL), offset 0x008 ............................................... 1209
16.7 µDMA Register Descriptions........................................................................................... 1212
16.7.1 DMA Status (DMASTAT), offset 0x000 .................................................................... 1212

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16.7.2 DMA Configuration (DMACFG), offset 0x004 ............................................................. 1213
16.7.3 DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008................................... 1213
16.7.4 DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C....................... 1214
16.7.5 DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010.............................. 1214
16.7.6 DMA Channel Software Request (DMASWREQ), offset 0x014 ........................................ 1214
16.7.7 DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018..................................... 1215
16.7.8 DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C.................................. 1215
16.7.9 DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 ............................... 1216
16.7.10 DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 1216
16.7.11 DMA Channel Enable Set (DMAENASET), offset 0x028............................................... 1216
16.7.12 DMA Channel Enable Clear (DMAENACLR), offset 0x02C............................................ 1217
16.7.13 DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030................................... 1217
16.7.14 DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................ 1218
16.7.15 DMA Channel Priority Set (DMAPRIOSET), offset 0x038.............................................. 1218
16.7.16 DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C........................................... 1218
16.7.17 DMA Bus Error Clear (DMAERRCLR), offset 0x04C ................................................... 1219
16.7.18 DMA Channel Assignment (DMACHALT), offset 0x500................................................ 1219
16.7.19 DMA Channel Map Assignment (DMACHMAP0) Register, offset 0x510 ............................ 1219
16.7.20 DMA Channel Map Assignment (DMACHMAP1) Register, offset 0x514 ............................ 1220
16.7.21 DMA Channel Map Assignment (DMACHMAP2) Register, offset 0x518 ............................ 1221
16.7.22 DMA Channel Map Assignment (DMACHMAP3) Register, offset 0x51C............................ 1222
16.7.23 DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ...................................... 1223
16.7.24 DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ...................................... 1224
16.7.25 DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ...................................... 1224
16.7.26 DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC...................................... 1224
16.7.27 DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ...................................... 1225
16.7.28 DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0......................................... 1225
16.7.29 DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4......................................... 1225
16.7.30 DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8......................................... 1226
16.7.31 DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................ 1226
17 External Peripheral Interface (EPI)..................................................................................... 1227
17.1 Introduction............................................................................................................... 1228
17.2 EPI Block Diagram...................................................................................................... 1229
17.3 Functional Description.................................................................................................. 1229
17.3.1 Non-Blocking Reads.......................................................................................... 1230
17.4 DMA Operation ......................................................................................................... 1231
17.5 Initialization and Configuration......................................................................................... 1231
17.6 SDRAM Mode ........................................................................................................... 1232
17.6.1 External Signal Connections................................................................................. 1233
17.6.2 Refresh Configuration ........................................................................................ 1233
17.6.3 Bus Interface Speed .......................................................................................... 1234
17.6.4 Non-Blocking Read Cycle.................................................................................... 1234
17.6.5 Normal Read Cycle ........................................................................................... 1234
17.6.6 Write Cycle..................................................................................................... 1235
17.7 Host Bus Mode .......................................................................................................... 1236
17.7.1 Control Pins.................................................................................................... 1236
17.7.2 Speed of Transactions........................................................................................ 1247
17.7.3 Sub-Modes of Host Bus 8/16................................................................................ 1248
17.7.4 Host Bus Operation........................................................................................... 1249
17.8 General-Purpose Mode................................................................................................. 1252
17.8.1 General Purpose Bus Operation ............................................................................ 1255
17.9 C28x Access to EPI..................................................................................................... 1260
17.9.1 Real-Time Window (RTW) ................................................................................... 1261

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17.9.2 Memory Protection............................................................................................ 1261
17.10 Register Map ............................................................................................................ 1262
17.11 Register Descriptions .................................................................................................. 1265
17.11.1 EPI Configuration Register (EPICFG), offset 0x000 .................................................... 1265
17.11.2 EPI Main Baud Rate (EPIBAUD) Register, offset 0x004............................................... 1266
17.11.3 EPI Main Baud Rate (EPIBAUD2) Register, offset 0x008 ............................................. 1267
17.11.4 EPI SDRAM Configuration (EPISDRAMCFG) Register, offset 0x010................................ 1268
17.11.5 EPI Host-Bus 8 Configuration (EPIHB8CFG) Register, offset 0x010................................. 1269
17.11.6 EPI Host-Bus 16 Configuration (EPIHB16CFG) Register. offset 0x010.............................. 1272
17.11.7 EPI General-Purpose Configuration (EPIGPCFG) Register, offset 0x010........................... 1275
17.11.8 EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) Register, Offset 0x014 ............................ 1278
17.11.9 EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Register, offset 0x014.......................... 1281
17.11.10 EPI General-Purpose Configuration 2 (EPIGPCFG2) Register, offset 0x014...................... 1284
17.11.11 EPI Address Map (EPIADDRMAP) Register, offset 0x01C........................................... 1285
17.11.12 EPI Read Size 0 (EPIRSIZE0) Register and EPI Read Size 1 (EPIRSIZE1) Register, offset
0x020 and 0x030............................................................................................... 1286
17.11.13 EPI Read Address 0 (EPIRADDR0) Register and EPI Read Address 1 (EPIRADDR1)
Register, offset 0x024 and 0x034............................................................................ 1288
17.11.14 EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register and EPI Non-Blocking Read Data 1
(EPIRPSTD1) Register, offset 0x028 and 0x038 .......................................................... 1288
17.11.15 EPI Status (EPISTAT) Register, offset 0x060.......................................................... 1290
17.11.16 EPI Read FIFO Count (EPIRFIFOCNT) Register, offset 0x06C..................................... 1291
17.11.17 EPI Read FIFO (EPIREADFIFO) Register and EPI Read FIFO Alias 1-7 (EPIREADFIFO1-7)
Registers, offset 0x070 and 0x08C .......................................................................... 1292
17.11.18 EPI FIFO Level Selects (EPIFIFOLVL) Register, 0x200.............................................. 1292
17.11.19 EPI Write FIFO Count (EPIWFIFOCNT) Register, offset 0x204..................................... 1294
17.11.20 EPI DMA Transmit Count (EPIDMATXCNT) Register, offset 0x208 ................................ 1295
17.11.21 EPI Interrupt Mask (EPIIM) Register, 0x210............................................................ 1295
17.11.22 EPI Raw Interrupt Status (EPIRIS) Register, offset 0x214 ........................................... 1296
17.11.23 EPI Masked Interrupt Status (EPIMIS) Register, offset 0x218....................................... 1297
17.11.24 EPI Error Interrupt Status and Clear (EPIEISC) Register, offset 0x21C............................ 1299
17.11.25 EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308 ...................................... 1300
17.11.26 EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), offset 0x308 ................................... 1301
17.11.27 EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), offset 0x30C...................................... 1302
17.11.28 EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), offset 0x30C................................... 1304
17.11.29 EPI Host-Bus 8 Timing Extension (EPIHB8TIME), offset 0x310..................................... 1305
17.11.30 EPI Host-Bus 16 Timing Extension (EPIHB16TIME), offset 0x310.................................. 1306
17.11.31 EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), offset 0x314 ................................... 1307
17.11.32 EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), offset 0x314 ................................ 1308
17.11.33 EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), offset 0x318 ................................... 1309
17.11.34 EPI Host-Bus 16 Timing Extension (EPIHB16TIME3) Register, offset 0x318 ..................... 1310
17.11.35 EPI Host-Bus 8 Timing Extension (EPIHB8TIME4) Register, offset 0x31C........................ 1311
17.11.36 EPI Host-Bus 16 Timing Extension (EPIHB16TIME4) Register, 0x31C ............................ 1312
17.11.37 CEPIRTWCFG Register................................................................................... 1313
17.11.38 CEPIRTWCNT Register................................................................................... 1313
17.11.39 CEPIRTWPRD Register................................................................................... 1314
17.11.40 CEPISTATUS Register.................................................................................... 1314
17.11.41 MEMPROT Register ...................................................................................... 1314
18 M3 Universal Serial Bus (USB) Controller .......................................................................... 1316
18.1 Introduction............................................................................................................... 1317
18.1.1 Block Diagram................................................................................................. 1317
18.2 Functional Description.................................................................................................. 1317
18.2.1 Operation as a Device........................................................................................ 1318
18.2.2 Operation as a Host........................................................................................... 1322

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18.2.3 OTG Mode ..................................................................................................... 1325
18.2.4 DMA Operation................................................................................................ 1327
18.3 Initialization and Configuration......................................................................................... 1328
18.3.1 Pin Configuration.............................................................................................. 1328
18.3.2 Endpoint Configuration ....................................................................................... 1328
18.4 Register Map............................................................................................................. 1329
18.5 Register Descriptions................................................................................................... 1337
18.5.1 USB Device Functional Address Register (USBFADDR), offset 0x000................................ 1337
18.5.2 USB Power Management Register (USBPOWER), offset 0x001....................................... 1338
18.5.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002 ..................................... 1340
18.5.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004...................................... 1342
18.5.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006 .................................... 1344
18.5.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008..................................... 1346
18.5.7 USB General Interrupt Status Register (USBIS), offset 0x00A ......................................... 1348
18.5.8 USB Interrupt Enable Register (USBIE), offset 0x00B................................................... 1350
18.5.9 USB Frame Value Register (USBFRAME), offset 0x00C................................................ 1352
18.5.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E............................................. 1352
18.5.11 USB Test Mode Register (USBTEST), offset 0x00F.................................................... 1353
18.5.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[15]).......................................... 1355
18.5.13 USB Device Control Register (USBDEVCTL), offset 0x060 ........................................... 1356
18.5.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062...................... 1358
18.5.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063...................... 1359
18.5.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064...................... 1360
18.5.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066...................... 1361
18.5.18 USB Connect Timing Register (USBCONTIM), offset 0x07A.......................................... 1362
18.5.19 USB OTG VBUS Pulse Timing Register (USBVPLEN), offset 0x07B................................ 1362
18.5.20 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset
0x07D............................................................................................................ 1363
18.5.21 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset
0x07E ............................................................................................................ 1363
18.5.22 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-
USBTXFUNCADDR[15]) ...................................................................................... 1364
18.5.23 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-
USBTXHUBADDR[15])........................................................................................ 1365
18.5.24 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[15]) ... 1366
18.5.25 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-
USBRXFUNCADDR[15])...................................................................................... 1367
18.5.26 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-
USBRXHUBADDR[15])........................................................................................ 1368
18.5.27 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]-USBRXHUBPORT[15]).... 1369
18.5.28 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[15]) ....... 1370
18.5.29 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102..................... 1371
18.5.30 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103.................... 1373
18.5.31 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108....................... 1374
18.5.32 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A........................................... 1374
18.5.33 USB NAK Limit Register (USBNAKLMT), offset 0x10B ................................................ 1375
18.5.34 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-
USBTXCSRL[15]) .............................................................................................. 1376
18.5.35 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-
USBTXCSRH[15]).............................................................................................. 1379
18.5.36 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[15]) ....... 1381
18.5.37 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-
USBRXCSRL[15]).............................................................................................. 1382
18.5.38 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-
USBRXCSRH[15]) ............................................................................................. 1385

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18.5.39 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[15]) ........ 1387
18.5.40 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[15])... 1388
18.5.41 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[15]) .1389
18.5.42 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[15]) ... 1390
18.5.43 USB Host Receive Polling Interval Endpoint n Register
(USBRXINTERVAL[1]USBRXINTERVAL[15]).............................................................. 1391
18.5.44 USB Request Packet Count in Block Transfer Endpoint n Registers
(USBRQPKTCOUNT[1]USBRQPKTCOUNT[15]).......................................................... 1392
18.5.45 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340..... 1393
18.5.46 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342 .... 1395
18.5.47 USB External Power Control Register (USBEPC), offset 0x400 ...................................... 1397
18.5.48 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404........ 1399
18.5.49 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408................. 1400
18.5.50 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C .1401
18.5.51 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410................. 1402
18.5.52 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414.................... 1403
18.5.53 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418........... 1404
18.5.54 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C.................... 1405
18.5.55 USB VBUS Droop Control Register (USBVDC), offset 0x430......................................... 1406
18.5.56 USB VBUS Droop Control Raw Interrupt Status Register (USBVDCRIS), offset 0x434........... 1407
18.5.57 USB VBUS Droop Control Interrupt Mask Register (USBVDCIM), offset 0x438.................... 1408
18.5.58 USB VBUS Droop Control Interrupt Status and Clear Register (USBVDCISC), offset 0x43C.... 1409
18.5.59 USB ID Valid Detect Raw Interrupt Status Register (USBIDVRIS), offset 0x444................... 1410
18.5.60 USB ID Valid Detect Interrupt Mask Register (USBIDVIM), offset 0x448............................ 1411
18.5.61 USB ID Valid Detect Interrupt Status and Clear Register (USBIDVISC), offset 0x44C............ 1412
18.5.62 USB DMA Select Register (USBDMASEL), offset 0x450 .............................................. 1413
19 M3 Ethernet Media Access Controller (EMAC) .................................................................... 1417
19.1 Introduction............................................................................................................... 1418
19.2 EMAC Block Diagram................................................................................................... 1418
19.3 Functional Description.................................................................................................. 1419
19.3.1 MAC Operation................................................................................................ 1419
19.3.2 Internal MII Operation ........................................................................................ 1422
19.3.3 Interrupts ....................................................................................................... 1422
19.3.4 DMA Operation................................................................................................ 1423
19.4 Initialization and Configuration......................................................................................... 1423
19.4.1 Software Configuration ....................................................................................... 1423
19.5 Register Map............................................................................................................. 1424
19.6 Ethernet MAC Register Descriptions ................................................................................. 1425
19.6.1 Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register, offset 0x000.. 1425
19.6.2 Ethernet MAC Interrupt Mask (MACIM) Register, offset 0x004......................................... 1426
19.6.3 Ethernet MAC Receive Control (MACRCTL) Register, offset 0x008................................... 1427
19.6.4 Ethernet MAC Transmit Control (MACTCTL) Register, offset 0x00C.................................. 1428
19.6.5 Ethernet MAC Data (MACDATA) Register, offset 0x010 ................................................ 1430
19.6.6 Ethernet MAC Individual Address 0 (MACIA0) Register, offset 0x014................................. 1431
19.6.7 Ethernet MAC Individual Address 1 (MACIA1) Register, offset 0x018................................. 1432
19.6.8 Ethernet MAC Threshold (MACTHR) Register, offset 0x01C ........................................... 1433
19.6.9 Ethernet MAC Management Control (MACMCTL) Register, offset 0x020............................. 1434
19.6.10 Ethernet MAC Management Divider (MACMDV) Register, offset 0x024............................. 1435
19.6.11 Ethernet MAC Management Address Register (MACMAR), offset 0x028 ........................... 1435
19.6.12 Ethernet MAC Management Transmit Data (MACMTXD) Register, offset 0x02C.................. 1435
19.6.13 Ethernet MAC Management Receive Data (MACMRXD) Register, offset 0x030................... 1437
19.6.14 Ethernet MAC Number of Packets (MACNP) Register, offset 0x034................................. 1437
19.6.15 Ethernet MAC Transmission Request (MACTR) Register, offset 0x038 ............................. 1438
19.6.16 Ethernet MAC Timer Support (MACTS) Register, offset 0x03C....................................... 1438

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19.7 MII Management Register Descriptions.............................................................................. 1439
19.7.1 Ethernet PHY Management Register 0 – Control (MR0) Register, address 0x00.................... 1439
19.7.2 Ethernet PHY Management Register 1 – Status (MR1) Register, address 0x01..................... 1441
19.7.3 Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Register , address 0x02......... 1442
19.7.4 Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3) Register, address 0x03 ......... 1442
19.7.5 Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4) Register,
address 0x04.................................................................................................... 1443
19.7.6 Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Register, address 0x05........................................................................................ 1444
19.7.7 Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Register, address
0x06.............................................................................................................. 1445
20 M3 Synchronous Serial Interface (SSI)............................................................................... 1446
20.1 Introduction............................................................................................................... 1447
20.2 Features .................................................................................................................. 1447
20.2.1 SSI Block Diagram............................................................................................ 1447
20.3 Functional Description.................................................................................................. 1448
20.3.1 Bit Rate Generation........................................................................................... 1449
20.3.2 FIFO Operation................................................................................................ 1449
20.3.3 Interrupts ....................................................................................................... 1449
20.3.4 Frame Formats ................................................................................................ 1450
20.3.5 DMA Operation................................................................................................ 1454
20.4 Initialization and Configuration......................................................................................... 1455
20.5 SSI Registers ............................................................................................................ 1456
20.5.1 SSI Base Addresses.......................................................................................... 1456
20.5.2 SSI_REGS Registers......................................................................................... 1457
21 M3 Universal Asynchronous Receivers/Transmitters (UARTs).............................................. 1488
21.1 Introduction............................................................................................................... 1489
21.2 Block Diagram ........................................................................................................... 1489
21.3 Functional Description.................................................................................................. 1490
21.3.1 Transmit/Receive Logic ...................................................................................... 1490
21.3.2 Baud-Rate Generation........................................................................................ 1491
21.3.3 Data Transmission ............................................................................................ 1491
21.3.4 Serial IR (SIR) ................................................................................................. 1492
21.3.5 ISO 7816 Support............................................................................................. 1493
21.3.6 LIN Support .................................................................................................... 1493
21.3.7 FIFO Operation................................................................................................ 1494
21.3.8 Interrupts ....................................................................................................... 1494
21.3.9 Loopback Operation .......................................................................................... 1495
21.3.10 DMA Operation............................................................................................... 1495
21.4 M3 UART4 to C28 SCI-A Internal Loopback ........................................................................ 1495
21.4.1 Loopback Initialization and Configuration.................................................................. 1496
21.5 Initialization and Configuration......................................................................................... 1496
21.6 Register Map............................................................................................................. 1497
21.7 Register Descriptions................................................................................................... 1498
21.7.1 UART Data Register (UARTDR), offset 0x000............................................................ 1498
21.7.2 UART Receive Status/Error Clear Register (UARTRSR/UARTECR), offset 0x004.................. 1499
21.7.3 UART Flag Register (UARTFR), offset 0x018............................................................. 1501
21.7.4 UART IrDA Low-Power Register (UARTILPR), offset 0x020............................................ 1503
21.7.5 UART Integer Baud-Rate Divisor Register (UARTIBRD), offset 0x024................................ 1503
21.7.6 UART Fractional Baud-Rate Divisor Register (UARTFBRD), offset 0x028 ........................... 1504
21.7.7 UART Line Control Register (UARTLCRH), offset 0x02C............................................... 1504
21.7.8 UART Control Register (UARTCTL), offset 0x030........................................................ 1505
21.7.9 UART Interrupt FIFO Level Select (UARTIFLS) Register, offset 0x034 ............................... 1507

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21.7.10 UART Interrupt Mask (UARTIM) Register, offset 0x038................................................ 1508
21.7.11 UART Raw Interrupt Status (UARTRIS), offset 0x03C ................................................. 1510
21.7.12 UART Masked Interrupt Status (UARTMIS), offset 0x040 ............................................. 1512
21.7.13 UART Interrupt Clear (UARTICR), offset 0x044......................................................... 1514
21.7.14 UART DMA Control (UARTDMACTL), offset 0x048 .................................................... 1515
21.7.15 UART LIN Control (UARTLCTL), offset 0x090 .......................................................... 1515
21.7.16 UART LIN Snap Shot (UARTLSS), offset 0x094........................................................ 1516
21.7.17 UART LIN Timer (UARTLTIM), offset 0x098............................................................. 1516
21.7.18 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.................................... 1517
21.7.19 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.................................... 1517
21.7.20 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.................................... 1517
21.7.21 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ................................... 1518
21.7.22 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.................................... 1518
21.7.23 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.................................... 1518
21.7.24 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.................................... 1519
21.7.25 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ................................... 1519
21.7.26 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0...................................... 1519
21.7.27 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4...................................... 1520
21.7.28 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8...................................... 1520
21.7.29 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ..................................... 1520
22 M3 Inter-Integrated Circuit (I2C) Interface........................................................................... 1521
22.1 Introduction............................................................................................................... 1522
22.2 I2C Block Diagram ...................................................................................................... 1522
22.3 Functional Description.................................................................................................. 1522
22.3.1 I2C Bus Functional Overview................................................................................ 1523
22.3.2 Available Speed Modes ...................................................................................... 1524
22.3.3 Interrupts ....................................................................................................... 1526
22.3.4 Loopback Operation .......................................................................................... 1527
22.3.5 Command Sequence Flow Charts.......................................................................... 1527
22.4 Initialization and Configuration......................................................................................... 1534
22.5 Register Map............................................................................................................. 1535
22.6 Register Descriptions................................................................................................... 1536
22.6.1 I2C Master Slave Address (I2CMSA), offset 0x000 ...................................................... 1536
22.6.2 I2C Master Control/Status (I2CMCS), offset 0x004 ...................................................... 1537
22.6.3 I2C Master Data (I2CMDR), offset 0x008.................................................................. 1541
22.6.4 I2C Master Timer Period (I2CMTPR), offset 0x00C...................................................... 1541
22.6.5 I2C Master Interrupt Mask (I2CMIMR), offset 0x010..................................................... 1542
22.6.6 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014.............................................. 1542
22.6.7 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018.......................................... 1543
22.6.8 I2C Master Interrupt Clear (I2CMICR), offset 0x01C..................................................... 1543
22.6.9 I2C Master Configuration (I2CMCR), offset 0x020 ....................................................... 1544
22.7 Register Descriptions (I2C Slave)..................................................................................... 1545
22.7.1 I2C Slave Own Address (I2CSOAR), offset 0x800 ....................................................... 1545
22.7.2 I2C Slave Control/Status (I2CSCSR), offset 0x804 ...................................................... 1545
22.7.3 I2C Slave Data (I2CSDR), offset 0x808.................................................................... 1546
22.7.4 I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C....................................................... 1546
22.7.5 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810................................................ 1547
22.7.6 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814............................................ 1547
22.7.7 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ....................................................... 1548
23 M3 Controller Area Network (CAN).................................................................................... 1549
23.1 Overview ................................................................................................................. 1550
23.1.1 Features ....................................................................................................... 1550
23.1.2 Functional Description ....................................................................................... 1550

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23.1.3 Block Diagram ................................................................................................ 1551
23.2 Operating Modes........................................................................................................ 1552
23.2.1 Initialization .................................................................................................... 1552
23.2.2 CAN Message Transfer (Normal Operation) .............................................................. 1552
23.2.3 Test Modes .................................................................................................... 1553
23.3 Multiple Clock Source .................................................................................................. 1557
23.4 Interrupt Functionality .................................................................................................. 1557
23.4.1 Message Object Interrupts .................................................................................. 1557
23.4.2 Status Change Interrupts .................................................................................... 1557
23.4.3 Error Interrupts ................................................................................................ 1558
23.5 Global Power-down Mode ............................................................................................. 1558
23.5.1 Entering Global Power-down Mode ........................................................................ 1558
23.5.2 Wakeup from Global Power-down Mode .................................................................. 1558
23.6 Local Power-down Mode .............................................................................................. 1558
23.6.1 Entering Local Power-down Mode ......................................................................... 1558
23.6.2 Wakeup from Local Power-down Mode ................................................................... 1558
23.7 Parity Check Mechanism .............................................................................................. 1559
23.7.1 Behavior on Parity Error ..................................................................................... 1559
23.8 Debug Mode ............................................................................................................ 1559
23.9 Module Initialization .................................................................................................... 1560
23.10 Configuration of Message Objects ................................................................................... 1560
23.10.1 Configuration of a Transmit Object for Data Frames ................................................... 1560
23.10.2 Configuration of a Transmit Object for Remote Frames ............................................... 1561
23.10.3 Configuration of a Single Receive Object for Data Frames ........................................... 1561
23.10.4 Configuration of a Single Receive Object for Remote Frames ....................................... 1561
23.10.5 Configuration of a FIFO Buffer ............................................................................ 1562
23.11 Message Handling ..................................................................................................... 1562
23.11.1 Message Handler Overview ............................................................................... 1562
23.11.2 Receive/Transmit Priority .................................................................................. 1563
23.11.3 Transmission of Messages in Event Driven CAN Communication ................................... 1563
23.11.4 Updating a Transmit Object ............................................................................... 1563
23.11.5 Changing a Transmit Object ............................................................................... 1564
23.11.6 Acceptance Filtering of Received Messages ............................................................ 1564
23.11.7 Reception of Data Frames ................................................................................. 1564
23.11.8 Reception of Remote Frames ............................................................................. 1564
23.11.9 Reading Received Messages ............................................................................. 1565
23.11.10 Requesting New Data for a Receive Object ........................................................... 1565
23.11.11 Storing Received Messages in FIFO Buffers .......................................................... 1565
23.11.12 Reading from a FIFO Buffer ............................................................................. 1565
23.12 CAN Bit Timing ......................................................................................................... 1566
23.12.1 Bit Time and Bit Rate ....................................................................................... 1567
23.12.2 Configuration of the CAN Bit Timing ..................................................................... 1572
23.13 Message Interface Register Sets .................................................................................... 1574
23.13.1 Message Interface Register Sets 1 and 2 ............................................................... 1575
23.13.2 IF3 Register Set ............................................................................................. 1576
23.14 Message RAM .......................................................................................................... 1576
23.14.1 Structure of Message Objects ............................................................................. 1577
23.14.2 Addressing Message Objects in RAM ................................................................... 1579
23.14.3 Message RAM Representation in Debug Mode ........................................................ 1580
23.15 CAN Control Registers................................................................................................. 1580
23.15.1 CAN Control Register (CAN CTL)......................................................................... 1581
23.15.2 Error and Status Register (CAN ES)...................................................................... 1583
23.15.3 Error Counter Register (CAN ERRC) ..................................................................... 1585

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23.15.4 Bit Timing Register (CAN BTR)............................................................................ 1585
23.15.5 Interrupt Register (CAN INT)............................................................................... 1586
23.15.6 Test Register (CAN TEST) ................................................................................. 1587
23.15.7 Parity Error Code Register (CAN PERR) ................................................................ 1588
23.15.8 Auto-Bus-On Time Register (CAN ABOTR) ............................................................. 1588
23.15.9 Transmission Request Registers (CAN TXRQ) ......................................................... 1589
23.15.10 New Data Registers (CAN NWDAT)..................................................................... 1590
23.15.11 Interrupt Pending Registers (CAN INTPND)............................................................ 1590
23.15.12 Message Valid Registers (CAN MSGVAL) ............................................................. 1591
23.15.13 Interrupt Multiplexer Registers (CAN INTMUX) ........................................................ 1591
23.15.14 IF1 and IF2 Command Registers (CAN IF1CMD, CAN IF2CMD)................................... 1592
23.15.15 IF1 and IF2 Mask Registers (CAN IF1MSK, CAN IF2MSK).......................................... 1594
23.15.16 IF1 and F2 Arbitration Registers (CAN IF1ARB, CAN IF2ARB) ..................................... 1595
23.15.17 IF1 and IF2 Message Control Registers (CAN IF1MCTL, CAN IF2MCTL)......................... 1596
23.15.18 IF1 and IF2 Data A and Data B Registers (CAN IF1DATA/DATB, CAN IF2DATA/DATB) ..... 1598
23.15.19 IF3 Observation Register (CAN IF3OBS)............................................................... 1599
23.15.20 IF3 Mask Register (CAN IF3MSK)....................................................................... 1600
23.15.21 IF3 Arbitration Register (CAN IF3ARB) ................................................................. 1600
23.15.22 IF3 Message Control Register (CAN IF3MCTL) ....................................................... 1601
23.15.23 IF3 Data A and Data B Registers (CAN IF3DATA/DATB)............................................ 1602
23.15.24 IF3 Update Enable Registers (CAN IF3UPD) .......................................................... 1603
24 Cortex-M3 Processor....................................................................................................... 1604
24.1 Overview.................................................................................................................. 1605
24.2 Block Diagram ........................................................................................................... 1605
24.3 Overview.................................................................................................................. 1606
24.3.1 System-Level Interface....................................................................................... 1606
24.3.2 System Component Details.................................................................................. 1606
24.4 Programming Model .................................................................................................... 1607
24.4.1 Processor Mode and Privilege Levels for Software Execution.......................................... 1607
24.4.2 Stacks........................................................................................................... 1607
24.4.3 Register Map................................................................................................... 1607
24.4.4 Register Descriptions......................................................................................... 1609
24.4.5 Exceptions and Interrupts.................................................................................... 1615
24.4.6 Data Types..................................................................................................... 1615
24.5 Memory Model........................................................................................................... 1615
24.6 Memory Regions, Types and Attributes.............................................................................. 1616
24.6.1 Memory System Ordering of Memory Accesses.......................................................... 1616
24.6.2 Behavior of Memory Accesses.............................................................................. 1616
24.6.3 Software Ordering of Memory Accesses................................................................... 1617
24.6.4 Bit-Banding..................................................................................................... 1618
24.6.5 Data Storage................................................................................................... 1619
24.6.6 Synchronization Primitives................................................................................... 1620
24.7 Exception Model......................................................................................................... 1621
24.7.1 Exception States .............................................................................................. 1621
24.7.2 Exception Types............................................................................................... 1621
24.7.3 Exception Handlers ........................................................................................... 1625
24.7.4 Vector Table ................................................................................................... 1625
24.7.5 Exception Priorities............................................................................................ 1626
24.7.6 Interrupt Priority Grouping.................................................................................... 1627
24.7.7 Exception Entry and Return.................................................................................. 1627
24.8 Fault Handling ........................................................................................................... 1629
24.8.1 Fault Types..................................................................................................... 1629
24.8.2 Fault Escalation and Hard Faults ........................................................................... 1630