STMicroelectronics STCF03 User manual

September 2007 Rev. 4 1/35
35
STCF03
High power white LED driver with I2C™ interface
Features
■Buck-boost dc/dc converter
■Drives one power white LED up to 800 mA from
2.7 V to 5.5 V in QFN
■Drives one power white LED up to 800 mA from
3.3 V to 5.5 V in BGA
■Efficient up to 92%
■Output current control
■1.8 MHz typ. fixed frequency PWM
■Synchronous rectification
■Full I2C control
■Operational modes:
– Shutdown mode
– Shutdown + NTC
– Ready mode + auxiliary red LED
– Flash mode: up to 800 mA
– Torch mode: up to 200 mA
■Soft and hard triggering of flash
■Flash and torch dimming with 16 exponential
values
■Dimmable red LED indicator auxiliary output
■Internally or externally timed flash operation
■Digitally programmable safety time-out in flash
mode
■LED overtemperature detection and protection
with external NTC resistor
■Opened and shorted led failure detection and
protection
■Chip over temperature detection and protection
■< 1 µA shutdown current
■Packages:
– QFN20 (4x4)
– TFBGA25 (3x3)
Applications
■Cell phone and smart phone
■Camera flashes/strobe
■PDAs and digital still cameras
Description
The STCF03 is a high efficiency power supply
solution to drive a single flash LED in camera
phone, PDAs and other hand-held devices. It is a
buck - boost converter to guarantee a proper LED
current control over all possible conditions of
battery voltage and output voltage; the output
current control ensure a good current regulation
over the forward voltage spread characteristics of
the Flash LED.
Thanks to the high efficiency of the converter
allows having the input current taken from the
battery remain under 1.5 A. (See continuous
description)
TFBGA25 (3x3)
QFN20 (4x4)
Table 1. Device summary
Order code Package Packaging
STCF03PNR QFN20 (4x4 mm) 4500 parts per reel
STCF03TBR (1) TFBGA25 (3x3 mm) 3000 parts per reel
1. Available on request.
www.st.com

STCF03
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Contents
1 Description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1 Buck-Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2 Logic pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.1 SCL, SDA pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.2 TRIG pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.3 ATN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2.4 ADD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2.5 TMSK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3 I2C BUS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.5 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.6 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.7 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.8 Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.9 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.10 Writing to multiple registers with incremental addressing . . . . . . . . . . . . 17
7.11 Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.12 Reading from multiple registers with incremental addressing . . . . . . . . . 18
8 Description of internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1 PWR_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.2 TRIG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

STCF03
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8.3 TCH_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.4 NTC_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.5 FTIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.6 TDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.7 FDIM_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.8 AUXI_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.9 AUXT_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.10 F_RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.11 LED_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.12 NTC_W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.13 NTC_H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.14 OT_F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.15 VOUTOK_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1 PowerON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2 Shutdown, shutdown with NTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.3 Ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.4 Single or multiple Flash using external (µP) temporization . . . . . . . . . . . 25
9.5 External (µP) temporization using TRIG_EN bit . . . . . . . . . . . . . . . . . . . . 26
9.6 Single Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . 26
9.7 Multiple Flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . 26
10 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

List of figures STCF03
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List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Pin connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Data validity on the I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Timing diagram on I2C Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Acknowledge on I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Writing to multiple register with incremental addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Reading from multiple registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Flash and Torch current vs. dimming value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. VOUTOK_N behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. IOTORCH vs T_DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. IOFLASH vs F_DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. IOAUX vs AUXI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18. IOFLASH vs Temp. VI= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 19. VFB2 vs Temp. at IO= 800 mA, VI= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20. IQvs Temp. VI= 5.5 V Ready-Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 21. Start-Up in Flash Mode 800mA at VI= 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. Line transient in Flash Mode 800 mA, change of VIfrom 2.7 V to 3.3 V in 10 µs. . . . . . . . 28

List of tables STCF03
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute maximum ratings (see note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5. List of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Electrical characteristics (TJ= 25°C, VI= 3.6 V, 2xCI = 10 µF, CO= 1 µF, L = 4.7 µH,
RFL = 0.27 ΩRTR = 1.8 Ω, RX= 15 KΩ, Typ. values @25°C, unless otherwise specified). 11
Table 7. Address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. I2C Register mapping function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Dimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Auxiliary led dimming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Torch Mode and Flash Mode dimming registers settings . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Status register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Description (continued) STCF03
6/35
1 Description (continued)
All the functions of the device are controlled through the I2C which helps bus that allows to
reduce logic pins on the package and to save PCB tracks on the board. Hard and soft-
triggering of Flash are both supported. The device includes many functions to protect the
chip and the power LED such as: a soft start control, chip over temperature detection and
protection as well as opened and shorted LED detection and protection. Besides, a digital
programmable Time Out function protects the LED in case of a wrong command from the
µP. An optional external NTC resistor is supported to protect the LED against over heating.
In mobile phone applications it is possible to reduce immediately the Flash LED current
during the signal transmission using the TMSK pin. This saves battery life and gives more
priority to supply RF transmission instead of flash function.
It is possible by I2C to separately program the current intensity in FLASH and TORCH
MODE using exponential steps. An auxiliary output can control an optional red LED to be
used as a recording indicator.
The device is packaged in QFN 4x4 20L with a height less than 1 mm and in TFBGA25 3x3.

Diagram STCF03
7/35
2 Diagram
Figure 1. Block diagram

Pin configuration STCF03
8/35
3 Pin configuration
Figure 2. Pin connections (bottom view)
TFBGA25 (3x3)
QFN20 (3x3)
Table 2. Pin description
Pin n° for
QFN20
Pin n° for
TFBGA25 Symbol Name and function
1 E1, D2 VLX2 Inductor connection
2 B3 RX Rx resistor connection
3 A4 NTC NTC resistor connection
4 D1, C2 VOUT Output voltage
5B5
FB1 Feedback pin [ILED*(RFL+RTR)]
6A5
FB2 RTR bypass
7B4
FB2S Feedback sensing pin [ILED*RFL]
8 E2 GND Signal ground
9D4
ADD I2C address selection
10 D5 AUXL Auxiliary LED output
11 C5 TMSK TX mask input.
12 B1, C1 PVBAT Power supply voltage
13 A3 VBAT Supply voltage
14 A2 VLX1A Inductor connection
15 A1, B2 VLX1B Inductor connection
16 E5 SCL I2C clock signal
17 E3 SDA I2C data
18 C3, D3 PGND Power ground
19 E4 ATN Attention (open drain output, active LOW)
20 C4 TRIG Flash trigger input
Exposed pad PGND To be connected to the PCB ground plane for optimal electrical and
thermal performance.

Maximum ratings STCF03
9/35
4 Maximum ratings
Note: Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these condition is not implied.
Table 3. Absolute maximum ratings (see note)
Symbol Parameter Value Unit
VBAT Signal supply voltage -0.3 to 6 V
PVBAT Power supply voltage -0.3 to 6 V
VLX1A, VLX1B Inductor connection 1 –0.3 to VI+0.3 V
VLX2 Inductor connection 2 –0.3 to VO+0.3 V
VOUT Output voltage -0.3 to 6 V
AUXL Auxiliary LED –0.3 to VI+0.3 V
FB1, FB2, FB2S Feedback and sense voltage -0.3 to 3 V
SCL, SDA, TRIG,
ATN, ADD TMSK
Logic Pin -0.3 to VI+0.3 V
RXConnection for reference resistor -0.3 to 3 V
NTC Connection for LED Temperature sensing -0.3 to 3 V
ESD Human body model ±2kV
PTOT (BGA) (1)
1. Power dissipation is related parameter to used PCB. The recommended PCB design is included in the application note.
Continuous power dissipation (at TA=70°C) 800 mW
TOP Operating junction temperature range -40 to 85 °C
TJJunction temperature -40 to 150 °C
TSTG Storage temperature range -65 to 150 °C
Table 4. Thermal data
Symbol Parameter QFN20 TFBGA25 Unit
RthJA Thermal resistance junction-ambient 59 150 °C/W

Application STCF03
10/35
5 Application
**: Connect to VI, or GND or SDA or SCL to choose one of the 4 different I2C Slave Addresses.
***: Optional components to support auxiliary functions.
Note: All of the above listed components refer to typical application. Operation of the STCF03 is
not limited to the choice of these external components.
Figure 3. Application schematic
Table 5. List of external components
Component Manufacturer Part number Value Size
CITDK X5R0J106M 10 µF 0603
COTDK X5R0J105M 1 µF 0603
L (IFLASH = 0.5A) TDK VLF3012ST-4R7MR91 4.7 µH 2.6 x 2.8 x 1.2mm
L (IFLASH = 0.8A) TDK VLF4012AT-4R7M1R1 4.7 µH 3.7 x 3.5 x 1.2mm
NTC Murata NCP21WF104J03RA 100kΩ0805
RFL 0.27Ω0603
RTR 1.8Ω0402
RX15kΩ0402

Electrical characteristics STCF03
11/35
6 Electrical characteristics
Table 6. Electrical characteristics
(TJ = 25°C, VI= 3.6 V, 2xCI= 10 µF, CO = 1 µF, L = 4.7 µH, RFL = 0.27 ΩRTR = 1.8 Ω, RX = 15 KΩ,
Typ. values @25°C, unless otherwise specified).
Symbol Parameter Test condition Min. Typ. Max. Unit
VIInput operation supply voltage 2.7 5.5 V
VPW_ON
RESET
Power ON reset threshold VIrising 2.3 V
IOOutput current adjustment
range IFLASH
FLASH MODE for VI = 2.7 V to 5.5 V
(STCF03PNR)
60 800 mA
FLASH MODE for VI = 2.7 V to 3.3 V
(STCF03TBR)
60 600
FLASH MODE for VI=3.3 V to 5.5 V
(STCF03TBR)
60 800
Output current adjustment
range ITORCH
Torch mode VI= 2.7 V to 5.5 V 15 200
Auxiliary LED output current
adjustment range IAUXLED
Ready mode, VI = 3.3 V to 5.5 V 0 20
VORegulated voltage range 2.5 5.3 V
FB1 Feedback voltage Torch mode 30 250 mV
FB2 Feedback voltage Flash mode 30 250 mV
ΔIOOutput current tolerance Flash mode, IO = 160 mV/RFL -10 10 %
RON_ FB1-FB2 ON resistance Torch mode, IO = 200 mA 90 mΩ
IQQuiescent current in
SHUTDOWN mode
NTC_ON=0 1 µA
NTC_ON=1 1
Quiescent current in ready -
mode
1.8 mA
fsFrequency VI = 2.7 V 1.8 MHz
νEfficiency of the chip itself VI= 3.2 to 4.2 V, Flash Mode,
IO = 800 mA
87 %
Efficiency of the whole
application
VI = 3.2 to 4.2 V, Flash Mode,
IO = 800 mA, VO=VfLED_max + VFB2 =
5.02 V
See the typical application schematic
It is included losses of inductor and
sensing resistor
76
OVP Output over voltage protection VI = 5.5 V, No Load 5.3 V
OVHYST Over voltage hysteresis VI= 5.5 V, No Load 0.3 V
OTP Over temperature protection VI = 5.5 V 140 °C
OTHYST Over temperature hysteresis VI = 5.5 V 20 °C

Electrical characteristics STCF03
12/35
Note: Typical value, not production tested.
RONT1 RX-NTC switch ON resistance Ready mode 25 Ω
NTCLEAK RX-NTC switch OFF leakage Shutdown mode, VNTC = 2 V
VRX = GND
1µA
VOL Output logic signal level low
AT N
IOL = 10 mA 0.2 V
IOZ Output logic leakage current
AT N
VOZ = 3.3 V 1 mA
VIL Input logic signal level SCL,
SDA, TRIG, TEST, ADD
VI = 2.7 V to 5.5 V 0 0.4 V
VIH 1.4 3
TON LED current rise time ILED = 0
to ILED = max
2ms
Table 6. Electrical characteristics
(TJ = 25°C, VI= 3.6 V, 2xCI= 10 µF, CO = 1 µF, L = 4.7 µH, RFL = 0.27 ΩRTR = 1.8 Ω, RX = 15 KΩ,
Typ. values @25°C, unless otherwise specified).
Symbol Parameter Test condition Min. Typ. Max. Unit

Introduction STCF03
13/35
7 Introduction
The STCF03 is a buck-boost converter, dedicated to power and control the current of a
Power White LED in a camera cell phone. The device operates at a constant switching
frequency of 1.8 MHz typ. It provides an output voltage down to 2.5 V and up to 5.3 V, from
a 2.7 V to 5.5 V supply voltage. This supply range allows operation from a single cell
Lithium-Ion battery. The I2C bus is used to control the device operation and for diagnostic
purposes. The current in Torch mode is adjustable from 15 mA to 200 mA. Flash mode
current is adjustable up to 800 mA, BGA version is able to deliver 600 mA at battery range
2.7 V to 3.3 V. The Aux LED current can be adjusted from 0 to 20 mA. The device uses an
external NTC resistor to sense the temperature of the white LED. These two last functions
may not be needed in all applications, and in these cases the relevant external components
can be omitted.
7.1 Buck-Boost converter
The regulation of the PWM controller is done by sensing the current of the LED through
external sensing resistors (RFL and RTR, see application schematic). Depending on the
forward voltage of the Flash LED, the device automatically can change the operation mode
between buck (step down) and boost (step up) mode.
Three cases can occur: Boost region (VO> VBAT): this configuration is used in most of the
cases, as the output voltage VO= VfLED + ILED x RFL) is higher than VBAT; Buck region (VO
< VBAT); Buck / Boost region (VO ~ VBAT).
7.2 Logic pin description
7.2.1 SCL, SDA pins
These are the standard Clock and Data pins as defined in the I2C bus specification. External
pull-up is required according to I2C bus specifications. The recommended maximum voltage
of these signals should be 3.0 V.
7.2.2 TRIG pin
This input pin is internally AND-ed with the TRIG_EN bit to generate the internal signal that
activates the flash operation. This gives to the user the possibility to accurately control the
flash duration using a dedicated pin, avoiding the I2C bus latencies (hard-triggering). No
internal pull-up nor pull-down is provided.
7.2.3 ATN pin
This output pin (open-drain, active LOW) is provided to better manage the information
transfer from the STCF03 to the µP. Because of the limitations of a Single Master I2C bus
configuration, the µP should regularly poll the STCF03 to verify if certain operations have
been completed, or to check diagnostic information. Alternatively, the µP can use the ATN
pin to be advised that new data are available in the STAT_REG, thus avoiding continuous
polling. Then the information can be read in the STAT_REG by a read operation via I2C that,
besides, automatically resets the ATN pin. The STAT_REG bits affecting the ATN pin status
are mapped in Ta bl e 1 6 . No internal pull-up is provided.

Introduction STCF03
14/35
7.2.4 ADD pin
With this pin it is possible to select one of the 4 possible I2C slave addresses. No internal
pull-up nor pull-down is provided. The pin has to be connected either GND, VI, SCL or SDA
to select the desired I2C slave address (see Table 6.)
7.2.5 TMSK pin
This pin can be used to implement the TX masking function. This function has effect only for
Flash current settings higher than 200 mA (bit FDIM_3=1). Under this condition, when this
pin is pulled high by the P, the current flowing in the LED is forced at 200 mA typ. No internal
pull-up nor pull-down is provided: to be externally wired to GND if TX masking function is not
used.
7.3 I2C BUS interface
Data transmission from the main µP STCF03 and vice versa takes place through the 2 wires
I2C bus interface wires, consisting of the two lines SDA and SCL (pull-up resistors to a
positive supply voltage must be externally connected). The recommended maximum voltage
of these signals should be 3.0 V.
7.4 Data validity
As shown in Figure 4, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
Table 7. Address table
ADD pin A7 A6 A5 A4 A3 A2 A1 A0
GND0110000R/W
VBAT0110001R/W
SDAL0110010R/W
SCL0110011R/W
Figure 4. Data validity on the I2C Bus

Introduction STCF03
15/35
7.5 Start and stop conditions
Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 5 a
start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition
must be sent before each START condition
7.6 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock
pulse. The data on the SDA line must remain stable during the HIGH period of the clock
pulse. Any change in the SDA line at this time will be interpreted as a control signal.
Figure 5. Timing diagram on I2C Bus
Figure 6. Bit transfer

Introduction STCF03
16/35
7.7 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7). The peripheral (STCF03) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate an acknowledge
pulse after the reception of each byte, otherwise the SDA line remains at the HIGH level
during the ninth clock pulse duration. In this case the master transmitter can generate the
STOP information in order to abort the transfer. The STCF03 won't generate the
acknowledge if the VIsupply is below the undervoltage lockout threshold.
7.8 Writing to a single register
Writing to a single register starts with a START bit followed by the 7 bit device address of
STCF03. The 8th bit is the R/W bit, which is 0 in this case. R/W = 1 means a reading
operation. Then the master waits for an acknowledge from STCF03. Then the 8 bit address
of register is sent to STCF03. It is also followed by an acknowledge pulse. The last
transmitted byte is the data that is going to be written to the register. It is again followed by
an acknowledge pulse from STCF03. Then master generates a STOP bit and the
communication is over. See Figure 8 below.
Figure 7. Acknowledge on I2C Bus
Table 8. Interface protocol
Device address + R/W bit Register address Data
76543210 76543210 76543210
S
T
A
R
T
M
S
B
L
S
B
R
W
A
C
K
M
S
B
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
S
T
O
P

Introduction STCF03
17/35
7.9 Interface protocol
The interface protocol is composed:
- A start condition (START)
- A Device address + R/W bit (read =1 / write =0)
- A Register address byte
- A sequence of data n* (1 byte + acknowledge)
- A stop condition (STOP)
The Register address byte determines the first register in which the read or write operation
takes place. When the read or write operation is finished, the register address is
automatically increased.
7.10 Writing to multiple registers with incremental addressing
It would be unpractical to send several times the device address and the address of the
register when writing to multiple registers. STCF03 supports writing to multiple registers with
incremental addressing. When the data is written to a register, the address register is
automatically increased, so the next data can be sent without sending the device address
and the register address again. See Figure 9 below.
Figure 8. Writing to a single register
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER DATA
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER DATA
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER DATA
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
SDA LINE

Introduction STCF03
18/35
7.11 Reading from a single register
The reading operation starts with a START bit followed by the 7 bit device address of
STCF03. The 8th bit is the R/W bit, which is 0 in this case. STCF03 confirms the receiving of
the address + R/W bit by an acknowledge pulse. The address of the register which should
be read is sent afterwards and confirmed again by an acknowledge pulse of STCF03 again.
Then the master generates a START bit again and sends the device address followed by the
R/W bit, which is 1 now. STCF03 confirms the receiving of the address + R/W bit by an
acknowledge pulse and starts to send the data to the master. No acknowledge pulse from
the master is required after receiving the data. Then the master generates a STOP bit to
terminate the communication. See Figure 10
7.12 Reading from multiple registers with incremental addressing
Reading from multiple registers starts in the same way like reading from a single register. As
soon as the first register is read, the register address is automatically increased. If the
master generates an acknowledge pulse after receiving the data from the first register, then
reading of the next register can start immediately without sending the device address and
Figure 9. Writing to multiple register with incremental addressing
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER i DATA i
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER i DATA i
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
A
C
K
ADDRESS OF
REGISTER i DATA i
A
C
K
A
C
K
S
T
O
P
M
S
B
M
S
B
L
S
B
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
A
C
K
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
SDA LINE
Figure 10. Reading from a single register
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS
OF
REGISTER
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits DATA
L
S
B
S
T
O
P
N
O
A
C
K
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS
OF
REGISTER
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits DATA
L
S
B
S
T
O
P
N
O
A
C
K
SDA LINE

Introduction STCF03
19/35
the register address again. The last acknowledge pulse before the STOP bit is not required.
See the Figure 11.
Figure 11. Reading from multiple registers
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS OF
REGISTER i
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits DATA i
A
C
K
S
T
O
P
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
N
O
A
C
K
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS OF
REGISTER i
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits DATA i
A
C
K
S
T
O
P
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
N
O
A
C
K
SDA LINE

Description of internal registers STCF03
20/35
8 Description of internal registers
8.1 PWR_ON
When set, it activates all analog and power internal blocks including the NTC supporting
circuit, and the device is ready to operate (Ready Mode). As long as PWR_ON=0, only the
I2C interface is active, minimizing Stand-by Mode power consumption.
8.2 TRIG_EN
This bit is AND-ed with the TRIG pin to generate the internal signal FL_ON that activates
Flash Mode. By this way, both soft-triggering and hard-triggering of the Flash are made
possible. If soft-triggering (through I2C) is chosen, the TRIG pin is not used and must be
kept HIGH (VI). If hard-triggering is chosen, then the TRIG pin has to be connected to a µP
I/O devoted to Flash timing control, and the TRIG_EN bit must be set in advance. Both
triggering modes can benefit of the internal Flash Time Counter, that uses the TRIG_EN bit
and can work either as a safety shut-down timer or as a Flash duration timer. Flash mode
can start only if PWR_ON=1. LED current is controlled by the value set by the FDIM_0~3 of
the DIM_REG.
8.3 TCH_ON
When set from Ready Mode, the STCF03 enters the Torch mode. The LED current is
controlled by the value set by the TDIM_0~3 of the DIM_REG.
8.4 NTC_ON
In ready mode, the comparators that monitor the LED temperature are activated if NTC_ON
bit is set. NTC-related blocks are always active regardless of this bit in Torch mode and
Flash mode.
Table 9. I2C Register mapping function
Register name SUB ADDRESS (hex) Operation
CMD_REG 00 R / W
DIM_REG 01 R / W
AUX_REG 02 R / W
STAT_REG 03 R only
Table 10. Command register
CMD_REG
(write mode) MSB LSB
SUB ADD=00 PWR_ON TRIG_EN TCH_ON NTC_ON FTIM_3 FTIM_2 FTIM_1 FTIM_0
Power ON
RESET Value
0 0 000000