STMicroelectronics STM32L100RC User manual

This is information on a product in full production.
March 2015 DocID024995 Rev 4 1/104
STM32L100RC
Ultra-low-power 32b MCU ARM®-based Cortex®-M3, 256KB Flash,
16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC, memory I/F
Datasheet −production data
Features
•Ultra-low-power platform
– 1.65 V to 3.6 V power supply
–-40 °C to 105 °C temperature range
– 0.29 µA Standby mode (3 wakeup pins)
–1.15 µA Standby mode + RTC
– 0.44 µA Stop mode (16 wakeup lines)
– 1.4 µA Stop mode + RTC
– 8.6 µA Low-power run mode
– 185 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
•Core: ARM®Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 1.25 DMIPS/MHz (Dhrystone 2.1)
– Memory protection unit
•Reset and supply management
– Low-power,ultrasafeBOR(brownoutreset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
•Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz
– PLL for CPU clock and USB (48 MHz)
•Pre-programmed bootloader
– USB and USART supported
•Development support
– Serial wire debug supported
– JTAG supported
•51 fast I/Os (42 I/Os 5V tolerant), all mappable
on 16 external interrupt vectors
•Memories
– 256 KB Flash memory with ECC
– 16 KB RAM
– 4 KB of true EEPROM with ECC
– 20 Byte backup register
•LCD Driver for up to 8x28 segments
•Analog peripherals
– 12-bit ADC 1Msps up to 20 channels
– 12-bit DACs 2 channels with output buffers
– 2x ultra-low-power-comparators
(window mode and wakeup capability)
•DMA controller 12x channels
•9x peripheral communication interfaces
– 1xUSB 2.0 (internal 48 MHz PLL)
–3xUSART
– 3xSPI 16 Mbits/s (2x SPI with I2S)
– 2xI2C (SMBus/PMBus)
•10x timers: 6x 16-bit with up to 4 IC/OC/PWM
channels, 2x 16-bit basic timers, 2x watchdog
timers (independent and window)
•CRC calculation unit
LQFP64 (10 × 10 mm)
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Contents STM32L100RC
2/104 DocID024995 Rev 4
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 ARM®Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22
3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10.1 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 25
3.13 System configuration controller and routing interface . . . . . . . . . . . . . . . 25
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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3.14.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 27
3.15.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.16 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 28
3.17 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 45
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Contents STM32L100RC
4/104 DocID024995 Rev 4
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.19 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.20 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.21 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.1 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
8 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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DocID024995 Rev 4 5/104
STM32L100RC
6
List of tables
Table 1. Ultra-low-power STM32L100RC device features and peripheral counts . . . . . . . . . . . . . . 10
Table 2. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14
Table 3. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. STM32L100RC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 10. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 11. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 13. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 14. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 15. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 16. Current consumption in Run mode, code with data processing running from Flash. . . . . . 49
Table 17. Current consumption in Run mode, code with data processing running from RAM . . . . . . 50
Table 18. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19. Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20. Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 21. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 22. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 56
Table 23. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 24. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 27. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 28. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 29. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 30. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 31. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 32. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 33. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 34. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 35. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 69
Table 36. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 37. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 38. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 39. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 40. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 41. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 42. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 43. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 44. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 45. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 46. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 47. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 79
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List of tables STM32L100RC
6/104 DocID024995 Rev 4
Table 48. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 49. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 50. USB DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 51. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 52. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 53. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 54. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 55. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 56. Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 57. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 58. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 59. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 60. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 61. LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 62. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . . 98
Table 63. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 64. STM32L100RC ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 65. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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STM32L100RC
7
List of figures
Figure 1. Ultra-low-power STM32L100RC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. STM32L100RC LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 5. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 9. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 10. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. HSE oscillator circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 13. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 14. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 15. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 16. I2C bus AC waveforms and measurement circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 17. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 18. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 19. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 20. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 21. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 22. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 23. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 24. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 25. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 26. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 27. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 97
Figure 28. LQFP64 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 29. LQFP64 device marking example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 30. Thermal resistance suffix 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 31. Thermal resistance suffix 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Introduction STM32L100RC
8/104 DocID024995 Rev 4
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L100RC ultra-low-power ARM®Cortex®-M3 based microcontroller product line.
The ultra-low-power STM32L100RC device is a microcontroller of 256 Kbytes in a 64-pin
package, the description below gives an overview of the complete range of peripherals
proposed in this device.
These features make the ultra-low-power STM32L100RC microcontroller suitable for a wide
range of applications:
•Medical and handheld equipment
•Application control and user interface
•PC peripherals, gaming, GPS and sport equipment
•Alarm systems, wired and wireless sensors, video intercom
•Utility metering
This STM32L100RC datasheet should be read in conjunction with the STM32L1xxxx
reference manual (RM0038). The application note “Getting started with STM32L1xxxx
hardware development” (AN3216) gives a hardware implementation overview. Both
documents are available from the STMicroelectronics website www.st.com.
For information on the ARM®Cortex®-M3 core please refer to the ARM®Cortex®-M3
technical reference manual, available from the www.arm.com website. Figure 1 shows the
general block diagram of the device.
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STM32L100RC
39
2 Description
The ultra-low-power STM32L100RC device incorporates the connectivity power of the
universal serial bus (USB) with the high-performance ARM®Cortex®-M3 32-bit RISC core
operating at a frequency of 32 MHz (33.3 DMIPS), a memory protection unit (MPU), high-
speed embedded memories (Flash memory up to 256 Kbytes and RAM up to 16 Kbytes)
and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
The STM32L100RC device offers one 12-bit ADC, two DACs, two ultra-low-power
comparators, six general-purpose 16-bit timers and two basic timers, which can be used as
time bases.
Moreover, the STM32L100RC device contains standard and advanced communication
interfaces: up to two I2Cs, three SPIs, two I2S, three USARTs, and an USB.
It also includes a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller has a built-in LCD voltage generator that allows to
drive up to 8 multiplexed LCDs with the contrast independent of the supply voltage.
The ultra-low-power STM32L100RC device operates from a 1.8 to 3.6 V power supply
(down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without
BOR option. It is available in the -40 to +85 °C and -40 to +105 °C temperature ranges. A
comprehensive set of power-saving modes allows the design of low-power applications.
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Description STM32L100RC
10/104 DocID024995 Rev 4
2.1 Device overview
2.2 Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8-
bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer your needs, in terms of ultra-low-power features. The STM32 Ultra-low-powerseries
are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare,
wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others will clearly allow you to build very cost-optimized applications by reducing BOM.
Table 1. Ultra-low-power STM32L100RC device features and peripheral counts
Peripheral STM32L100RC
Flash (Kbytes) 256
Data EEPROM (Kbytes) 4
RAM (Kbytes) 16
16-bit
Timers
General-
purpose 6
Basic 2
Communica
tion
interfaces
SPI/(I2S) 3/(2)
I2C2
USART 3
USB 1
GPIOs 51
12-bit synchronized ADC
Number of channels 1 20
12-bit DAC
Number total of channels 2 2
LCD
COM x SEG 4x32 or 8x28
Comparators 2
Max. CPU frequency 32 MHz
Operating voltage 1.8 V to 3.6 V
Operating temperatures Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: –40 to + 110 °C
Package LQFP64
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DocID024995 Rev 4 11/104
STM32L100RC
39
Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, your old applications can be upgraded to respond to the latest market features
and efficiency demand.
2.2.1 Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2 Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
•Analog peripherals: ADC, DAC and comparators
•Digital peripherals: RTC and some communication interfaces
2.2.3 Common system strategy.
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
•Same power supply range from 1.65 V to 3.6 V
•Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
•Fast startup strategy from low-power modes
•Flexible system clock
•Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
2.2.4 Features
ST ultra-low-power continuum also lies in feature compatibility:
•More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
•Memory density ranging from 2 to 512 Kbytes
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Functional overview STM32L100RC
12/104 DocID024995 Rev 4
3 Functional overview
Figure 1. Ultra-low-power STM32L100RC block diagram
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STM32L100RC
39
3.1 Low-power modes
The ultra-low-power STM32L100RC device supports dynamic voltage scaling to optimize its
power consumption in run mode. The voltage from the internal low-drop regulator that
supplies the logic can be adjusted according to the system’s maximum operating frequency
and the external voltage supply.
There are three power consumption ranges:
•Range 1 (VDD range limited to 2.0 V - 3.6 V), with the CPU running at up to 32 MHz
•Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
•Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In low-power
run mode, the clock frequency and the number of enabled peripherals are both limited.
•Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
•Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
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Functional overview STM32L100RC
14/104 DocID024995 Rev 4
•Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
•Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 2. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power
supply range DAC and ADC operation USB Dynamic
voltage scaling
range I/O operation
VDD = 1.8 to 2.0 V Conversiontime
up to 500 Ksps Not functional Range 2 or range 3 Degraded speed performance
VDD = 2.0 to 2.4 V Conversiontime
up to
500 Ksps Functional(1)
1. To be USB compliant from the IO voltage standpoint, the minimum VDD is 3.0 V.
Range 1, range 2
or range 3 Full speed operation
VDD = 2.4 to 3.6 V Conversiontime up to
1 Msps Functional(1) Range 1, range 2
or range 3 Full speed operation
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Table 3. CPU frequency range depending on dynamic voltage scaling
CPU frequency range Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws) Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws) Range 2
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws) Range 3
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Functional overview STM32L100RC
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Table 4. Functionalities depending on the working mode (from Run/active down to
standby)
Ips Run/Active Sleep Low- power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability Wakeup capability
CPU Y -- Y -- -- -- -- --
Flash Y Y Y Y -- -- -- --
RAM Y Y Y Y Y -- -- --
Backup Registers Y Y Y Y Y -- Y --
EEPROM Y Y Y Y Y -- -- --
Brown-out rest
(BOR) YYYYYYY--
DMA Y Y Y Y -- -- -- --
Programmable
Voltage Detector
(PVD) YYYYYYY--
Power On Reset
(POR) YYYYYYY--
Power Down Rest
(PDR) YYYYY--Y--
High Speed
Internal (HSI) Y Y -- -- -- -- -- --
High Speed
External (HSE) Y Y -- -- -- -- -- --
LowSpeed Internal
(LSI) YYYYY------
Low Speed
External (LSE) YYYYY------
Multi-Speed
Internal (MSI) Y Y Y Y -- -- -- --
Inter-Connect
Controller Y Y Y Y -- -- -- --
RTC Y Y Y Y Y Y Y --
RTC Tamper Y Y Y Y Y Y Y Y
Auto WakeUp
(AWU) YYYYYYYY
LCD Y Y Y Y Y -- -- --
USB Y Y -- -- -- Y -- --
USART Y Y Y Y Y (1) -- --
SPI Y Y Y Y -- -- -- --
I2C Y Y Y Y -- (1) -- --
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3.2 ARM®Cortex®-M3 core with MPU
The ARM®Cortex®-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM®Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit device.
ADC Y Y -- -- -- -- -- --
DAC Y Y Y Y Y -- -- --
Tempsensor Y Y Y Y Y -- -- --
OP amp Y Y Y Y Y -- -- --
Comparators Y Y Y Y Y Y -- --
16-bit and 32-bit
Timers Y Y Y Y -- -- -- --
IWDG Y Y Y Y Y Y Y Y
WWDG Y Y Y Y -- -- -- --
Touch sensing Y Y -- -- -- -- -- --
Systic Timer Y Y Y Y -- -- --
GPIOs Y Y Y Y Y Y -- 3 pins
Wakeup time to
Run mode 0 µs 0.4 µs 3 µs 46 µs < 8 µs 58 µs
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to 185
µA/MHz (from
Flash)
Down to 34.5
µA/MHz (from
Flash)
Down to
8.6 µA Down to 4.4 µA
0.43 µA
(no RTC)
VDD=1.8V
0.29 µA
(no RTC)
VDD=1.8V
1.15 µA
(with RTC)
VDD=1.8V
0.9 µA
(with RTC)
VDD=1.8V
0.44 µA
(no RTC)
VDD=3.0V
0.29 µA
(no RTC)
VDD=3.0V
1.4 µA
(with RTC)
VDD=3.0V
1.15 µA
(with RTC)
VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
Table 4. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Ips Run/Active Sleep Low- power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability Wakeup capability
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Functional overview STM32L100RC
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The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L100RC device is compatible with all ARM
tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L100RC device embeds a nested vectored interrupt controller
able to handle up to 52 maskable interrupt channels (not including the 16 interrupt lines of
ARM®Cortex®-M3) and 16 priority levels.
•Closely coupled NVIC gives low-latency interrupt processing
•Interrupt entry vector table address passed directly to the core
•Closely coupled NVIC core interface
•Allows early processing of interrupts
•Processing of late arriving, higher-priority interrupts
•Support for tail-chaining
•Processor state automatically saved
•Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3 Reset and supply management
3.3.1 Power supply schemes
•VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
•VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
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power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for a device with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3 Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
•MR is used in Run mode (nominal regulation)
•LPR is used in the Low-power run, Low-power sleep and Stop modes
•Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
•Boot from Flash memory
•Boot from System memory
•Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1 and USART2. See Application note “STM32 microcontroller system memory
boot mode” (AN2606) for details.
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3.4 Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
– 1-24 MHz high-speed external crystal (HSE), that can supply a PLL
– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
•Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE)
– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
•USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
•Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
•Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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