STMicroelectronics STM32F031F4 User manual

This is information on a product in full production.
August 2015 DocID025743 Rev 3 1/113
STM32F031x4 STM32F031x6
ARM®-based 32-bit MCU with up to 32 Kbyte Flash, timers,
ADC and communication interfaces, 2.0 - 3.6 V
Datasheet -production data
Features
Core: ARM®32-bit Cortex®-M0 CPU,
frequency up to 48 MHz
Memories
– 16 to 32 Kbytes of Flash memory
– 4 Kbytes of SRAM with HW parity
CRC calculation unit
Reset and power management
– Digital and I/Os supply: 2.0 to 3.6 V
– Analog supply: VDDA = from VDD to 3.6 V
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop and
Standby
–V
BAT supply for RTC and backup registers
Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
Up to 39 fast I/Os
– All mappable on external interrupt vectors
– Up to 25 I/Os with 5 V tolerant capability
5-channel DMA controller
1 × 12-bit, 1.0 µs ADC (up to 10 channels)
– Conversion range: 0 to 3.6V
– Separate analog supply from 2.4 up to
3.6 V
Up to 9 timers
– 1 x 16-bit 7-channel advanced-control timer
for 6 channels PWM output, with deadtime
generation and emergency stop
– 1 x 32-bit and 1 x 16-bit timer, with up to 4
IC/OC, usable for IR control decoding
– 1 x 16-bit timer, with 2 IC/OC, 1 OCN,
deadtime generation and emergency stop
– 1 x 16-bit timer, with IC/OC and OCN,
deadtime generation, emergency stop and
modulator gate for IR control
– 1 x 16-bit timer with 1 IC/OC
– Independent and system watchdog timers
– SysTick timer: 24-bit downcounter
Calendar RTC with alarm and periodic wakeup
from Stop/Standby
Communication interfaces
– 1 x I2C interface; supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus, and wakeup from Stop
mode
– 1 x USART supporting master synchronous
SPI and modem control; one with ISO7816
interface, LIN, IrDA capability auto baud
rate detection and wakeup feature
– 1 x SPI (18 Mbit/s) with 4 to 16
programmable bit frames, with I2S interface
multiplexed
Serial wire debug (SWD)
96-bit unique ID
Extended temperature range: -40 to +105°C
All packages ECOPACK®2
Table 1. Device summary
Reference Part number
STM32F031x4 STM32F031C4, STM32F031F4,
STM32F031G4, STM32F031K4
STM32F031x6 STM32F031C6, STM32F031E6, STM32F031F6, STM32F031G6,
STM32F031K6
UFQFPN32 5x5 mm TSSOP20
UFQFPN28 4x4 mm
LQFP32 7x7 mm
LQFP48 7x7 mm WLCSP25
(2.1x2.1 mm)
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Contents STM32F031x4 STM32F031x6
2/113 DocID025743 Rev 3
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 ARM®-Cortex®-M0 core with embedded Flash and SRAM . . . . . . . . . . . 12
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11.2 General-purpose timers (TIM2..3, TIM14, 16, 17) . . . . . . . . . . . . . . . . . 19
3.11.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14 Universal synchronous/asynchronous receiver transmitters (USART) . . 22
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DocID025743 Rev 3 3/113
STM32F031x4 STM32F031x6 Contents
4
3.15 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 23
3.16 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 43
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.17 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.18 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.19 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Contents STM32F031x4 STM32F031x6
4/113 DocID025743 Rev 3
6.3.20 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.1 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.3 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.4 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.5 WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.6 WLCSP25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.7 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 107
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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DocID025743 Rev 3 5/113
STM32F031x4 STM32F031x6 List of tables
6
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F031x4/x6 family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 10
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Comparison of I2C analog and digital filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. STM32F031x4/x6 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. STM32F031x4/x6 USART implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. STM32F031x4/x6 SPI/I2S implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 11. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 12. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 32
Table 13. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 33
Table 14. STM32F031x4/x6 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 22. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. Typical and maximum current consumption from the VDD supply at VDD = 3.6 V . . . . . . . 46
Table 24. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 47
Table 25. Typical and maximum current consumption in Stop and Standby modes . . . . . . . . . . . . 48
Table 26. Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 49
Table 27. Typical current consumption, code executing from Flash, 
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 29. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 30. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 32. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 33. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 34. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 35. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 36. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 37. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 38. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 39. Flash memory characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 40. Flash memory endurance and data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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List of tables STM32F031x4 STM32F031x6
6/113 DocID025743 Rev 3
Table 48. I/O AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 50. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 51. RAIN max for fADC = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 52. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 53. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 54. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 55. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 56. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 57. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 58. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 59. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 60. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 61. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package 
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 62. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package 
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 63. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat 
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 64. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 65. WLCSP25 - 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 66. WLCSP25 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 101
Table 67. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, 
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 68. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 69. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 70. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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STM32F031x4 STM32F031x6 List of figures
8
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. LQFP48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4. LQFP32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5. UFQFPN32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6. UFQFPN28 28-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. WLCSP25 25-ball package ballout (bump side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. TSSOP20 20-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. STM32F031x4/x6 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 16. Typical application with an 8 MHz crystal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 18. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 62
Figure 19. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 20. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 24. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 25. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 27. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 28. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 29. I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 31. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 87
Figure 32. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package 
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 33. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 34. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 91
Figure 35. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package 
recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 36. LQFP32 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 37. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 38. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat 
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 39. UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 40. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 41. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat 
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 42. UFQFPN28 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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List of figures STM32F031x4 STM32F031x6
8/113 DocID025743 Rev 3
Figure 43. WLCSP25 - 25-ball, 2.423 x 2.325 mm, 0.4 mm pitch wafer level chip scale 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 44. WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 45. WLCSP25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 46. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, 
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 48. TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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DocID025743 Rev 3 9/113
STM32F031x4 STM32F031x6 Introduction
23
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F031x4/x6 microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM®Cortex®-M0 core, please refer to the Cortex®-M0 Technical
Reference Manual, available from the www.arm.com website.
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Description STM32F031x4 STM32F031x6
10/113 DocID025743 Rev 3
2 Description
The STM32F031x4/x6 microcontrollers incorporate the high-performance ARM®Cortex®-
M0 32-bit RISC core operating at a 48 MHz maximum frequency, high-speed embedded
memories (up to 32 Kbytes of Flash memory and 4 Kbytes of SRAM), and an extensive
range of enhanced peripherals and I/Os. All devices offer standard communication
interfaces (one I2C, one SPI/ I2S and one USART), one 12-bit ADC, five 16-bit timers, one
32-bit timer and an advanced-control PWM timer.
The STM32F031x4/x6 microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of power-
saving modes allows the design of low-power applications.
The STM32F031x4/x6 microcontrollers include devices in six different packages ranging
from 20 pins to 48 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included. The description below provides an
overview of the complete range of STM32F031x4/x6 peripherals proposed.
These features make the STM32F031x4/x6 microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
Table 2. STM32F031x4/x6 family device features and peripheral counts
Peripheral STM32F031Fx STM32F031Ex STM32F031Gx STM32F031Kx STM32F031Cx
Flash (Kbyte) 16 32 32 16 32 16 32 16 32
SRAM (Kbyte) 4
Timers
Advanced
control 1 (16-bit)
General
purpose 4 (16-bit)
1 (32-bit)
Comm.
interfaces
SPI [I2S](1) 1 [1]
I2C1
USART 1
12-bit ADC 
(number of channels) 1 (9 ext. + 3 int.) 1 (10 ext. + 3 int.)
GPIOs 15 20 23 25 (on LQFP32)
27 (on UFQFPN32) 39
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient operating temperature: -40°C to 85°C / -40°C to 105°C
Junction temperature: -40°C to 105°C / -40°C to 125°C
Packages TSSOP20 WLCSP25 UFQFPN28 LQFP32
UFQFPN32 LQFP48
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
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DocID025743 Rev 3 11/113
STM32F031x4 STM32F031x6 Description
23
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Functional overview STM32F031x4 STM32F031x6
12/113 DocID025743 Rev 3
3 Functional overview
3.1 ARM®-Cortex®-M0 core with embedded Flash and SRAM
The ARM®Cortex®-M0 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM®Cortex®-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F0xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2 Memories
The device has the following features:
4 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
The non-volatile memory is divided into two arrays:
– 16 to 32 Kbytes of embedded Flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
– Level 2: chip readout protection, debug features (Cortex®-M0 serial wire) and
boot in RAM selection disabled
3.3 Boot modes
At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART on pins PA14/PA15 or PA9/PA10.
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STM32F031x4 STM32F031x6 Functional overview
23
3.4 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes
VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal
regulator. It is provided externally through VDD pins.
VDDA = from VDD to 3.6 V: external analog power supply for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). It is
provided externally through VDDA pin. The VDDA voltage level must be always greater
or equal to the VDD voltage level and must be established first.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 12: Power supply scheme.
3.5.2 Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3 Voltage regulator
The regulator has two operating modes and it is always enabled after reset.
Main (MR) is used in normal operating mode (Run).
Low power (LPR) can be used in Stop mode where the power demand is reduced.
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In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4 Low-power modes
The STM32F031x4/x6 microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1 or USART1.
The peripherals listed above can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used when the voltage regulator is put in low power
mode, the regulator is first switched to normal mode before the clock is provided to the
given peripheral.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.6 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
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STM32F031x4 STM32F031x6 Functional overview
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3.7 General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8 Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14) and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M0) and 4
priority levels.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2 Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 39
GPIOs can be connected to the 16 external interrupt lines.
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3.10 Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.10.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name Description Memory address
TS_CAL1 TS ADC raw data acquired at a temperature of 30 °C (5 °C),
VDDA= 3.3 V (10 mV) 0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2 TS ADC raw data acquired at a temperature of 110 °C (5 °C),
VDDA= 3.3 V (10 mV) 0x1FFF F7C2 - 0x1FFF F7C3
Table 4. Internal voltage reference calibration values
Calibration value name Description Memory address
VREFINT_CAL Raw data acquired at a temperature of 30 °C (5 °C),
VDDA= 3.3 V (10 mV) 0x1FFF F7BA - 0x1FFF F7BB
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3.10.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application tomeasure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.11 Timers and watchdogs
The STM32F031x4/x6 devices include up to five general-purpose timers and an advanced
control timer.
Table 5 compares the features of the different timers.
3.11.1 Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
Input capture
Output compare
PWM generation (edge or center-aligned modes)
One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Table 5. Timer feature comparison
Timer
type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/compare channels Complementary outputs
Advanced
control TIM1 16-bit Up,
down,
up/down
Any integer
between 1
and 65536 Yes 4 3
General
purpose
TIM2 32-bit Up, down,
up/down
Any integer
between 1
and 65536 Yes 4 No
TIM3 16-bit Up, down,
up/down
Any integer
between 1
and 65536 Yes 4 No
TIM14 16-bit Up Any integer between 1
and 65536 No 1 No
TIM16,
TIM17 16-bit Up Any integer
between 1
and 65536 Yes 1 1
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Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.11.2 General-purpose timers (TIM2..3, TIM14, 16, 17)
There are six synchronizable general-purpose timers embedded in the STM32F031x4/x6
devices (see Table 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F031x4/x6 devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
They each have a single channel for input capture/output compare, PWM or one-pulse
mode output.
TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
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3.11.3 Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.11.4 System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
3.11.5 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
A 24-bit down counter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source (HCLK or HCLK/8)
3.12 Real-time clock (RTC) and backup registers
The RTC and the five backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 day of the month.
Programmable alarm with wake up from Stop and Standby mode capability.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
Two anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
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