Sun Microsystems 2060 Installation and operation manual

Hardware Engineering Manual
for tIle
2060 CPU Board
C011fidential andProprz"etalY Material
Sun Microsystems, Inc. •2550 Garcia Avenue •Mountain View, CA 94043 •415-960-1300
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Part No: 800-1386-13
{Rev 1 of 10 May 1987} CONFIDENTIAL!

Acknowledgements
Sun Microsystems and Sun Workstation are
registered trademarks
of Sun Microsystems, Incorporated.
Sun-3, Sun-3/xxx, Deskside,
SunStation,
SunCore,
Sun Windows, and DVMA are trademarks of Sun Microsystems,
Incorporated.
UNIX is aregistered trademark
of Bell Laboratories.
Multibus is atrademark of Intel Corporation
Thanks to Karl Bizjak, Joe Murphy, Jim Ludemann, Bruce
Smith, Kevin Mobley, and Niel Hanes, without whose explanation
and assistance this manual would never have been written.
Copyright ©1987 by Sun Microsystems, Inc.
This publication is protected by Federal Copyright Law, with all rights reserved.
No part
of this publication may be reproduced, stored in aretrieval system,
translated, transcribed,
or transmitted, in any fonn, or by any means manual,
electric, electronic, electro-magnetic, mechanical, chemical, optical,
or other-
wise, without priorexplicit written permission from Sun Microsystems.

Contents
Preface xxiii
Chapter 1 An OvelView of the Sun-3 Architecture 3
1.1. CPU 3
1.2. System DVMA 3
1.3. V!\1E Slave User DVMA 3
1.4. Refresh 4
1.5. DVMA Controller 4
1.6. Control Space Devices -FC3 4
1.7. Memory Management Unit 4
1.8. Device space 4
1.9. Memory Space (TYPED space) 5
Parity Main Memory 5
Video Memory 5
1.10. I/O Devices (TYPEI space) 5
1.11. V!\1E Master (TYPE2 and TYPE3 Space) 6
1.12. Interrupts 6
On- Board Interrupts __ 6
Vl\.ffi Vectored Interrupts _ _...... 7
1.13. CPU Resets and Timeout _................................ 7
Chapter 2VME ComplIance _ _.................... 11
2.1. Options _..................... 11
2.2. PerfoIlIlance Parameters _ _........ 11
- iii-

Contents -Continued
Chapter 3Block Diagram 15
3.1. Data Patlls 16
Chapter 4Mechanical Specifications 19
4.1. Board Fonn Factor 19
4.2. Connectors 19
4.3. Switches 19
Chapter 568020,68881 Floating Point Coprocessor, and
Associated Circuitry 23
5.1. Processor Data Buffers -UI05:2 23
U105:2 Data Flow 23
5.2. Cache Disable -J100 23
5.3. CPU Space PALs -U106 and U10? 24
5.4. U1tJ6 PAL 26
U106 Input Signals
26
U106 Output Signals 27
5.5. UIO? PAL 30
UIO? Input Signals
31
UIO? Output Signals 31
Chapter 6 Power-on Circuitry 37
Chapter 7Response Synchronizer-U206 41
Chapter 8Reset Pal U201 and User Reset Switch U205 45
8.1. U205 UserReset Switch 45
8.2. U201 Reset PAL 46
U201 Input Signals 46
U201 Output Signals 4?
Chapter 9U202 and U203 Bus Error PAL and Register 51
9.1. U202 Inputs 51
9.2. Pinout ofU202 PAL 52
-iv -

Contents - Continued
9.3. U202 Output Signals 53
9.4. U203 Bus Error Register 56
Chapter 10 U204 DSACK PAL 59
10.1. Pinout ofU2()4 PAL 59
10.2. U2()4 Input Signals 60
Bus Transfer Size 60
Offset Bits 60
10.3.
U2()4 Outputs 62
Chapter 11 Interrupt Circuitry -U301 :U300, J300 67
11.1. Interrupt Priority 67
11.2. U301:0 Interrupt Enable Registers 68
11.3. J300 ::~.................................................................................... 69
Chapter 12 Interrupt Circuitry -U302-U304 PALs, U305
Register 73
12.1. Interrupt Request Cycle 73
12.2. Interrupt Acknowledge Cycle
74
12.3. Priority 77
12.4. Two-Level Priority Encoding 77
12.5. U302 Lower-Priority Encoder 78
U302 Pinout 79
U302 Input Signals 79
U302 Output Signals
80
12.6. U303 Higher-Priority Encoder 84
U303 Pinout 84
U303 Input Signals 84
U303 Output Signals 85
12.7. Second-Level Interrupt Priority Encoder-U3()4 89
Pinout of U3()4 PAL 89
U3()4 Input SigIlals 90
U304 Output SigIlals 90
Sample Interrupt Cycle 92
-\'-

Contents -Continued
Spurious Interrupt 92
Ethernet Controller and Spurious Interrupts 93
12.8. U30S Latch 94
Chapter 13 ATE Pulldowns -U407 97
Chapter 14 Clock Generation -U400-U406 101
14.1. Pinout ofU400 Oock PAL 101
14.2. U400 Input SigJlals 102
14.3. U400 Output Signals 103
14.4. U401 Flip-Flops 1()4
14.S. U402 Flip-Flops lQ.4
Chapter 15 Pal U408 107
IS.I. Pinout ofU408 PAL 107
Chapter 16 Sun-3 Memory Management Unit (MMU) 111
Chapter 17 Context Register -U509 115
17.1. US09Pinout 116
17.2. US09 Input Signals 116
17.3. US09 Output Signals 117
Chapter 18 Segment Map -U500:08 121
18.1. Segment Map Read and Write Cycles 122
Segment
Map RAM Read Cycle 122
Segment Map
RAM Write Cycle 123
Truth Table for the US08 Buffer 123
18.2. Segment Map
RAM Control Signals 123
Chapter 19 Page Map RAM 127
Chapter 20 Statistics Control PAL-U611 133
20.1. U611 Input Signals 133
-vi-

Contents -Continued
20.2. U611 Output Signals 134
Chapter 21 MMU Validation and Decode PAL -U612 139
21.1. U612 Input Signals .. _.................................................................................................. 139
21.2. U612 Output Signals 140
Chapter 22 P2 Bus Control and Address Buffers 147
22.1. U700 Comparator 147
22.2. U703:01
P2 Address Buffers 147
22.3. U704 Control Signal Buffer 148
22.4. Aliases
14S
Chapter 23 Parity Circuitry 151
23.1. Parity Address Latch -U811:08 15]
23.2. Parity Generator/Checkers -U807:04
151
23.3. U803 Multiplexer 152
23.4. Parity Control and Parity Check PALs -U802 and U812 152
23.5. U812 Parity Check PAL 153
U812 Input Signals
153
U812 Output Signals 153
23.6. U802 Parity Control PAL 156
U802 Input Signals 156
U802 Output Signals 157
Pinout
of U802 PAL 159
23.7. Memory
ErrorRegister-U801 161
23.8. Byte Select Buffer (and Address Bit Driver) -U813 162
23.9. Parity Data Buffer- U3112 162
Chapter 24 MOS Bus Devices 165
24.1. U5KXJ MOS Enables PAL 166
U5KXJ Pinout 167
U5KXJ MOS Write Enable -moswren 167
U5KXJ MOS Read Enable-mosrden 168
Diagnostic Cycle -diagcy 169
- vii-

Contents -Continued
24.2. U901 MOS SACK State Machine 169
Pinout
of U901 PAL 170
U901 MOS Read/Write Control 172
U901 SCC Interrupt- SYNCW AIT State 176
24.3. U904
MOS Read/Write Strobe Decoder 179
U904 Pinout 179
U904·Input SigIlals 180
U904 Output SigIlals 180
24.4. U902 MOS Write
ana U903 MOS Read Buffers 184
U902 MOS Write Buffer 184
U903 MOS Read Buffer 184
24.5. MOS Read and Write Cycles 185
MOS Read Cycle 186
MOS Write Cycle 186
24.6. Mouse and Keyboard SCC 186
U405 and U2207 Baud Rate Clock 187
Transmit Data Path 187
Receive Data Path 187
24.7. Serial Ports Aand B - ttya and
nyb 187
Transmit Data Path 188
Receive Data Path 188
24.8.
EEPROM aIld EPROM 188
EEPROM 190
EPROM 190
24.9. Time
of Day (TOD) Dock 190
TOD Oscillator Circuit 190
Chapter 25 TTL Bus Accesses 195
25.1. TIL Bus Read/Write Cycle 195
25.2. U1400 'ITL
Bus Sack State Machine 195
U1400 Pioout _
_........................................................................ 196
U1400 State Machine Outputs 196
'ITL Bus DTACK State Machine Diagram 198
- viii-

Contents -Continued
TTL Bus Cycle Timing 203
25.3. U
1401 TTL Bus Device Decoder 204
U1401 PiIlOut 205
U1401 Input Sigrtals
:.............................. 205
Output Signals
of the Ul401 PAL 206
25.4. U1402 MMU Decoder 210
U1402
PiIlOut 212
U1402 Input Signals 21 2
U1402 Output Sigrtals 213
25.5. U1403 (MIscellaneous) CPU Signal
TTL Bus Decoder 218
PinoutofUI403PAL 219
U1403 Input Signals 219
U1403 Output Signals 220
25.6. Ethernet Control Register 223
U1405 Ethernet Control Write Buffer 223
U1407 Ethernet Control Read Buffer 224
25.7. System Enable Register 224
U1406 System Enable Write Register 224
U1408 System Enable Read Register 225
25.8. U1410 Diagnostics Register 225
25.9. U1409 ID PROM 225
25.10. U1404 P2-to-TTL Data Buffer 225
25.11. U2905 and U2906 UserDVMA Enable Register 226
25.12. U203 Bus ErrorRegister 226
25.13. U509 Context Register 226
U509 Pinout 227
Inputs and Outputs
of U509 Context Register 227
Chapter 26 Video Circuitry 233
26.1. Video Cycle Timing 233
26.2. U1504 Video Select
DecOOer 234
U1504 Pioout 235
U1504 Input and Output signals 235
-ix-

Contents -Continued
26.3. U1502 Video Control Decoder 236
U1502 Pioout 237
U1502 Inpllt Signals 237
U1502 Output Sigtlals 237
26.4.
P2 Interface State Machine -U1503, Ul605/07 241
U1503 Pinout 241
U1503 Inl"lts 241
U1503 Outputs 242
26.5. VARB and Video Side State Machines 242
Video Read 243
Video Write 247
Video Write Timing Diagrams: AReal Example 249
26.6. U1501 Byte Decode
PAL 250
V1501 Pinout 250
V1501 Output signals 251
V1500 Buffer and U1505 DIP 253
26.7.
Ul608-UI603 Video Controller 253
26.8. V17oo-01 Video RAS/CAS Latches 254
26.9. Frame Buffer
RM1 255
26.10.
ECL Circuitry 256
ECL Oock 256
26.11. Horizontal and Vertical Synch State Machines 257
Chapter 27 VMEbus -Perfonnance 263
27.1. 2060 VtviE Implementation 263
Chapter 28 VME Arbiter and Requester 269
28.1. Tenninology for VME Arbiterand Requester 269
28.2. U2704
VME Arbiter and Requester 271
State Machine as Arbiter and Requester 272
Transitions from
BUSREQ State 273
Transitions from
MASTER State 274
Transitions from
MASTER_NG State 276
-)(-